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7d0f2f23 | 1 | /** @file\r |
2 | \r | |
3 | Copyright (c) 2011, ARM Ltd. All rights reserved.<BR>\r | |
4 | This program and the accompanying materials\r | |
5 | are licensed and made available under the terms and conditions of the BSD License\r | |
6 | which accompanies this distribution. The full text of the license may be found at\r | |
7 | http://opensource.org/licenses/bsd-license.php\r | |
8 | \r | |
9 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
10 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
11 | \r | |
12 | **/\r | |
13 | \r | |
14 | #ifndef __LCDPLATFORMLIB_H\r | |
15 | #define __LCDPLATFORMLIB_H\r | |
16 | \r | |
17 | #include <Protocol/GraphicsOutput.h>\r | |
18 | \r | |
19 | #define LCD_VRAM_SIZE SIZE_8MB\r | |
20 | \r | |
21 | //\r | |
22 | // Modes definitions\r | |
23 | //\r | |
24 | #define VGA 0\r | |
25 | #define SVGA 1\r | |
26 | #define XGA 2\r | |
27 | #define SXGA 3\r | |
beeb44f4 | 28 | #define WSXGA 4\r |
29 | #define UXGA 5\r | |
30 | #define HD 6\r | |
7d0f2f23 | 31 | \r |
32 | //\r | |
33 | // VGA Mode: 640 x 480\r | |
34 | //\r | |
35 | #define VGA_H_RES_PIXELS 640\r | |
36 | #define VGA_V_RES_PIXELS 480\r | |
37 | #define VGA_OSC_FREQUENCY 23750000 /* 0x016A6570 */\r | |
38 | \r | |
39 | #define VGA_H_SYNC ( 80 - 1)\r | |
40 | #define VGA_H_FRONT_PORCH ( 16 - 1)\r | |
41 | #define VGA_H_BACK_PORCH ( 64 - 1)\r | |
42 | \r | |
43 | #define VGA_V_SYNC ( 4 - 1)\r | |
44 | #define VGA_V_FRONT_PORCH ( 3 - 1)\r | |
45 | #define VGA_V_BACK_PORCH ( 13 - 1)\r | |
46 | \r | |
47 | //\r | |
48 | // SVGA Mode: 800 x 600\r | |
49 | //\r | |
50 | #define SVGA_H_RES_PIXELS 800\r | |
51 | #define SVGA_V_RES_PIXELS 600\r | |
52 | #define SVGA_OSC_FREQUENCY 38250000 /* 0x0247A610 */\r | |
53 | \r | |
54 | #define SVGA_H_SYNC ( 80 - 1)\r | |
55 | #define SVGA_H_FRONT_PORCH ( 32 - 1)\r | |
56 | #define SVGA_H_BACK_PORCH (112 - 1)\r | |
57 | \r | |
58 | #define SVGA_V_SYNC ( 4 - 1)\r | |
59 | #define SVGA_V_FRONT_PORCH ( 3 - 1)\r | |
60 | #define SVGA_V_BACK_PORCH ( 17 - 1)\r | |
61 | \r | |
62 | //\r | |
63 | // XGA Mode: 1024 x 768\r | |
64 | //\r | |
65 | #define XGA_H_RES_PIXELS 1024\r | |
66 | #define XGA_V_RES_PIXELS 768\r | |
67 | #define XGA_OSC_FREQUENCY 63500000 /* 0x03C8EEE0 */\r | |
68 | \r | |
69 | #define XGA_H_SYNC (104 - 1)\r | |
70 | #define XGA_H_FRONT_PORCH ( 48 - 1)\r | |
71 | #define XGA_H_BACK_PORCH (152 - 1)\r | |
72 | \r | |
73 | #define XGA_V_SYNC ( 4 - 1)\r | |
74 | #define XGA_V_FRONT_PORCH ( 3 - 1)\r | |
75 | #define XGA_V_BACK_PORCH ( 23 - 1)\r | |
76 | \r | |
77 | //\r | |
78 | // SXGA Mode: 1280 x 1024\r | |
79 | //\r | |
80 | #define SXGA_H_RES_PIXELS 1280\r | |
81 | #define SXGA_V_RES_PIXELS 1024\r | |
82 | #define SXGA_OSC_FREQUENCY 109000000 /* 0x067F3540 */\r | |
83 | \r | |
84 | #define SXGA_H_SYNC (136 - 1)\r | |
85 | #define SXGA_H_FRONT_PORCH ( 80 - 1)\r | |
86 | #define SXGA_H_BACK_PORCH (216 - 1)\r | |
87 | \r | |
88 | #define SXGA_V_SYNC ( 7 - 1)\r | |
89 | #define SXGA_V_FRONT_PORCH ( 3 - 1)\r | |
90 | #define SXGA_V_BACK_PORCH ( 29 - 1)\r | |
91 | \r | |
beeb44f4 | 92 | //\r |
93 | // WSXGA+ Mode: 1680 x 1050\r | |
94 | //\r | |
95 | #define WSXGA_H_RES_PIXELS 1680\r | |
96 | #define WSXGA_V_RES_PIXELS 1050\r | |
97 | #define WSXGA_OSC_FREQUENCY 147000000 /* 0x08C30AC0 */\r | |
98 | \r | |
99 | #define WSXGA_H_SYNC (170 - 1)\r | |
100 | #define WSXGA_H_FRONT_PORCH (104 - 1)\r | |
101 | #define WSXGA_H_BACK_PORCH (274 - 1)\r | |
102 | \r | |
103 | #define WSXGA_V_SYNC ( 5 - 1)\r | |
104 | #define WSXGA_V_FRONT_PORCH ( 4 - 1)\r | |
105 | #define WSXGA_V_BACK_PORCH ( 41 - 1)\r | |
106 | \r | |
7d0f2f23 | 107 | //\r |
108 | // UXGA Mode: 1600 x 1200\r | |
109 | //\r | |
110 | #define UXGA_H_RES_PIXELS 1600\r | |
111 | #define UXGA_V_RES_PIXELS 1200\r | |
112 | #define UXGA_OSC_FREQUENCY 161000000 /* 0x0998AA40 */\r | |
113 | \r | |
114 | #define UXGA_H_SYNC (168 - 1)\r | |
115 | #define UXGA_H_FRONT_PORCH (112 - 1)\r | |
116 | #define UXGA_H_BACK_PORCH (280 - 1)\r | |
117 | \r | |
118 | #define UXGA_V_SYNC ( 4 - 1)\r | |
119 | #define UXGA_V_FRONT_PORCH ( 3 - 1)\r | |
120 | #define UXGA_V_BACK_PORCH ( 38 - 1)\r | |
121 | \r | |
122 | //\r | |
123 | // HD Mode: 1920 x 1080\r | |
124 | //\r | |
125 | #define HD_H_RES_PIXELS 1920\r | |
126 | #define HD_V_RES_PIXELS 1080\r | |
deb8a061 | 127 | #define HD_OSC_FREQUENCY 165000000 /* 0x09D5B340 */\r |
7d0f2f23 | 128 | \r |
deb8a061 | 129 | #define HD_H_SYNC ( 79 - 1)\r |
7d0f2f23 | 130 | #define HD_H_FRONT_PORCH (128 - 1)\r |
131 | #define HD_H_BACK_PORCH (328 - 1)\r | |
132 | \r | |
133 | #define HD_V_SYNC ( 5 - 1)\r | |
134 | #define HD_V_FRONT_PORCH ( 3 - 1)\r | |
135 | #define HD_V_BACK_PORCH ( 32 - 1)\r | |
136 | \r | |
137 | //\r | |
138 | // Colour Masks\r | |
139 | //\r | |
140 | \r | |
141 | #define LCD_24BPP_RED_MASK 0x00FF0000\r | |
142 | #define LCD_24BPP_GREEN_MASK 0x0000FF00\r | |
143 | #define LCD_24BPP_BLUE_MASK 0x000000FF\r | |
144 | #define LCD_24BPP_RESERVED_MASK 0xFF000000\r | |
145 | \r | |
146 | #define LCD_16BPP_555_RED_MASK 0x00007C00\r | |
147 | #define LCD_16BPP_555_GREEN_MASK 0x000003E0\r | |
148 | #define LCD_16BPP_555_BLUE_MASK 0x0000001F\r | |
149 | #define LCD_16BPP_555_RESERVED_MASK 0x00000000\r | |
150 | \r | |
151 | #define LCD_16BPP_565_RED_MASK 0x0000F800\r | |
152 | #define LCD_16BPP_565_GREEN_MASK 0x000007E0\r | |
153 | #define LCD_16BPP_565_BLUE_MASK 0x0000001F\r | |
154 | #define LCD_16BPP_565_RESERVED_MASK 0x00008000\r | |
155 | \r | |
156 | #define LCD_12BPP_444_RED_MASK 0x00000F00\r | |
157 | #define LCD_12BPP_444_GREEN_MASK 0x000000F0\r | |
158 | #define LCD_12BPP_444_BLUE_MASK 0x0000000F\r | |
159 | #define LCD_12BPP_444_RESERVED_MASK 0x0000F000\r | |
160 | \r | |
161 | \r | |
162 | // The enumeration indexes maps the PL111 LcdBpp values used in the LCD Control Register\r | |
163 | typedef enum {\r | |
164 | LCD_BITS_PER_PIXEL_1 = 0,\r | |
165 | LCD_BITS_PER_PIXEL_2,\r | |
166 | LCD_BITS_PER_PIXEL_4,\r | |
167 | LCD_BITS_PER_PIXEL_8,\r | |
168 | LCD_BITS_PER_PIXEL_16_555,\r | |
169 | LCD_BITS_PER_PIXEL_24,\r | |
170 | LCD_BITS_PER_PIXEL_16_565,\r | |
171 | LCD_BITS_PER_PIXEL_12_444\r | |
172 | } LCD_BPP;\r | |
173 | \r | |
174 | \r | |
175 | EFI_STATUS\r | |
176 | LcdPlatformInitializeDisplay (\r | |
6d8d7363 | 177 | IN EFI_HANDLE Handle\r |
7d0f2f23 | 178 | );\r |
179 | \r | |
180 | EFI_STATUS\r | |
181 | LcdPlatformGetVram (\r | |
182 | OUT EFI_PHYSICAL_ADDRESS* VramBaseAddress,\r | |
183 | OUT UINTN* VramSize\r | |
184 | );\r | |
185 | \r | |
186 | UINT32\r | |
187 | LcdPlatformGetMaxMode (\r | |
188 | VOID\r | |
189 | );\r | |
190 | \r | |
191 | EFI_STATUS\r | |
192 | LcdPlatformSetMode (\r | |
193 | IN UINT32 ModeNumber\r | |
194 | );\r | |
195 | \r | |
196 | EFI_STATUS\r | |
197 | LcdPlatformQueryMode (\r | |
198 | IN UINT32 ModeNumber,\r | |
199 | OUT EFI_GRAPHICS_OUTPUT_MODE_INFORMATION *Info\r | |
200 | );\r | |
201 | \r | |
202 | EFI_STATUS\r | |
203 | LcdPlatformGetTimings (\r | |
204 | IN UINT32 ModeNumber,\r | |
205 | OUT UINT32* HRes,\r | |
206 | OUT UINT32* HSync,\r | |
207 | OUT UINT32* HBackPorch,\r | |
208 | OUT UINT32* HFrontPorch,\r | |
209 | OUT UINT32* VRes,\r | |
210 | OUT UINT32* VSync,\r | |
211 | OUT UINT32* VBackPorch,\r | |
212 | OUT UINT32* VFrontPorch\r | |
213 | );\r | |
214 | \r | |
215 | EFI_STATUS\r | |
216 | LcdPlatformGetBpp (\r | |
217 | IN UINT32 ModeNumber,\r | |
218 | OUT LCD_BPP* Bpp\r | |
219 | );\r | |
220 | \r | |
221 | #endif\r |