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1 | /** @file\r |
2 | *\r | |
3 | * Copyright (c) 2011-2016, ARM Limited. All rights reserved.\r | |
4 | *\r | |
f4dfad05 | 5 | * SPDX-License-Identifier: BSD-2-Clause-Patent\r |
12156134 AB |
6 | *\r |
7 | **/\r | |
8 | \r | |
9 | #ifndef __PL011_UART_H__\r | |
10 | #define __PL011_UART_H__\r | |
11 | \r | |
12 | #define PL011_VARIANT_ZTE 1\r | |
13 | \r | |
14 | // PL011 Registers\r | |
15 | #if FixedPcdGet8 (PL011UartRegOffsetVariant) == PL011_VARIANT_ZTE\r | |
16 | #define UARTDR 0x004\r | |
17 | #define UARTRSR 0x010\r | |
18 | #define UARTECR 0x010\r | |
19 | #define UARTFR 0x014\r | |
20 | #define UARTIBRD 0x024\r | |
21 | #define UARTFBRD 0x028\r | |
22 | #define UARTLCR_H 0x030\r | |
23 | #define UARTCR 0x034\r | |
24 | #define UARTIFLS 0x038\r | |
25 | #define UARTIMSC 0x040\r | |
26 | #define UARTRIS 0x044\r | |
27 | #define UARTMIS 0x048\r | |
28 | #define UARTICR 0x04c\r | |
29 | #define UARTDMACR 0x050\r | |
30 | #else\r | |
31 | #define UARTDR 0x000\r | |
32 | #define UARTRSR 0x004\r | |
33 | #define UARTECR 0x004\r | |
34 | #define UARTFR 0x018\r | |
35 | #define UARTILPR 0x020\r | |
36 | #define UARTIBRD 0x024\r | |
37 | #define UARTFBRD 0x028\r | |
38 | #define UARTLCR_H 0x02C\r | |
39 | #define UARTCR 0x030\r | |
40 | #define UARTIFLS 0x034\r | |
41 | #define UARTIMSC 0x038\r | |
42 | #define UARTRIS 0x03C\r | |
43 | #define UARTMIS 0x040\r | |
44 | #define UARTICR 0x044\r | |
45 | #define UARTDMACR 0x048\r | |
46 | #endif\r | |
47 | \r | |
48 | #define UARTPID0 0xFE0\r | |
49 | #define UARTPID1 0xFE4\r | |
50 | #define UARTPID2 0xFE8\r | |
51 | #define UARTPID3 0xFEC\r | |
52 | \r | |
53 | // Data status bits\r | |
54 | #define UART_DATA_ERROR_MASK 0x0F00\r | |
55 | \r | |
56 | // Status reg bits\r | |
57 | #define UART_STATUS_ERROR_MASK 0x0F\r | |
58 | \r | |
59 | // Flag reg bits\r | |
60 | #if FixedPcdGet8 (PL011UartRegOffsetVariant) == PL011_VARIANT_ZTE\r | |
61 | #define PL011_UARTFR_RI (1 << 0) // Ring indicator\r | |
62 | #define PL011_UARTFR_TXFE (1 << 7) // Transmit FIFO empty\r | |
63 | #define PL011_UARTFR_RXFF (1 << 6) // Receive FIFO full\r | |
64 | #define PL011_UARTFR_TXFF (1 << 5) // Transmit FIFO full\r | |
65 | #define PL011_UARTFR_RXFE (1 << 4) // Receive FIFO empty\r | |
66 | #define PL011_UARTFR_BUSY (1 << 8) // UART busy\r | |
67 | #define PL011_UARTFR_DCD (1 << 2) // Data carrier detect\r | |
68 | #define PL011_UARTFR_DSR (1 << 3) // Data set ready\r | |
69 | #define PL011_UARTFR_CTS (1 << 1) // Clear to send\r | |
70 | #else\r | |
71 | #define PL011_UARTFR_RI (1 << 8) // Ring indicator\r | |
72 | #define PL011_UARTFR_TXFE (1 << 7) // Transmit FIFO empty\r | |
73 | #define PL011_UARTFR_RXFF (1 << 6) // Receive FIFO full\r | |
74 | #define PL011_UARTFR_TXFF (1 << 5) // Transmit FIFO full\r | |
75 | #define PL011_UARTFR_RXFE (1 << 4) // Receive FIFO empty\r | |
76 | #define PL011_UARTFR_BUSY (1 << 3) // UART busy\r | |
77 | #define PL011_UARTFR_DCD (1 << 2) // Data carrier detect\r | |
78 | #define PL011_UARTFR_DSR (1 << 1) // Data set ready\r | |
79 | #define PL011_UARTFR_CTS (1 << 0) // Clear to send\r | |
80 | #endif\r | |
81 | \r | |
82 | // Flag reg bits - alternative names\r | |
83 | #define UART_TX_EMPTY_FLAG_MASK PL011_UARTFR_TXFE\r | |
84 | #define UART_RX_FULL_FLAG_MASK PL011_UARTFR_RXFF\r | |
85 | #define UART_TX_FULL_FLAG_MASK PL011_UARTFR_TXFF\r | |
86 | #define UART_RX_EMPTY_FLAG_MASK PL011_UARTFR_RXFE\r | |
87 | #define UART_BUSY_FLAG_MASK PL011_UARTFR_BUSY\r | |
88 | \r | |
89 | // Control reg bits\r | |
90 | #define PL011_UARTCR_CTSEN (1 << 15) // CTS hardware flow control enable\r | |
91 | #define PL011_UARTCR_RTSEN (1 << 14) // RTS hardware flow control enable\r | |
92 | #define PL011_UARTCR_RTS (1 << 11) // Request to send\r | |
93 | #define PL011_UARTCR_DTR (1 << 10) // Data transmit ready.\r | |
94 | #define PL011_UARTCR_RXE (1 << 9) // Receive enable\r | |
95 | #define PL011_UARTCR_TXE (1 << 8) // Transmit enable\r | |
96 | #define PL011_UARTCR_LBE (1 << 7) // Loopback enable\r | |
97 | #define PL011_UARTCR_UARTEN (1 << 0) // UART Enable\r | |
98 | \r | |
99 | // Line Control Register Bits\r | |
100 | #define PL011_UARTLCR_H_SPS (1 << 7) // Stick parity select\r | |
101 | #define PL011_UARTLCR_H_WLEN_8 (3 << 5)\r | |
102 | #define PL011_UARTLCR_H_WLEN_7 (2 << 5)\r | |
103 | #define PL011_UARTLCR_H_WLEN_6 (1 << 5)\r | |
104 | #define PL011_UARTLCR_H_WLEN_5 (0 << 5)\r | |
105 | #define PL011_UARTLCR_H_FEN (1 << 4) // FIFOs Enable\r | |
106 | #define PL011_UARTLCR_H_STP2 (1 << 3) // Two stop bits select\r | |
107 | #define PL011_UARTLCR_H_EPS (1 << 2) // Even parity select\r | |
108 | #define PL011_UARTLCR_H_PEN (1 << 1) // Parity Enable\r | |
109 | #define PL011_UARTLCR_H_BRK (1 << 0) // Send break\r | |
110 | \r | |
111 | #define PL011_UARTPID2_VER(X) (((X) >> 4) & 0xF)\r | |
112 | #define PL011_VER_R1P4 0x2\r | |
113 | \r | |
114 | #endif\r |