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12156134 AB |
1 | /** @file\r |
2 | Serial I/O Port library functions with no library constructor/destructor\r | |
3 | \r | |
4 | Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>\r | |
5 | Copyright (c) 2011 - 2016, ARM Ltd. All rights reserved.<BR>\r | |
6 | \r | |
f4dfad05 | 7 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
12156134 AB |
8 | \r |
9 | **/\r | |
10 | \r | |
11 | #include <Uefi.h>\r | |
12 | \r | |
13 | #include <Library/DebugLib.h>\r | |
14 | #include <Library/IoLib.h>\r | |
15 | #include <Library/PcdLib.h>\r | |
16 | \r | |
17 | #include <Protocol/SerialIo.h>\r | |
18 | \r | |
19 | #include "PL011Uart.h"\r | |
20 | \r | |
21 | #define FRACTION_PART_SIZE_IN_BITS 6\r | |
22 | #define FRACTION_PART_MASK ((1 << FRACTION_PART_SIZE_IN_BITS) - 1)\r | |
23 | \r | |
24 | //\r | |
25 | // EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE is the only\r | |
26 | // control bit that is not supported.\r | |
27 | //\r | |
28 | STATIC CONST UINT32 mInvalidControlBits = EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE;\r | |
29 | \r | |
30 | /**\r | |
31 | \r | |
32 | Initialise the serial port to the specified settings.\r | |
33 | The serial port is re-configured only if the specified settings\r | |
34 | are different from the current settings.\r | |
35 | All unspecified settings will be set to the default values.\r | |
36 | \r | |
37 | @param UartBase The base address of the serial device.\r | |
38 | @param UartClkInHz The clock in Hz for the serial device.\r | |
39 | Ignored if the PCD PL011UartInteger is not 0\r | |
40 | @param BaudRate The baud rate of the serial device. If the\r | |
41 | baud rate is not supported, the speed will be\r | |
42 | reduced to the nearest supported one and the\r | |
43 | variable's value will be updated accordingly.\r | |
44 | @param ReceiveFifoDepth The number of characters the device will\r | |
45 | buffer on input. Value of 0 will use the\r | |
46 | device's default FIFO depth.\r | |
47 | @param Parity If applicable, this is the EFI_PARITY_TYPE\r | |
48 | that is computed or checked as each character\r | |
49 | is transmitted or received. If the device\r | |
50 | does not support parity, the value is the\r | |
51 | default parity value.\r | |
52 | @param DataBits The number of data bits in each character.\r | |
53 | @param StopBits If applicable, the EFI_STOP_BITS_TYPE number\r | |
54 | of stop bits per character.\r | |
55 | If the device does not support stop bits, the\r | |
56 | value is the default stop bit value.\r | |
57 | \r | |
58 | @retval RETURN_SUCCESS All attributes were set correctly on the\r | |
59 | serial device.\r | |
60 | @retval RETURN_INVALID_PARAMETER One or more of the attributes has an\r | |
61 | unsupported value.\r | |
62 | \r | |
63 | **/\r | |
64 | RETURN_STATUS\r | |
65 | EFIAPI\r | |
66 | PL011UartInitializePort (\r | |
67 | IN UINTN UartBase,\r | |
68 | IN UINT32 UartClkInHz,\r | |
69 | IN OUT UINT64 *BaudRate,\r | |
70 | IN OUT UINT32 *ReceiveFifoDepth,\r | |
71 | IN OUT EFI_PARITY_TYPE *Parity,\r | |
72 | IN OUT UINT8 *DataBits,\r | |
73 | IN OUT EFI_STOP_BITS_TYPE *StopBits\r | |
74 | )\r | |
75 | {\r | |
76 | UINT32 LineControl;\r | |
77 | UINT32 Divisor;\r | |
78 | UINT32 Integer;\r | |
79 | UINT32 Fractional;\r | |
80 | UINT32 HardwareFifoDepth;\r | |
81 | \r | |
82 | HardwareFifoDepth = (PL011_UARTPID2_VER (MmioRead32 (UartBase + UARTPID2)) \\r | |
83 | > PL011_VER_R1P4) \\r | |
84 | ? 32 : 16 ;\r | |
85 | // The PL011 supports a buffer of 1, 16 or 32 chars. Therefore we can accept\r | |
86 | // 1 char buffer as the minimum FIFO size. Because everything can be rounded\r | |
87 | // down, there is no maximum FIFO size.\r | |
88 | if ((*ReceiveFifoDepth == 0) || (*ReceiveFifoDepth >= HardwareFifoDepth)) {\r | |
89 | // Enable FIFO\r | |
90 | LineControl = PL011_UARTLCR_H_FEN;\r | |
91 | *ReceiveFifoDepth = HardwareFifoDepth;\r | |
92 | } else {\r | |
93 | // Disable FIFO\r | |
94 | LineControl = 0;\r | |
95 | // Nothing else to do. 1 byte FIFO is default.\r | |
96 | *ReceiveFifoDepth = 1;\r | |
97 | }\r | |
98 | \r | |
99 | //\r | |
100 | // Parity\r | |
101 | //\r | |
102 | switch (*Parity) {\r | |
103 | case DefaultParity:\r | |
104 | *Parity = NoParity;\r | |
105 | case NoParity:\r | |
106 | // Nothing to do. Parity is disabled by default.\r | |
107 | break;\r | |
108 | case EvenParity:\r | |
109 | LineControl |= (PL011_UARTLCR_H_PEN | PL011_UARTLCR_H_EPS);\r | |
110 | break;\r | |
111 | case OddParity:\r | |
112 | LineControl |= PL011_UARTLCR_H_PEN;\r | |
113 | break;\r | |
114 | case MarkParity:\r | |
115 | LineControl |= ( PL011_UARTLCR_H_PEN \\r | |
116 | | PL011_UARTLCR_H_SPS \\r | |
117 | | PL011_UARTLCR_H_EPS);\r | |
118 | break;\r | |
119 | case SpaceParity:\r | |
120 | LineControl |= (PL011_UARTLCR_H_PEN | PL011_UARTLCR_H_SPS);\r | |
121 | break;\r | |
122 | default:\r | |
123 | return RETURN_INVALID_PARAMETER;\r | |
124 | }\r | |
125 | \r | |
126 | //\r | |
127 | // Data Bits\r | |
128 | //\r | |
129 | switch (*DataBits) {\r | |
130 | case 0:\r | |
131 | *DataBits = 8;\r | |
132 | case 8:\r | |
133 | LineControl |= PL011_UARTLCR_H_WLEN_8;\r | |
134 | break;\r | |
135 | case 7:\r | |
136 | LineControl |= PL011_UARTLCR_H_WLEN_7;\r | |
137 | break;\r | |
138 | case 6:\r | |
139 | LineControl |= PL011_UARTLCR_H_WLEN_6;\r | |
140 | break;\r | |
141 | case 5:\r | |
142 | LineControl |= PL011_UARTLCR_H_WLEN_5;\r | |
143 | break;\r | |
144 | default:\r | |
145 | return RETURN_INVALID_PARAMETER;\r | |
146 | }\r | |
147 | \r | |
148 | //\r | |
149 | // Stop Bits\r | |
150 | //\r | |
151 | switch (*StopBits) {\r | |
152 | case DefaultStopBits:\r | |
153 | *StopBits = OneStopBit;\r | |
154 | case OneStopBit:\r | |
155 | // Nothing to do. One stop bit is enabled by default.\r | |
156 | break;\r | |
157 | case TwoStopBits:\r | |
158 | LineControl |= PL011_UARTLCR_H_STP2;\r | |
159 | break;\r | |
160 | case OneFiveStopBits:\r | |
161 | // Only 1 or 2 stop bits are supported\r | |
162 | default:\r | |
163 | return RETURN_INVALID_PARAMETER;\r | |
164 | }\r | |
165 | \r | |
166 | // Don't send the LineControl value to the PL011 yet,\r | |
167 | // wait until after the Baud Rate setting.\r | |
168 | // This ensures we do not mess up the UART settings halfway through\r | |
169 | // in the rare case when there is an error with the Baud Rate.\r | |
170 | \r | |
171 | //\r | |
172 | // Baud Rate\r | |
173 | //\r | |
174 | \r | |
175 | // If PL011 Integer value has been defined then always ignore the BAUD rate\r | |
176 | if (FixedPcdGet32 (PL011UartInteger) != 0) {\r | |
177 | Integer = FixedPcdGet32 (PL011UartInteger);\r | |
178 | Fractional = FixedPcdGet32 (PL011UartFractional);\r | |
179 | } else {\r | |
180 | // If BAUD rate is zero then replace it with the system default value\r | |
181 | if (*BaudRate == 0) {\r | |
182 | *BaudRate = FixedPcdGet32 (PcdSerialBaudRate);\r | |
183 | if (*BaudRate == 0) {\r | |
184 | return RETURN_INVALID_PARAMETER;\r | |
185 | }\r | |
186 | }\r | |
187 | if (0 == UartClkInHz) {\r | |
188 | return RETURN_INVALID_PARAMETER;\r | |
189 | }\r | |
190 | \r | |
191 | Divisor = (UartClkInHz * 4) / *BaudRate;\r | |
192 | Integer = Divisor >> FRACTION_PART_SIZE_IN_BITS;\r | |
193 | Fractional = Divisor & FRACTION_PART_MASK;\r | |
194 | }\r | |
195 | \r | |
196 | //\r | |
197 | // If PL011 is already initialized, check the current settings\r | |
198 | // and re-initialize only if the settings are different.\r | |
199 | //\r | |
200 | if (((MmioRead32 (UartBase + UARTCR) & PL011_UARTCR_UARTEN) != 0) &&\r | |
201 | (MmioRead32 (UartBase + UARTLCR_H) == LineControl) &&\r | |
202 | (MmioRead32 (UartBase + UARTIBRD) == Integer) &&\r | |
203 | (MmioRead32 (UartBase + UARTFBRD) == Fractional)) {\r | |
204 | // Nothing to do - already initialized with correct attributes\r | |
205 | return RETURN_SUCCESS;\r | |
206 | }\r | |
207 | \r | |
208 | // Wait for the end of transmission\r | |
209 | while ((MmioRead32 (UartBase + UARTFR) & PL011_UARTFR_TXFE) == 0);\r | |
210 | \r | |
211 | // Disable UART: "The UARTLCR_H, UARTIBRD, and UARTFBRD registers must not be changed\r | |
212 | // when the UART is enabled"\r | |
213 | MmioWrite32 (UartBase + UARTCR, 0);\r | |
214 | \r | |
215 | // Set Baud Rate Registers\r | |
216 | MmioWrite32 (UartBase + UARTIBRD, Integer);\r | |
217 | MmioWrite32 (UartBase + UARTFBRD, Fractional);\r | |
218 | \r | |
219 | // No parity, 1 stop, no fifo, 8 data bits\r | |
220 | MmioWrite32 (UartBase + UARTLCR_H, LineControl);\r | |
221 | \r | |
222 | // Clear any pending errors\r | |
223 | MmioWrite32 (UartBase + UARTECR, 0);\r | |
224 | \r | |
225 | // Enable Tx, Rx, and UART overall\r | |
226 | MmioWrite32 (UartBase + UARTCR,\r | |
227 | PL011_UARTCR_RXE | PL011_UARTCR_TXE | PL011_UARTCR_UARTEN);\r | |
228 | \r | |
229 | return RETURN_SUCCESS;\r | |
230 | }\r | |
231 | \r | |
232 | /**\r | |
233 | \r | |
234 | Assert or deassert the control signals on a serial port.\r | |
235 | The following control signals are set according their bit settings :\r | |
236 | . Request to Send\r | |
237 | . Data Terminal Ready\r | |
238 | \r | |
239 | @param[in] UartBase UART registers base address\r | |
240 | @param[in] Control The following bits are taken into account :\r | |
241 | . EFI_SERIAL_REQUEST_TO_SEND : assert/deassert the\r | |
242 | "Request To Send" control signal if this bit is\r | |
243 | equal to one/zero.\r | |
244 | . EFI_SERIAL_DATA_TERMINAL_READY : assert/deassert\r | |
245 | the "Data Terminal Ready" control signal if this\r | |
246 | bit is equal to one/zero.\r | |
247 | . EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE : enable/disable\r | |
248 | the hardware loopback if this bit is equal to\r | |
249 | one/zero.\r | |
250 | . EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE : not supported.\r | |
251 | . EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE : enable/\r | |
252 | disable the hardware flow control based on CTS (Clear\r | |
253 | To Send) and RTS (Ready To Send) control signals.\r | |
254 | \r | |
255 | @retval RETURN_SUCCESS The new control bits were set on the device.\r | |
256 | @retval RETURN_UNSUPPORTED The device does not support this operation.\r | |
257 | \r | |
258 | **/\r | |
259 | RETURN_STATUS\r | |
260 | EFIAPI\r | |
261 | PL011UartSetControl (\r | |
262 | IN UINTN UartBase,\r | |
263 | IN UINT32 Control\r | |
264 | )\r | |
265 | {\r | |
266 | UINT32 Bits;\r | |
267 | \r | |
268 | if (Control & (mInvalidControlBits)) {\r | |
269 | return RETURN_UNSUPPORTED;\r | |
270 | }\r | |
271 | \r | |
272 | Bits = MmioRead32 (UartBase + UARTCR);\r | |
273 | \r | |
274 | if (Control & EFI_SERIAL_REQUEST_TO_SEND) {\r | |
275 | Bits |= PL011_UARTCR_RTS;\r | |
276 | } else {\r | |
277 | Bits &= ~PL011_UARTCR_RTS;\r | |
278 | }\r | |
279 | \r | |
280 | if (Control & EFI_SERIAL_DATA_TERMINAL_READY) {\r | |
281 | Bits |= PL011_UARTCR_DTR;\r | |
282 | } else {\r | |
283 | Bits &= ~PL011_UARTCR_DTR;\r | |
284 | }\r | |
285 | \r | |
286 | if (Control & EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE) {\r | |
287 | Bits |= PL011_UARTCR_LBE;\r | |
288 | } else {\r | |
289 | Bits &= ~PL011_UARTCR_LBE;\r | |
290 | }\r | |
291 | \r | |
292 | if (Control & EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE) {\r | |
293 | Bits |= (PL011_UARTCR_CTSEN | PL011_UARTCR_RTSEN);\r | |
294 | } else {\r | |
295 | Bits &= ~(PL011_UARTCR_CTSEN | PL011_UARTCR_RTSEN);\r | |
296 | }\r | |
297 | \r | |
298 | MmioWrite32 (UartBase + UARTCR, Bits);\r | |
299 | \r | |
300 | return RETURN_SUCCESS;\r | |
301 | }\r | |
302 | \r | |
303 | /**\r | |
304 | \r | |
305 | Retrieve the status of the control bits on a serial device.\r | |
306 | \r | |
307 | @param[in] UartBase UART registers base address\r | |
308 | @param[out] Control Status of the control bits on a serial device :\r | |
309 | \r | |
310 | . EFI_SERIAL_DATA_CLEAR_TO_SEND,\r | |
311 | EFI_SERIAL_DATA_SET_READY,\r | |
312 | EFI_SERIAL_RING_INDICATE,\r | |
313 | EFI_SERIAL_CARRIER_DETECT,\r | |
314 | EFI_SERIAL_REQUEST_TO_SEND,\r | |
315 | EFI_SERIAL_DATA_TERMINAL_READY\r | |
316 | are all related to the DTE (Data Terminal Equipment)\r | |
317 | and DCE (Data Communication Equipment) modes of\r | |
318 | operation of the serial device.\r | |
319 | . EFI_SERIAL_INPUT_BUFFER_EMPTY : equal to one if the\r | |
320 | receive buffer is empty, 0 otherwise.\r | |
321 | . EFI_SERIAL_OUTPUT_BUFFER_EMPTY : equal to one if the\r | |
322 | transmit buffer is empty, 0 otherwise.\r | |
323 | . EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE : equal to one if\r | |
16f3544d | 324 | the hardware loopback is enabled (the output feeds the\r |
12156134 AB |
325 | receive buffer), 0 otherwise.\r |
326 | . EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE : equal to one if\r | |
327 | a loopback is accomplished by software, 0 otherwise.\r | |
328 | . EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE : equal to\r | |
329 | one if the hardware flow control based on CTS (Clear\r | |
330 | To Send) and RTS (Ready To Send) control signals is\r | |
331 | enabled, 0 otherwise.\r | |
332 | \r | |
333 | @retval RETURN_SUCCESS The control bits were read from the serial device.\r | |
334 | \r | |
335 | **/\r | |
336 | RETURN_STATUS\r | |
337 | EFIAPI\r | |
338 | PL011UartGetControl (\r | |
339 | IN UINTN UartBase,\r | |
340 | OUT UINT32 *Control\r | |
341 | )\r | |
342 | {\r | |
343 | UINT32 FlagRegister;\r | |
344 | UINT32 ControlRegister;\r | |
345 | \r | |
346 | \r | |
347 | FlagRegister = MmioRead32 (UartBase + UARTFR);\r | |
348 | ControlRegister = MmioRead32 (UartBase + UARTCR);\r | |
349 | \r | |
350 | *Control = 0;\r | |
351 | \r | |
352 | if ((FlagRegister & PL011_UARTFR_CTS) == PL011_UARTFR_CTS) {\r | |
353 | *Control |= EFI_SERIAL_CLEAR_TO_SEND;\r | |
354 | }\r | |
355 | \r | |
356 | if ((FlagRegister & PL011_UARTFR_DSR) == PL011_UARTFR_DSR) {\r | |
357 | *Control |= EFI_SERIAL_DATA_SET_READY;\r | |
358 | }\r | |
359 | \r | |
360 | if ((FlagRegister & PL011_UARTFR_RI) == PL011_UARTFR_RI) {\r | |
361 | *Control |= EFI_SERIAL_RING_INDICATE;\r | |
362 | }\r | |
363 | \r | |
364 | if ((FlagRegister & PL011_UARTFR_DCD) == PL011_UARTFR_DCD) {\r | |
365 | *Control |= EFI_SERIAL_CARRIER_DETECT;\r | |
366 | }\r | |
367 | \r | |
368 | if ((ControlRegister & PL011_UARTCR_RTS) == PL011_UARTCR_RTS) {\r | |
369 | *Control |= EFI_SERIAL_REQUEST_TO_SEND;\r | |
370 | }\r | |
371 | \r | |
372 | if ((ControlRegister & PL011_UARTCR_DTR) == PL011_UARTCR_DTR) {\r | |
373 | *Control |= EFI_SERIAL_DATA_TERMINAL_READY;\r | |
374 | }\r | |
375 | \r | |
376 | if ((FlagRegister & PL011_UARTFR_RXFE) == PL011_UARTFR_RXFE) {\r | |
377 | *Control |= EFI_SERIAL_INPUT_BUFFER_EMPTY;\r | |
378 | }\r | |
379 | \r | |
380 | if ((FlagRegister & PL011_UARTFR_TXFE) == PL011_UARTFR_TXFE) {\r | |
381 | *Control |= EFI_SERIAL_OUTPUT_BUFFER_EMPTY;\r | |
382 | }\r | |
383 | \r | |
384 | if ((ControlRegister & (PL011_UARTCR_CTSEN | PL011_UARTCR_RTSEN))\r | |
385 | == (PL011_UARTCR_CTSEN | PL011_UARTCR_RTSEN)) {\r | |
386 | *Control |= EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE;\r | |
387 | }\r | |
388 | \r | |
389 | if ((ControlRegister & PL011_UARTCR_LBE) == PL011_UARTCR_LBE) {\r | |
390 | *Control |= EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE;\r | |
391 | }\r | |
392 | \r | |
393 | return RETURN_SUCCESS;\r | |
394 | }\r | |
395 | \r | |
396 | /**\r | |
397 | Write data to serial device.\r | |
398 | \r | |
399 | @param Buffer Point of data buffer which need to be written.\r | |
400 | @param NumberOfBytes Number of output bytes which are cached in Buffer.\r | |
401 | \r | |
402 | @retval 0 Write data failed.\r | |
403 | @retval !0 Actual number of bytes written to serial device.\r | |
404 | \r | |
405 | **/\r | |
406 | UINTN\r | |
407 | EFIAPI\r | |
408 | PL011UartWrite (\r | |
409 | IN UINTN UartBase,\r | |
410 | IN UINT8 *Buffer,\r | |
411 | IN UINTN NumberOfBytes\r | |
412 | )\r | |
413 | {\r | |
414 | UINT8* CONST Final = &Buffer[NumberOfBytes];\r | |
415 | \r | |
416 | while (Buffer < Final) {\r | |
417 | // Wait until UART able to accept another char\r | |
418 | while ((MmioRead32 (UartBase + UARTFR) & UART_TX_FULL_FLAG_MASK));\r | |
419 | \r | |
420 | MmioWrite8 (UartBase + UARTDR, *Buffer++);\r | |
421 | }\r | |
422 | \r | |
423 | return NumberOfBytes;\r | |
424 | }\r | |
425 | \r | |
426 | /**\r | |
427 | Read data from serial device and save the data in buffer.\r | |
428 | \r | |
429 | @param Buffer Point of data buffer which need to be written.\r | |
430 | @param NumberOfBytes Number of output bytes which are cached in Buffer.\r | |
431 | \r | |
432 | @retval 0 Read data failed.\r | |
433 | @retval !0 Actual number of bytes read from serial device.\r | |
434 | \r | |
435 | **/\r | |
436 | UINTN\r | |
437 | EFIAPI\r | |
438 | PL011UartRead (\r | |
439 | IN UINTN UartBase,\r | |
440 | OUT UINT8 *Buffer,\r | |
441 | IN UINTN NumberOfBytes\r | |
442 | )\r | |
443 | {\r | |
444 | UINTN Count;\r | |
445 | \r | |
446 | for (Count = 0; Count < NumberOfBytes; Count++, Buffer++) {\r | |
447 | while ((MmioRead32 (UartBase + UARTFR) & UART_RX_EMPTY_FLAG_MASK) != 0);\r | |
448 | *Buffer = MmioRead8 (UartBase + UARTDR);\r | |
449 | }\r | |
450 | \r | |
451 | return NumberOfBytes;\r | |
452 | }\r | |
453 | \r | |
454 | /**\r | |
455 | Check to see if any data is available to be read from the debug device.\r | |
456 | \r | |
457 | @retval TRUE At least one byte of data is available to be read\r | |
458 | @retval FALSE No data is available to be read\r | |
459 | \r | |
460 | **/\r | |
461 | BOOLEAN\r | |
462 | EFIAPI\r | |
463 | PL011UartPoll (\r | |
464 | IN UINTN UartBase\r | |
465 | )\r | |
466 | {\r | |
467 | return ((MmioRead32 (UartBase + UARTFR) & UART_RX_EMPTY_FLAG_MASK) == 0);\r | |
468 | }\r |