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1bc83266 | 1 | #\r |
eaa84fd5 | 2 | # Copyright (c) 2011-2014, ARM Limited. All rights reserved.\r |
1bc83266 HL |
3 | #\r |
4 | # This program and the accompanying materials\r | |
5 | # are licensed and made available under the terms and conditions of the BSD License\r | |
6 | # which accompanies this distribution. The full text of the license may be found at\r | |
7 | # http://opensource.org/licenses/bsd-license.php\r | |
8 | #\r | |
9 | # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
10 | # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
11 | #\r | |
12 | #\r | |
13 | \r | |
d855b261 | 14 | #include <Chipset/AArch64.h>\r |
1bc83266 HL |
15 | #include <AsmMacroIoLibV8.h>\r |
16 | #include <Base.h>\r | |
17 | #include <AutoGen.h>\r | |
18 | \r | |
19 | .text\r | |
1bc83266 HL |
20 | \r |
21 | //============================================================\r | |
22 | //Default Exception Handlers\r | |
23 | //============================================================\r | |
24 | \r | |
1bc83266 HL |
25 | #define TO_HANDLER \\r |
26 | EL1_OR_EL2(x1) \\r | |
27 | 1: mrs x1, elr_el1 /* EL1 Exception Link Register */ ;\\r | |
28 | b 3f ;\\r | |
29 | 2: mrs x1, elr_el2 /* EL2 Exception Link Register */ ;\\r | |
30 | 3: bl ASM_PFX(PeiCommonExceptionEntry) ;\r | |
31 | \r | |
32 | \r | |
33 | //\r | |
34 | // Default Exception handlers: There is no plan to return from any of these exceptions.\r | |
35 | // No context saving at all.\r | |
36 | //\r | |
37 | \r | |
d855b261 MR |
38 | VECTOR_BASE(PeiVectorTable)\r |
39 | \r | |
40 | VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SP0_SYNC)\r | |
1bc83266 HL |
41 | _DefaultSyncExceptHandler_t:\r |
42 | mov x0, #EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS\r | |
43 | TO_HANDLER\r | |
44 | \r | |
d855b261 | 45 | VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SP0_IRQ)\r |
1bc83266 HL |
46 | _DefaultIrq_t:\r |
47 | mov x0, #EXCEPT_AARCH64_IRQ\r | |
48 | TO_HANDLER\r | |
49 | \r | |
d855b261 | 50 | VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SP0_FIQ)\r |
1bc83266 HL |
51 | _DefaultFiq_t:\r |
52 | mov x0, #EXCEPT_AARCH64_FIQ\r | |
53 | TO_HANDLER\r | |
54 | \r | |
d855b261 | 55 | VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SP0_SERR)\r |
1bc83266 HL |
56 | _DefaultSError_t:\r |
57 | mov x0, #EXCEPT_AARCH64_SERROR\r | |
58 | TO_HANDLER\r | |
59 | \r | |
d855b261 | 60 | VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SPx_SYNC)\r |
1bc83266 HL |
61 | _DefaultSyncExceptHandler_h:\r |
62 | mov x0, #EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS\r | |
63 | TO_HANDLER\r | |
64 | \r | |
d855b261 | 65 | VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SPx_IRQ)\r |
1bc83266 HL |
66 | _DefaultIrq_h:\r |
67 | mov x0, #EXCEPT_AARCH64_IRQ\r | |
68 | TO_HANDLER\r | |
69 | \r | |
d855b261 | 70 | VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SPx_FIQ)\r |
1bc83266 HL |
71 | _DefaultFiq_h:\r |
72 | mov x0, #EXCEPT_AARCH64_FIQ\r | |
73 | TO_HANDLER\r | |
74 | \r | |
d855b261 | 75 | VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SPx_SERR)\r |
1bc83266 HL |
76 | _DefaultSError_h:\r |
77 | mov x0, #EXCEPT_AARCH64_SERROR\r | |
78 | TO_HANDLER\r | |
d855b261 MR |
79 | \r |
80 | VECTOR_END(PeiVectorTable)\r |