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Commit | Line | Data |
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f598bf12 | 1 | /** @file\r |
5a5440d0 PG |
2 | Main file supporting the transition to PEI Core in Normal World for Versatile Express\r |
3 | \r | |
4 | Copyright (c) 2011, ARM Limited. All rights reserved.\r | |
5 | \r | |
6 | SPDX-License-Identifier: BSD-2-Clause-Patent\r | |
7 | \r | |
f598bf12 | 8 | **/\r |
40b0b23e | 9 | \r |
f598bf12 | 10 | #ifndef __PREPEICORE_H_\r |
11 | #define __PREPEICORE_H_\r | |
12 | \r | |
8fc38a3f | 13 | #include <Library/ArmLib.h>\r |
14 | #include <Library/ArmPlatformLib.h>\r | |
15 | #include <Library/BaseMemoryLib.h>\r | |
5cc45b70 | 16 | #include <Library/DebugLib.h>\r |
8fc38a3f | 17 | #include <Library/IoLib.h>\r |
5cc45b70 | 18 | #include <Library/PcdLib.h>\r |
19 | \r | |
f598bf12 | 20 | #include <PiPei.h>\r |
21 | #include <Ppi/TemporaryRamSupport.h>\r | |
22 | \r | |
77de7e53 | 23 | VOID\r |
24 | CreatePpiList (\r | |
25 | OUT UINTN *PpiListSize,\r | |
26 | OUT EFI_PEI_PPI_DESCRIPTOR **PpiList\r | |
27 | );\r | |
f598bf12 | 28 | \r |
29 | EFI_STATUS\r | |
30 | EFIAPI\r | |
77de7e53 | 31 | PrePeiCoreTemporaryRamSupport (\r |
40b0b23e MK |
32 | IN CONST EFI_PEI_SERVICES **PeiServices,\r |
33 | IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase,\r | |
34 | IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase,\r | |
35 | IN UINTN CopySize\r | |
f598bf12 | 36 | );\r |
37 | \r | |
38 | VOID\r | |
39 | SecSwitchStack (\r | |
40b0b23e | 40 | INTN StackDelta\r |
f598bf12 | 41 | );\r |
42 | \r | |
43 | // Vector Table for Pei Phase\r | |
40b0b23e MK |
44 | VOID\r |
45 | PeiVectorTable (\r | |
46 | VOID\r | |
47 | );\r | |
f598bf12 | 48 | \r |
49 | VOID\r | |
50 | EFIAPI\r | |
51 | PrimaryMain (\r | |
52 | IN EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint\r | |
53 | );\r | |
54 | \r | |
55 | /*\r | |
56 | * This is the main function for secondary cores. They loop around until a non Null value is written to\r | |
57 | * SYS_FLAGS register.The SYS_FLAGS register is platform specific.\r | |
58 | * Note:The secondary cores, while executing secondary_main, assumes that:\r | |
59 | * : SGI 0 is configured as Non-secure interrupt\r | |
60 | * : Priority Mask is configured to allow SGI 0\r | |
61 | * : Interrupt Distributor and CPU interfaces are enabled\r | |
62 | *\r | |
63 | */\r | |
64 | VOID\r | |
65 | EFIAPI\r | |
66 | SecondaryMain (\r | |
40b0b23e | 67 | IN UINTN MpId\r |
f598bf12 | 68 | );\r |
69 | \r | |
a9d7090f | 70 | VOID\r |
71 | PeiCommonExceptionEntry (\r | |
40b0b23e MK |
72 | IN UINT32 Entry,\r |
73 | IN UINTN LR\r | |
a9d7090f | 74 | );\r |
75 | \r | |
f598bf12 | 76 | #endif\r |