]> git.proxmox.com Git - mirror_edk2.git/blame - ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf
MdeModulePkg/DxeCore: use separate lock for pool allocations
[mirror_edk2.git] / ArmPlatformPkg / PrePeiCore / PrePeiCoreMPCore.inf
CommitLineData
1d5d0ae9 1#/** @file\r
2# Pre PeiCore - Hand-off to PEI Core in Normal World\r
3402aac7 3#\r
18744a5f 4# Copyright (c) 2011-2014, ARM Limited. All rights reserved.\r
1d5d0ae9 5#\r
3402aac7
RC
6# This program and the accompanying materials\r
7# are licensed and made available under the terms and conditions of the BSD License\r
8# which accompanies this distribution. The full text of the license may be found at\r
9# http://opensource.org/licenses/bsd-license.php\r
10#\r
11# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
12# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
13#\r
1d5d0ae9 14#**/\r
15\r
16[Defines]\r
17 INF_VERSION = 0x00010005\r
18 BASE_NAME = ArmPlatformPrePeiCore\r
19 FILE_GUID = 469fc080-aec1-11df-927c-0002a5d5c51b\r
20 MODULE_TYPE = SEC\r
21 VERSION_STRING = 1.0\r
22\r
a9d7090f 23[Sources.common]\r
1d5d0ae9 24 MainMPCore.c\r
a9d7090f 25 PrePeiCore.c\r
26\r
27[Sources.ARM]\r
28 Arm/ArchPrePeiCore.c\r
29 Arm/PrePeiCoreEntryPoint.asm | RVCT\r
30 Arm/PrePeiCoreEntryPoint.S | GCC\r
31 Arm/SwitchStack.asm | RVCT\r
32 Arm/SwitchStack.S | GCC\r
33 Arm/Exception.asm | RVCT\r
34 Arm/Exception.S | GCC\r
35\r
1bc83266
HL
36[Sources.AARCH64]\r
37 AArch64/ArchPrePeiCore.c\r
ef7b3786
BJ
38 AArch64/PrePeiCoreEntryPoint.S\r
39 AArch64/SwitchStack.S\r
40 AArch64/Exception.S\r
41 AArch64/Helper.S\r
1bc83266 42\r
1d5d0ae9 43[Packages]\r
44 MdePkg/MdePkg.dec\r
45 MdeModulePkg/MdeModulePkg.dec\r
1d5d0ae9 46 ArmPkg/ArmPkg.dec\r
47 ArmPlatformPkg/ArmPlatformPkg.dec\r
48\r
49[LibraryClasses]\r
1d5d0ae9 50 ArmLib\r
51 ArmPlatformLib\r
3723a71a 52 BaseLib\r
53 DebugLib\r
a6caee65 54 DebugAgentLib\r
3723a71a 55 IoLib\r
55a0d64b 56 ArmGicLib\r
3723a71a 57 PrintLib\r
2637d1ef 58 SerialPortLib\r
1d5d0ae9 59\r
60[Ppis]\r
61 gEfiTemporaryRamSupportPpiGuid\r
44788bae 62 gArmMpCoreInfoPpiGuid\r
1d5d0ae9 63\r
a6caee65 64[FeaturePcd]\r
65 gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores\r
bf72cf33 66\r
a6caee65 67[FixedPcd]\r
f92b93c9 68 gArmTokenSpaceGuid.PcdFvBaseAddress\r
69 gArmTokenSpaceGuid.PcdFvSize\r
1d5d0ae9 70\r
2dbcb8f0 71 gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase\r
72 gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize\r
73 gArmPlatformTokenSpaceGuid.PcdCPUCoreSecondaryStackSize\r
3402aac7 74\r
1d5d0ae9 75 gArmTokenSpaceGuid.PcdGicDistributorBase\r
76 gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase\r
4c19ece3 77 gArmTokenSpaceGuid.PcdGicSgiIntId\r