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cd872e40 | 1 | /** @file\r |
2 | *\r | |
1b0ac0de | 3 | * Copyright (c) 2011-2014, ARM Limited. All rights reserved.\r |
cd872e40 | 4 | *\r |
f4dfad05 | 5 | * SPDX-License-Identifier: BSD-2-Clause-Patent\r |
cd872e40 | 6 | *\r |
7 | **/\r | |
8 | \r | |
9 | #include "PrePi.h"\r | |
10 | \r | |
55a0d64b | 11 | #include <Library/ArmGicLib.h>\r |
cd872e40 | 12 | \r |
99565b88 | 13 | #include <Ppi/ArmMpCoreInfo.h>\r |
14 | \r | |
cd872e40 | 15 | VOID\r |
16 | PrimaryMain (\r | |
17 | IN UINTN UefiMemoryBase,\r | |
c524ffbb | 18 | IN UINTN StacksBase,\r |
cd872e40 | 19 | IN UINT64 StartTimeStamp\r |
20 | )\r | |
21 | {\r | |
55a0d64b | 22 | // Enable the GIC Distributor\r |
8a1f2378 | 23 | ArmGicEnableDistributor(PcdGet64(PcdGicDistributorBase));\r |
cd872e40 | 24 | \r |
0dbbacdf | 25 | // In some cases, the secondary cores are waiting for an SGI from the next stage boot loader to resume their initialization\r |
d269095b | 26 | if (!FixedPcdGet32(PcdSendSgiToBringUpSecondaryCores)) {\r |
cd872e40 | 27 | // Sending SGI to all the Secondary CPU interfaces\r |
8a1f2378 | 28 | ArmGicSendSgiTo (PcdGet64(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E, PcdGet32 (PcdGicSgiIntId));\r |
cd872e40 | 29 | }\r |
30 | \r | |
f2e17a07 | 31 | PrePiMain (UefiMemoryBase, StacksBase, StartTimeStamp);\r |
cd872e40 | 32 | \r |
33 | // We must never return\r | |
34 | ASSERT(FALSE);\r | |
35 | }\r | |
36 | \r | |
37 | VOID\r | |
38 | SecondaryMain (\r | |
0787bc61 | 39 | IN UINTN MpId\r |
cd872e40 | 40 | )\r |
41 | {\r | |
99565b88 | 42 | EFI_STATUS Status;\r |
43 | ARM_MP_CORE_INFO_PPI *ArmMpCoreInfoPpi;\r | |
44 | UINTN Index;\r | |
45 | UINTN ArmCoreCount;\r | |
46 | ARM_CORE_INFO *ArmCoreInfoTable;\r | |
47 | UINT32 ClusterId;\r | |
48 | UINT32 CoreId;\r | |
49 | VOID (*SecondaryStart)(VOID);\r | |
50 | UINTN SecondaryEntryAddr;\r | |
1b0ac0de OM |
51 | UINTN AcknowledgeInterrupt;\r |
52 | UINTN InterruptId;\r | |
99565b88 | 53 | \r |
54 | ClusterId = GET_CLUSTER_ID(MpId);\r | |
55 | CoreId = GET_CORE_ID(MpId);\r | |
56 | \r | |
57 | // On MP Core Platform we must implement the ARM MP Core Info PPI (gArmMpCoreInfoPpiGuid)\r | |
58 | Status = GetPlatformPpi (&gArmMpCoreInfoPpiGuid, (VOID**)&ArmMpCoreInfoPpi);\r | |
59 | ASSERT_EFI_ERROR (Status);\r | |
60 | \r | |
61 | ArmCoreCount = 0;\r | |
62 | Status = ArmMpCoreInfoPpi->GetMpCoreInfo (&ArmCoreCount, &ArmCoreInfoTable);\r | |
63 | ASSERT_EFI_ERROR (Status);\r | |
64 | \r | |
65 | // Find the core in the ArmCoreTable\r | |
66 | for (Index = 0; Index < ArmCoreCount; Index++) {\r | |
67 | if ((ArmCoreInfoTable[Index].ClusterId == ClusterId) && (ArmCoreInfoTable[Index].CoreId == CoreId)) {\r | |
68 | break;\r | |
69 | }\r | |
70 | }\r | |
71 | \r | |
72 | // The ARM Core Info Table must define every core\r | |
73 | ASSERT (Index != ArmCoreCount);\r | |
cd872e40 | 74 | \r |
75 | // Clear Secondary cores MailBox\r | |
99565b88 | 76 | MmioWrite32 (ArmCoreInfoTable[Index].MailboxClearAddress, ArmCoreInfoTable[Index].MailboxClearValue);\r |
cd872e40 | 77 | \r |
315649cd | 78 | do {\r |
99565b88 | 79 | ArmCallWFI ();\r |
315649cd | 80 | \r |
81 | // Read the Mailbox\r | |
82 | SecondaryEntryAddr = MmioRead32 (ArmCoreInfoTable[Index].MailboxGetAddress);\r | |
83 | \r | |
cd872e40 | 84 | // Acknowledge the interrupt and send End of Interrupt signal.\r |
8a1f2378 | 85 | AcknowledgeInterrupt = ArmGicAcknowledgeInterrupt (PcdGet64 (PcdGicInterruptInterfaceBase), &InterruptId);\r |
2ca815a4 | 86 | // Check if it is a valid interrupt ID\r |
8a1f2378 | 87 | if (InterruptId < ArmGicGetMaxNumInterrupts (PcdGet64 (PcdGicDistributorBase))) {\r |
2ca815a4 | 88 | // Got a valid SGI number hence signal End of Interrupt\r |
8a1f2378 | 89 | ArmGicEndOfInterrupt (PcdGet64 (PcdGicInterruptInterfaceBase), AcknowledgeInterrupt);\r |
2ca815a4 | 90 | }\r |
f93f248a | 91 | } while (SecondaryEntryAddr == 0);\r |
cd872e40 | 92 | \r |
cd872e40 | 93 | // Jump to secondary core entry point.\r |
99565b88 | 94 | SecondaryStart = (VOID (*)())SecondaryEntryAddr;\r |
95 | SecondaryStart();\r | |
cd872e40 | 96 | \r |
97 | // The secondaries shouldn't reach here\r | |
98 | ASSERT(FALSE);\r | |
99 | }\r |