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cd872e40 | 1 | /** @file\r |
2 | *\r | |
1b0ac0de | 3 | * Copyright (c) 2011-2014, ARM Limited. All rights reserved.\r |
cd872e40 | 4 | *\r |
5 | * This program and the accompanying materials\r | |
6 | * are licensed and made available under the terms and conditions of the BSD License\r | |
7 | * which accompanies this distribution. The full text of the license may be found at\r | |
8 | * http://opensource.org/licenses/bsd-license.php\r | |
9 | *\r | |
10 | * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
12 | *\r | |
13 | **/\r | |
14 | \r | |
15 | #include "PrePi.h"\r | |
16 | \r | |
55a0d64b | 17 | #include <Library/ArmGicLib.h>\r |
cd872e40 | 18 | \r |
99565b88 | 19 | #include <Ppi/ArmMpCoreInfo.h>\r |
20 | \r | |
cd872e40 | 21 | VOID\r |
22 | PrimaryMain (\r | |
23 | IN UINTN UefiMemoryBase,\r | |
c524ffbb | 24 | IN UINTN StacksBase,\r |
cd872e40 | 25 | IN UINT64 StartTimeStamp\r |
26 | )\r | |
27 | {\r | |
55a0d64b | 28 | // Enable the GIC Distributor\r |
29 | ArmGicEnableDistributor(PcdGet32(PcdGicDistributorBase));\r | |
cd872e40 | 30 | \r |
0dbbacdf | 31 | // In some cases, the secondary cores are waiting for an SGI from the next stage boot loader to resume their initialization\r |
d269095b | 32 | if (!FixedPcdGet32(PcdSendSgiToBringUpSecondaryCores)) {\r |
cd872e40 | 33 | // Sending SGI to all the Secondary CPU interfaces\r |
4c19ece3 | 34 | ArmGicSendSgiTo (PcdGet32(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E, PcdGet32 (PcdGicSgiIntId));\r |
cd872e40 | 35 | }\r |
36 | \r | |
f2e17a07 | 37 | PrePiMain (UefiMemoryBase, StacksBase, StartTimeStamp);\r |
cd872e40 | 38 | \r |
39 | // We must never return\r | |
40 | ASSERT(FALSE);\r | |
41 | }\r | |
42 | \r | |
43 | VOID\r | |
44 | SecondaryMain (\r | |
0787bc61 | 45 | IN UINTN MpId\r |
cd872e40 | 46 | )\r |
47 | {\r | |
99565b88 | 48 | EFI_STATUS Status;\r |
49 | ARM_MP_CORE_INFO_PPI *ArmMpCoreInfoPpi;\r | |
50 | UINTN Index;\r | |
51 | UINTN ArmCoreCount;\r | |
52 | ARM_CORE_INFO *ArmCoreInfoTable;\r | |
53 | UINT32 ClusterId;\r | |
54 | UINT32 CoreId;\r | |
55 | VOID (*SecondaryStart)(VOID);\r | |
56 | UINTN SecondaryEntryAddr;\r | |
1b0ac0de OM |
57 | UINTN AcknowledgeInterrupt;\r |
58 | UINTN InterruptId;\r | |
99565b88 | 59 | \r |
60 | ClusterId = GET_CLUSTER_ID(MpId);\r | |
61 | CoreId = GET_CORE_ID(MpId);\r | |
62 | \r | |
63 | // On MP Core Platform we must implement the ARM MP Core Info PPI (gArmMpCoreInfoPpiGuid)\r | |
64 | Status = GetPlatformPpi (&gArmMpCoreInfoPpiGuid, (VOID**)&ArmMpCoreInfoPpi);\r | |
65 | ASSERT_EFI_ERROR (Status);\r | |
66 | \r | |
67 | ArmCoreCount = 0;\r | |
68 | Status = ArmMpCoreInfoPpi->GetMpCoreInfo (&ArmCoreCount, &ArmCoreInfoTable);\r | |
69 | ASSERT_EFI_ERROR (Status);\r | |
70 | \r | |
71 | // Find the core in the ArmCoreTable\r | |
72 | for (Index = 0; Index < ArmCoreCount; Index++) {\r | |
73 | if ((ArmCoreInfoTable[Index].ClusterId == ClusterId) && (ArmCoreInfoTable[Index].CoreId == CoreId)) {\r | |
74 | break;\r | |
75 | }\r | |
76 | }\r | |
77 | \r | |
78 | // The ARM Core Info Table must define every core\r | |
79 | ASSERT (Index != ArmCoreCount);\r | |
cd872e40 | 80 | \r |
81 | // Clear Secondary cores MailBox\r | |
99565b88 | 82 | MmioWrite32 (ArmCoreInfoTable[Index].MailboxClearAddress, ArmCoreInfoTable[Index].MailboxClearValue);\r |
cd872e40 | 83 | \r |
315649cd | 84 | do {\r |
99565b88 | 85 | ArmCallWFI ();\r |
315649cd | 86 | \r |
87 | // Read the Mailbox\r | |
88 | SecondaryEntryAddr = MmioRead32 (ArmCoreInfoTable[Index].MailboxGetAddress);\r | |
89 | \r | |
cd872e40 | 90 | // Acknowledge the interrupt and send End of Interrupt signal.\r |
1b0ac0de | 91 | AcknowledgeInterrupt = ArmGicAcknowledgeInterrupt (PcdGet32 (PcdGicInterruptInterfaceBase), &InterruptId);\r |
2ca815a4 | 92 | // Check if it is a valid interrupt ID\r |
1b0ac0de | 93 | if (InterruptId < ArmGicGetMaxNumInterrupts (PcdGet32 (PcdGicDistributorBase))) {\r |
2ca815a4 | 94 | // Got a valid SGI number hence signal End of Interrupt\r |
1b0ac0de | 95 | ArmGicEndOfInterrupt (PcdGet32 (PcdGicInterruptInterfaceBase), AcknowledgeInterrupt);\r |
2ca815a4 | 96 | }\r |
f93f248a | 97 | } while (SecondaryEntryAddr == 0);\r |
cd872e40 | 98 | \r |
cd872e40 | 99 | // Jump to secondary core entry point.\r |
99565b88 | 100 | SecondaryStart = (VOID (*)())SecondaryEntryAddr;\r |
101 | SecondaryStart();\r | |
cd872e40 | 102 | \r |
103 | // The secondaries shouldn't reach here\r | |
104 | ASSERT(FALSE);\r | |
105 | }\r |