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cd872e40 | 1 | /** @file\r |
2 | *\r | |
a63be426 | 3 | * Copyright (c) 2011-2017, ARM Limited. All rights reserved.\r |
cd872e40 | 4 | *\r |
5 | * This program and the accompanying materials\r | |
6 | * are licensed and made available under the terms and conditions of the BSD License\r | |
7 | * which accompanies this distribution. The full text of the license may be found at\r | |
8 | * http://opensource.org/licenses/bsd-license.php\r | |
9 | *\r | |
10 | * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
12 | *\r | |
13 | **/\r | |
14 | \r | |
15 | #include <PiPei.h>\r | |
16 | \r | |
17 | #include <Library/DebugAgentLib.h>\r | |
18 | #include <Library/PrePiLib.h>\r | |
cd872e40 | 19 | #include <Library/PrintLib.h>\r |
37573927 | 20 | #include <Library/PrePiHobListPointerLib.h>\r |
cd872e40 | 21 | #include <Library/TimerLib.h>\r |
22 | #include <Library/PerformanceLib.h>\r | |
23 | \r | |
24 | #include <Ppi/GuidedSectionExtraction.h>\r | |
0dbbacdf | 25 | #include <Ppi/ArmMpCoreInfo.h>\r |
a63be426 | 26 | #include <Ppi/SecPerformance.h>\r |
cd872e40 | 27 | \r |
28 | #include "PrePi.h"\r | |
cd872e40 | 29 | \r |
91673dfd LD |
30 | #define IS_XIP() (((UINT64)FixedPcdGet64 (PcdFdBaseAddress) > mSystemMemoryEnd) || \\r |
31 | ((FixedPcdGet64 (PcdFdBaseAddress) + FixedPcdGet32 (PcdFdSize)) < FixedPcdGet64 (PcdSystemMemoryBase)))\r | |
8fc38a3f | 32 | \r |
4aae7419 AB |
33 | UINT64 mSystemMemoryEnd = FixedPcdGet64(PcdSystemMemoryBase) +\r |
34 | FixedPcdGet64(PcdSystemMemorySize) - 1;\r | |
35 | \r | |
0dbbacdf | 36 | EFI_STATUS\r |
37 | GetPlatformPpi (\r | |
38 | IN EFI_GUID *PpiGuid,\r | |
39 | OUT VOID **Ppi\r | |
40 | )\r | |
41 | {\r | |
42 | UINTN PpiListSize;\r | |
43 | UINTN PpiListCount;\r | |
44 | EFI_PEI_PPI_DESCRIPTOR *PpiList;\r | |
45 | UINTN Index;\r | |
46 | \r | |
47 | PpiListSize = 0;\r | |
48 | ArmPlatformGetPlatformPpiList (&PpiListSize, &PpiList);\r | |
49 | PpiListCount = PpiListSize / sizeof(EFI_PEI_PPI_DESCRIPTOR);\r | |
50 | for (Index = 0; Index < PpiListCount; Index++, PpiList++) {\r | |
51 | if (CompareGuid (PpiList->Guid, PpiGuid) == TRUE) {\r | |
52 | *Ppi = PpiList->Ppi;\r | |
53 | return EFI_SUCCESS;\r | |
54 | }\r | |
55 | }\r | |
56 | \r | |
57 | return EFI_NOT_FOUND;\r | |
58 | }\r | |
59 | \r | |
cd872e40 | 60 | VOID\r |
61 | PrePiMain (\r | |
62 | IN UINTN UefiMemoryBase,\r | |
c524ffbb | 63 | IN UINTN StacksBase,\r |
cd872e40 | 64 | IN UINT64 StartTimeStamp\r |
65 | )\r | |
66 | {\r | |
37573927 | 67 | EFI_HOB_HANDOFF_INFO_TABLE* HobList;\r |
0dbbacdf | 68 | ARM_MP_CORE_INFO_PPI* ArmMpCoreInfoPpi;\r |
69 | UINTN ArmCoreCount;\r | |
70 | ARM_CORE_INFO* ArmCoreInfoTable;\r | |
cd872e40 | 71 | EFI_STATUS Status;\r |
72 | CHAR8 Buffer[100];\r | |
73 | UINTN CharCount;\r | |
d269095b | 74 | UINTN StacksSize;\r |
a63be426 | 75 | FIRMWARE_SEC_PERFORMANCE Performance;\r |
cd872e40 | 76 | \r |
8fc38a3f | 77 | // If ensure the FD is either part of the System Memory or totally outside of the System Memory (XIP)\r |
3402aac7 | 78 | ASSERT (IS_XIP() ||\r |
91673dfd LD |
79 | ((FixedPcdGet64 (PcdFdBaseAddress) >= FixedPcdGet64 (PcdSystemMemoryBase)) &&\r |
80 | ((UINT64)(FixedPcdGet64 (PcdFdBaseAddress) + FixedPcdGet32 (PcdFdSize)) <= (UINT64)mSystemMemoryEnd)));\r | |
8fc38a3f | 81 | \r |
1bc83266 HL |
82 | // Initialize the architecture specific bits\r |
83 | ArchInitialize ();\r | |
cd872e40 | 84 | \r |
85 | // Initialize the Serial Port\r | |
86 | SerialPortInitialize ();\r | |
37363dff | 87 | CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"UEFI firmware (version %s built at %a on %a)\n\r",\r |
88 | (CHAR16*)PcdGetPtr(PcdFirmwareVersionString), __TIME__, __DATE__);\r | |
cd872e40 | 89 | SerialPortWrite ((UINT8 *) Buffer, CharCount);\r |
90 | \r | |
91 | // Initialize the Debug Agent for Source Level Debugging\r | |
92 | InitializeDebugAgent (DEBUG_AGENT_INIT_POSTMEM_SEC, NULL, NULL);\r | |
93 | SaveAndSetDebugTimerInterrupt (TRUE);\r | |
3402aac7 | 94 | \r |
d269095b | 95 | // Declare the PI/UEFI memory region\r |
37573927 | 96 | HobList = HobConstructor (\r |
cd872e40 | 97 | (VOID*)UefiMemoryBase,\r |
98 | FixedPcdGet32 (PcdSystemMemoryUefiRegionSize),\r | |
99 | (VOID*)UefiMemoryBase,\r | |
d269095b | 100 | (VOID*)StacksBase // The top of the UEFI Memory is reserved for the stacks\r |
101 | );\r | |
37573927 | 102 | PrePeiSetHobList (HobList);\r |
cd872e40 | 103 | \r |
104 | // Initialize MMU and Memory HOBs (Resource Descriptor HOBs)\r | |
105 | Status = MemoryPeim (UefiMemoryBase, FixedPcdGet32 (PcdSystemMemoryUefiRegionSize));\r | |
106 | ASSERT_EFI_ERROR (Status);\r | |
107 | \r | |
d269095b | 108 | // Create the Stacks HOB (reserve the memory for all stacks)\r |
99565b88 | 109 | if (ArmIsMpCore ()) {\r |
81514a8a OM |
110 | StacksSize = PcdGet32 (PcdCPUCorePrimaryStackSize) +\r |
111 | ((FixedPcdGet32 (PcdCoreCount) - 1) * FixedPcdGet32 (PcdCPUCoreSecondaryStackSize));\r | |
99565b88 | 112 | } else {\r |
113 | StacksSize = PcdGet32 (PcdCPUCorePrimaryStackSize);\r | |
114 | }\r | |
d269095b | 115 | BuildStackHob (StacksBase, StacksSize);\r |
cd872e40 | 116 | \r |
44788bae | 117 | //TODO: Call CpuPei as a library\r |
118 | BuildCpuHob (PcdGet8 (PcdPrePiCpuMemorySize), PcdGet8 (PcdPrePiCpuIoSize));\r | |
119 | \r | |
0dbbacdf | 120 | if (ArmIsMpCore ()) {\r |
121 | // Only MP Core platform need to produce gArmMpCoreInfoPpiGuid\r | |
122 | Status = GetPlatformPpi (&gArmMpCoreInfoPpiGuid, (VOID**)&ArmMpCoreInfoPpi);\r | |
123 | \r | |
124 | // On MP Core Platform we must implement the ARM MP Core Info PPI (gArmMpCoreInfoPpiGuid)\r | |
125 | ASSERT_EFI_ERROR (Status);\r | |
126 | \r | |
127 | // Build the MP Core Info Table\r | |
128 | ArmCoreCount = 0;\r | |
129 | Status = ArmMpCoreInfoPpi->GetMpCoreInfo (&ArmCoreCount, &ArmCoreInfoTable);\r | |
130 | if (!EFI_ERROR(Status) && (ArmCoreCount > 0)) {\r | |
131 | // Build MPCore Info HOB\r | |
132 | BuildGuidDataHob (&gArmMpCoreInfoGuid, ArmCoreInfoTable, sizeof (ARM_CORE_INFO) * ArmCoreCount);\r | |
133 | }\r | |
134 | }\r | |
135 | \r | |
a63be426 AF |
136 | // Store timer value logged at the beginning of firmware image execution\r |
137 | Performance.ResetEnd = GetTimeInNanoSecond (StartTimeStamp);\r | |
138 | \r | |
139 | // Build SEC Performance Data Hob\r | |
140 | BuildGuidDataHob (&gEfiFirmwarePerformanceGuid, &Performance, sizeof (Performance));\r | |
141 | \r | |
cd872e40 | 142 | // Set the Boot Mode\r |
143 | SetBootMode (ArmPlatformGetBootMode ());\r | |
144 | \r | |
145 | // Initialize Platform HOBs (CpuHob and FvHob)\r | |
146 | Status = PlatformPeim ();\r | |
147 | ASSERT_EFI_ERROR (Status);\r | |
148 | \r | |
cd872e40 | 149 | // Now, the HOB List has been initialized, we can register performance information\r |
150 | PERF_START (NULL, "PEI", NULL, StartTimeStamp);\r | |
151 | \r | |
152 | // SEC phase needs to run library constructors by hand.\r | |
6efd58aa | 153 | ProcessLibraryConstructorList ();\r |
cd872e40 | 154 | \r |
cd872e40 | 155 | // Assume the FV that contains the SEC (our code) also contains a compressed FV.\r |
156 | Status = DecompressFirstFv ();\r | |
157 | ASSERT_EFI_ERROR (Status);\r | |
158 | \r | |
159 | // Load the DXE Core and transfer control to it\r | |
160 | Status = LoadDxeCoreFromFv (NULL, 0);\r | |
161 | ASSERT_EFI_ERROR (Status);\r | |
162 | }\r | |
163 | \r | |
164 | VOID\r | |
165 | CEntryPoint (\r | |
0787bc61 | 166 | IN UINTN MpId,\r |
c524ffbb | 167 | IN UINTN UefiMemoryBase,\r |
f2e17a07 | 168 | IN UINTN StacksBase\r |
cd872e40 | 169 | )\r |
170 | {\r | |
171 | UINT64 StartTimeStamp;\r | |
3402aac7 | 172 | \r |
f437141a | 173 | // Initialize the platform specific controllers\r |
174 | ArmPlatformInitialize (MpId);\r | |
175 | \r | |
bebda7ce | 176 | if (ArmPlatformIsPrimaryCore (MpId) && PerformanceMeasurementEnabled ()) {\r |
cd872e40 | 177 | // Initialize the Timer Library to setup the Timer HW controller\r |
178 | TimerConstructor ();\r | |
179 | // We cannot call yet the PerformanceLib because the HOB List has not been initialized\r | |
180 | StartTimeStamp = GetPerformanceCounter ();\r | |
2ee85366 | 181 | } else {\r |
182 | StartTimeStamp = 0;\r | |
cd872e40 | 183 | }\r |
184 | \r | |
6dafb303 OM |
185 | // Data Cache enabled on Primary core when MMU is enabled.\r |
186 | ArmDisableDataCache ();\r | |
187 | // Invalidate Data cache\r | |
188 | ArmInvalidateDataCache ();\r | |
d269095b | 189 | // Invalidate instruction cache\r |
190 | ArmInvalidateInstructionCache ();\r | |
6dafb303 | 191 | // Enable Instruction Caches on all cores.\r |
d269095b | 192 | ArmEnableInstructionCache ();\r |
cd872e40 | 193 | \r |
99565b88 | 194 | // Define the Global Variable region when we are not running in XIP\r |
195 | if (!IS_XIP()) {\r | |
bebda7ce | 196 | if (ArmPlatformIsPrimaryCore (MpId)) {\r |
1aa9860e | 197 | if (ArmIsMpCore()) {\r |
b1d41be7 | 198 | // Signal the Global Variable Region is defined (event: ARM_CPU_EVENT_DEFAULT)\r |
199 | ArmCallSEV ();\r | |
1aa9860e | 200 | }\r |
99565b88 | 201 | } else {\r |
b1d41be7 | 202 | // Wait the Primay core has defined the address of the Global Variable region (event: ARM_CPU_EVENT_DEFAULT)\r |
203 | ArmCallWFE ();\r | |
99565b88 | 204 | }\r |
205 | }\r | |
3402aac7 | 206 | \r |
d269095b | 207 | // If not primary Jump to Secondary Main\r |
bebda7ce | 208 | if (ArmPlatformIsPrimaryCore (MpId)) {\r |
cd872e40 | 209 | // Goto primary Main.\r |
f2e17a07 | 210 | PrimaryMain (UefiMemoryBase, StacksBase, StartTimeStamp);\r |
cd872e40 | 211 | } else {\r |
0787bc61 | 212 | SecondaryMain (MpId);\r |
cd872e40 | 213 | }\r |
214 | \r | |
215 | // DXE Core should always load and never return\r | |
216 | ASSERT (FALSE);\r | |
217 | }\r | |
218 | \r |