ArmPlatformPkg/ArmVExpressPkg: Add virtio to RTSM A15 MPCore BSP

[mirror_edk2.git] / ArmPlatformPkg / Sec / AArch64 / SecEntryPoint.S

//\r
//  Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
//\r
//  This program and the accompanying materials\r
//  are licensed and made available under the terms and conditions of the BSD License\r
//  which accompanies this distribution.  The full text of the license may be found at\r
//  http://opensource.org/licenses/bsd-license.php\r
//\r
//  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
//  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
//\r
//\r
\r
#include <AutoGen.h>\r
#include <AsmMacroIoLibV8.h>\r
#include "SecInternal.h"\r
\r
.text\r
.align 3\r
\r
GCC_ASM_IMPORT(CEntryPoint)\r
GCC_ASM_IMPORT(ArmPlatformIsPrimaryCore)\r
GCC_ASM_IMPORT(ArmPlatformGetCorePosition)\r
GCC_ASM_IMPORT(ArmPlatformSecBootAction)\r
GCC_ASM_IMPORT(ArmPlatformSecBootMemoryInit)\r
GCC_ASM_IMPORT(ArmDisableInterrupts)\r
GCC_ASM_IMPORT(ArmDisableCachesAndMmu)\r
GCC_ASM_IMPORT(ArmReadMpidr)\r
GCC_ASM_IMPORT(ArmCallWFE)\r
GCC_ASM_EXPORT(_ModuleEntryPoint)\r
\r
StartupAddr:        .dword       ASM_PFX(CEntryPoint)\r
\r
ASM_PFX(_ModuleEntryPoint):\r
\r
// NOTE: We could be booting from EL3, EL2 or EL1. Need to correctly detect\r
//       and configure the system accordingly. EL2 is default if possible.\r
// If we started in EL3 we need to switch and run at EL2.\r
// If we are running at EL2 stay in EL2\r
// If we are starting at EL1 stay in EL1.\r
\r
// Sec only runs in EL3. Othewise we jump to PEI without changing anything.\r
// If Sec runs we change to EL2 before switching to PEI.\r
\r
// Which EL are we running at? Every EL needs some level of setup...\r
  EL1_OR_EL2_OR_EL3(x0)\r
1:// If we are at EL1 or EL2 leave SEC for PEI.\r
2:b     ASM_PFX(JumpToPEI)\r
  // If we are at EL3 we need to configure it and switch to EL2\r
3:b     ASM_PFX(MainEntryPoint)\r
\r
ASM_PFX(MainEntryPoint):\r
  // First ensure all interrupts are disabled\r
  bl    ASM_PFX(ArmDisableInterrupts)\r
\r
  // Ensure that the MMU and caches are off\r
  bl    ASM_PFX(ArmDisableCachesAndMmu)\r
\r
  // By default, we are doing a cold boot\r
  mov   x10, #ARM_SEC_COLD_BOOT\r
\r
  // Jump to Platform Specific Boot Action function\r
  bl    ASM_PFX(ArmPlatformSecBootAction)\r
\r
_IdentifyCpu:\r
  // Identify CPU ID\r
  bl    ASM_PFX(ArmReadMpidr)\r
  // Keep a copy of the MpId register value\r
  mov   x5, x0\r
\r
  // Is it the Primary Core ?\r
  bl    ASM_PFX(ArmPlatformIsPrimaryCore)\r
  cmp   x0, #1\r
  // Only the primary core initialize the memory (SMC)\r
  b.eq  _InitMem\r
\r
_WaitInitMem:\r
  // If we are not doing a cold boot in this case we should assume the Initial Memory to be already initialized\r
  // Otherwise we have to wait the Primary Core to finish the initialization\r
  cmp   x10, #ARM_SEC_COLD_BOOT\r
  b.ne  _SetupSecondaryCoreStack\r
\r
  // Wait for the primary core to initialize the initial memory (event: BOOT_MEM_INIT)\r
  bl    ASM_PFX(ArmCallWFE)\r
  // Now the Init Mem is initialized, we setup the secondary core stacks\r
  b     _SetupSecondaryCoreStack\r
\r
_InitMem:\r
  // If we are not doing a cold boot in this case we should assume the Initial Memory to be already initialized\r
  cmp   x10, #ARM_SEC_COLD_BOOT\r
  b.ne  _SetupPrimaryCoreStack\r
\r
  // Initialize Init Boot Memory\r
  bl    ASM_PFX(ArmPlatformSecBootMemoryInit)\r
\r
_SetupPrimaryCoreStack:\r
  // Get the top of the primary stacks (and the base of the secondary stacks)\r
  LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), x1)\r
  LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecPrimaryStackSize), x2)\r
  add   x1, x1, x2\r
\r
  LoadConstantToReg (FixedPcdGet32(PcdSecGlobalVariableSize), x2)\r
\r
  // The reserved space for global variable must be 8-bytes aligned for pushing\r
  // 64-bit variable on the stack\r
  SetPrimaryStack (x1, x2, x3, x4)\r
  b     _PrepareArguments\r
\r
_SetupSecondaryCoreStack:\r
  // Get the top of the primary stacks (and the base of the secondary stacks)\r
  LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), x1)\r
  LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecPrimaryStackSize), x2)\r
  add   x6, x1, x2\r
\r
  // Get the Core Position\r
  mov   x0, x5\r
  bl    ASM_PFX(ArmPlatformGetCorePosition)\r
  // The stack starts at the top of the stack region. Add '1' to the Core Position to get the top of the stack\r
  add   x0, x0, #1\r
\r
  // StackOffset = CorePos * StackSize\r
  LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecSecondaryStackSize), x2)\r
  mul   x0, x0, x2\r
  // SP = StackBase + StackOffset\r
  add   sp, x6, x0\r
\r
_PrepareArguments:\r
  // Move sec startup address into a data register\r
  // Ensure we're jumping to FV version of the code (not boot remapped alias)\r
  ldr   x3, StartupAddr\r
\r
  // Jump to SEC C code\r
  //    r0 = mp_id\r
  //    r1 = Boot Mode\r
  mov   x0, x5\r
  mov   x1, x10\r
  blr   x3\r
\r
  ret\r
\r
ASM_PFX(JumpToPEI):\r
  LoadConstantToReg (FixedPcdGet32(PcdFvBaseAddress), x0)\r
  blr   x0\r
\r
dead:\r
  b     dead\r