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90d6a1bb | 1 | //\r |
bebda7ce | 2 | // Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r |
90d6a1bb | 3 | //\r |
3402aac7 RC |
4 | // This program and the accompanying materials\r |
5 | // are licensed and made available under the terms and conditions of the BSD License\r | |
6 | // which accompanies this distribution. The full text of the license may be found at\r | |
7 | // http://opensource.org/licenses/bsd-license.php\r | |
8 | //\r | |
9 | // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
10 | // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
90d6a1bb | 11 | //\r |
12 | //\r | |
13 | \r | |
14 | #include <AutoGen.h>\r | |
15 | #include <AsmMacroIoLib.h>\r | |
16 | #include "SecInternal.h"\r | |
17 | \r | |
18 | INCLUDE AsmMacroIoLib.inc\r | |
3402aac7 | 19 | \r |
90d6a1bb | 20 | IMPORT CEntryPoint\r |
bebda7ce | 21 | IMPORT ArmPlatformIsPrimaryCore\r |
2d45f194 | 22 | IMPORT ArmPlatformGetCorePosition\r |
90d6a1bb | 23 | IMPORT ArmPlatformSecBootAction\r |
e314d564 | 24 | IMPORT ArmPlatformSecBootMemoryInit\r |
90d6a1bb | 25 | IMPORT ArmDisableInterrupts\r |
26 | IMPORT ArmDisableCachesAndMmu\r | |
90d6a1bb | 27 | IMPORT ArmReadMpidr\r |
b1d41be7 | 28 | IMPORT ArmCallWFE\r |
90d6a1bb | 29 | EXPORT _ModuleEntryPoint\r |
30 | \r | |
31 | PRESERVE8\r | |
32 | AREA SecEntryPoint, CODE, READONLY\r | |
3402aac7 | 33 | \r |
90d6a1bb | 34 | StartupAddr DCD CEntryPoint\r |
35 | \r | |
a75568e9 | 36 | _ModuleEntryPoint FUNCTION\r |
90d6a1bb | 37 | // First ensure all interrupts are disabled\r |
6271d8c5 | 38 | bl ArmDisableInterrupts\r |
90d6a1bb | 39 | \r |
40 | // Ensure that the MMU and caches are off\r | |
6271d8c5 | 41 | bl ArmDisableCachesAndMmu\r |
90d6a1bb | 42 | \r |
a75568e9 | 43 | // By default, we are doing a cold boot\r |
44 | mov r10, #ARM_SEC_COLD_BOOT\r | |
45 | \r | |
90d6a1bb | 46 | // Jump to Platform Specific Boot Action function\r |
47 | blx ArmPlatformSecBootAction\r | |
48 | \r | |
3402aac7 | 49 | _IdentifyCpu\r |
90d6a1bb | 50 | // Identify CPU ID\r |
51 | bl ArmReadMpidr\r | |
bebda7ce | 52 | // Keep a copy of the MpId register value\r |
53 | mov r9, r0\r | |
3402aac7 | 54 | \r |
90d6a1bb | 55 | // Is it the Primary Core ?\r |
91c38d4e | 56 | bl ArmPlatformIsPrimaryCore\r |
bebda7ce | 57 | cmp r0, #1\r |
90d6a1bb | 58 | // Only the primary core initialize the memory (SMC)\r |
59 | beq _InitMem\r | |
3402aac7 | 60 | \r |
90d6a1bb | 61 | _WaitInitMem\r |
a75568e9 | 62 | // If we are not doing a cold boot in this case we should assume the Initial Memory to be already initialized\r |
63 | // Otherwise we have to wait the Primary Core to finish the initialization\r | |
64 | cmp r10, #ARM_SEC_COLD_BOOT\r | |
65 | bne _SetupSecondaryCoreStack\r | |
66 | \r | |
b1d41be7 | 67 | // Wait for the primary core to initialize the initial memory (event: BOOT_MEM_INIT)\r |
68 | bl ArmCallWFE\r | |
90d6a1bb | 69 | // Now the Init Mem is initialized, we setup the secondary core stacks\r |
70 | b _SetupSecondaryCoreStack\r | |
3402aac7 | 71 | \r |
90d6a1bb | 72 | _InitMem\r |
8cfd2e24 | 73 | // If we are not doing a cold boot in this case we should assume the Initial Memory to be already initialized\r |
74 | cmp r10, #ARM_SEC_COLD_BOOT\r | |
75 | bne _SetupPrimaryCoreStack\r | |
76 | \r | |
90d6a1bb | 77 | // Initialize Init Boot Memory\r |
e314d564 | 78 | bl ArmPlatformSecBootMemoryInit\r |
3402aac7 | 79 | \r |
90d6a1bb | 80 | _SetupPrimaryCoreStack\r |
1377db63 | 81 | // Get the top of the primary stacks (and the base of the secondary stacks)\r |
82 | LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r1)\r | |
83 | LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecPrimaryStackSize), r2)\r | |
84 | add r1, r1, r2\r | |
85 | \r | |
86 | LoadConstantToReg (FixedPcdGet32(PcdSecGlobalVariableSize), r2)\r | |
90d6a1bb | 87 | \r |
88 | // The reserved space for global variable must be 8-bytes aligned for pushing\r | |
89 | // 64-bit variable on the stack\r | |
1377db63 | 90 | SetPrimaryStack (r1, r2, r3)\r |
91 | b _PrepareArguments\r | |
90d6a1bb | 92 | \r |
93 | _SetupSecondaryCoreStack\r | |
1377db63 | 94 | // Get the top of the primary stacks (and the base of the secondary stacks)\r |
95 | LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r1)\r | |
96 | LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecPrimaryStackSize), r2)\r | |
2d45f194 | 97 | add r6, r1, r2\r |
1377db63 | 98 | \r |
2d45f194 | 99 | // Get the Core Position\r |
100 | mov r0, r9\r | |
101 | bl ArmPlatformGetCorePosition\r | |
90d6a1bb | 102 | // The stack starts at the top of the stack region. Add '1' to the Core Position to get the top of the stack\r |
103 | add r0, r0, #1\r | |
104 | \r | |
90d6a1bb | 105 | // StackOffset = CorePos * StackSize\r |
1377db63 | 106 | LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecSecondaryStackSize), r2)\r |
90d6a1bb | 107 | mul r0, r0, r2\r |
108 | // SP = StackBase + StackOffset\r | |
2d45f194 | 109 | add sp, r6, r0\r |
90d6a1bb | 110 | \r |
90d6a1bb | 111 | _PrepareArguments\r |
112 | // Move sec startup address into a data register\r | |
113 | // Ensure we're jumping to FV version of the code (not boot remapped alias)\r | |
114 | ldr r3, StartupAddr\r | |
3402aac7 | 115 | \r |
90d6a1bb | 116 | // Jump to SEC C code\r |
117 | // r0 = mp_id\r | |
a75568e9 | 118 | // r1 = Boot Mode\r |
bebda7ce | 119 | mov r0, r9\r |
a75568e9 | 120 | mov r1, r10\r |
90d6a1bb | 121 | blx r3\r |
a75568e9 | 122 | ENDFUNC\r |
3402aac7 | 123 | \r |
90d6a1bb | 124 | _NeverReturn\r |
125 | b _NeverReturn\r | |
126 | END\r |