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1d5d0ae9 | 1 | #------------------------------------------------------------------------------ |
2 | # | |
3 | # ARM VE Entry point. Reset vector in FV header will brach to | |
4 | # _ModuleEntryPoint. | |
5 | # | |
6 | # Copyright (c) 2011, ARM Limited. All rights reserved. | |
7 | # | |
8 | # This program and the accompanying materials | |
9 | # are licensed and made available under the terms and conditions of the BSD License | |
10 | # which accompanies this distribution. The full text of the license may be found at | |
11 | # http://opensource.org/licenses/bsd-license.php | |
12 | # | |
13 | # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, | |
14 | # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. | |
15 | # | |
16 | #------------------------------------------------------------------------------ | |
17 | ||
18 | #include <AsmMacroIoLib.h> | |
19 | #include <Base.h> | |
20 | #include <Library/PcdLib.h> | |
21 | #include <Library/ArmPlatformLib.h> | |
22 | #include <AutoGen.h> | |
23 | ||
24 | #Start of Code section | |
25 | .text | |
26 | .align 3 | |
27 | ||
28 | #make _ModuleEntryPoint as global | |
29 | GCC_ASM_EXPORT(_ModuleEntryPoint) | |
30 | ||
31 | #global functions referenced by this module | |
32 | GCC_ASM_IMPORT(CEntryPoint) | |
33 | GCC_ASM_IMPORT(ArmPlatformIsMemoryInitialized) | |
34 | GCC_ASM_IMPORT(ArmPlatformInitializeBootMemory) | |
35 | GCC_ASM_IMPORT(ArmDisableInterrupts) | |
36 | GCC_ASM_IMPORT(ArmDisableCachesAndMmu) | |
37 | GCC_ASM_IMPORT(ArmWriteVBar) | |
38 | GCC_ASM_IMPORT(SecVectorTable) | |
39 | ||
40 | #if (FixedPcdGet32(PcdMPCoreSupport)) | |
41 | GCC_ASM_IMPORT(ArmIsScuEnable) | |
42 | #endif | |
43 | ||
6377d2f1 | 44 | StartupAddr: .word ASM_PFX(CEntryPoint) |
45 | SecVectorTableAddr: .word ASM_PFX(SecVectorTable) | |
1d5d0ae9 | 46 | |
47 | ASM_PFX(_ModuleEntryPoint): | |
48 | #Set VBAR to the start of the exception vectors in Secure Mode | |
49 | ldr r0, SecVectorTableAddr | |
50 | bl ASM_PFX(ArmWriteVBar) | |
51 | ||
52 | # First ensure all interrupts are disabled | |
53 | bl ASM_PFX(ArmDisableInterrupts) | |
54 | ||
55 | # Ensure that the MMU and caches are off | |
56 | bl ASM_PFX(ArmDisableCachesAndMmu) | |
57 | ||
58 | _IdentifyCpu: | |
59 | # Identify CPU ID | |
60 | bl ASM_PFX(ArmReadMpidr) | |
61 | and r5, r0, #0xf | |
62 | ||
63 | #get ID of this CPU in Multicore system | |
64 | cmp r5, #0 | |
65 | # Only the primary core initialize the memory (SMC) | |
66 | beq _InitMem | |
67 | ||
68 | #if (FixedPcdGet32(PcdMPCoreSupport)) | |
69 | # ... The secondary cores wait for SCU to be enabled | |
70 | _WaitForEnabledScu: | |
71 | bl ASM_PFX(ArmIsScuEnable) | |
72 | tst r1, #1 | |
73 | beq _WaitForEnabledScu | |
74 | b _SetupStack | |
75 | #endif | |
76 | ||
77 | _InitMem: | |
78 | bl ASM_PFX(ArmPlatformIsMemoryInitialized) | |
79 | bne _SetupStack | |
80 | ||
81 | # Initialize Init Memory | |
82 | bl ASM_PFX(ArmPlatformInitializeBootMemory) | |
83 | ||
84 | # Only Primary CPU could run this line (the secondary cores have jumped from _IdentifyCpu to _SetupStack) | |
85 | mov r5, #0 | |
86 | ||
87 | _SetupStack: | |
88 | # Setup Stack for the 4 CPU cores | |
89 | #Read Stack Base address from PCD | |
90 | LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase) ,r1) | |
91 | ||
92 | #read Stack size from PCD | |
93 | LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecStackSize) ,r2) | |
94 | ||
95 | #calcuate Stack Pointer reg value using Stack size and CPU ID. | |
96 | mov r3,r5 @ r3 = core_id | |
97 | mul r3,r3,r2 @ r3 = core_id * stack_size = offset from the stack base | |
98 | add r3,r3,r1 @ r3 ldr= stack_base + offset | |
99 | mov sp, r3 | |
100 | ||
101 | # move sec startup address into a data register | |
102 | # ensure we're jumping to FV version of the code (not boot remapped alias) | |
103 | ldr r3, StartupAddr | |
104 | ||
105 | # Move the CoreId in r0 to be the first argument of the SEC Entry Point | |
106 | mov r0, r5 | |
107 | ||
108 | # jump to SEC C code | |
109 | # r0 = core_id | |
110 | blx r3 | |
111 | ||
6377d2f1 | 112 |