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90d6a1bb | 1 | //\r |
2 | // Copyright (c) 2011, ARM Limited. All rights reserved.\r | |
3 | // \r | |
4 | // This program and the accompanying materials \r | |
5 | // are licensed and made available under the terms and conditions of the BSD License \r | |
6 | // which accompanies this distribution. The full text of the license may be found at \r | |
7 | // http://opensource.org/licenses/bsd-license.php \r | |
8 | //\r | |
9 | // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r | |
10 | // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r | |
11 | //\r | |
12 | //\r | |
13 | \r | |
14 | #include <AutoGen.h>\r | |
15 | #include <AsmMacroIoLib.h>\r | |
16 | #include "SecInternal.h"\r | |
17 | \r | |
18 | INCLUDE AsmMacroIoLib.inc\r | |
19 | \r | |
20 | IMPORT CEntryPoint\r | |
21 | IMPORT ArmPlatformSecBootAction\r | |
22 | IMPORT ArmPlatformInitializeBootMemory\r | |
23 | IMPORT ArmDisableInterrupts\r | |
24 | IMPORT ArmDisableCachesAndMmu\r | |
25 | IMPORT ArmWriteVBar\r | |
26 | IMPORT ArmReadMpidr\r | |
27 | IMPORT SecVectorTable\r | |
28 | IMPORT ArmCpuSynchronizeWait\r | |
29 | EXPORT _ModuleEntryPoint\r | |
30 | \r | |
31 | PRESERVE8\r | |
32 | AREA SecEntryPoint, CODE, READONLY\r | |
33 | \r | |
34 | StartupAddr DCD CEntryPoint\r | |
35 | \r | |
36 | _ModuleEntryPoint\r | |
37 | // First ensure all interrupts are disabled\r | |
38 | blx ArmDisableInterrupts\r | |
39 | \r | |
40 | // Ensure that the MMU and caches are off\r | |
41 | blx ArmDisableCachesAndMmu\r | |
42 | \r | |
43 | // Jump to Platform Specific Boot Action function\r | |
44 | blx ArmPlatformSecBootAction\r | |
45 | \r | |
46 | // Set VBAR to the start of the exception vectors in Secure Mode\r | |
47 | ldr r0, =SecVectorTable\r | |
48 | blx ArmWriteVBar\r | |
49 | \r | |
50 | _IdentifyCpu \r | |
51 | // Identify CPU ID\r | |
52 | bl ArmReadMpidr\r | |
53 | // Get ID of this CPU in Multicore system\r | |
54 | LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCoreMask), r1)\r | |
55 | and r5, r0, r1\r | |
56 | \r | |
57 | // Is it the Primary Core ?\r | |
58 | LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r1)\r | |
59 | cmp r5, r1\r | |
60 | // Only the primary core initialize the memory (SMC)\r | |
61 | beq _InitMem\r | |
62 | \r | |
63 | _WaitInitMem\r | |
64 | mov r0, #ARM_CPU_EVENT_BOOT_MEM_INIT\r | |
65 | bl ArmCpuSynchronizeWait\r | |
66 | // Now the Init Mem is initialized, we setup the secondary core stacks\r | |
67 | b _SetupSecondaryCoreStack\r | |
68 | \r | |
69 | _InitMem\r | |
70 | // Initialize Init Boot Memory\r | |
71 | bl ArmPlatformInitializeBootMemory\r | |
72 | \r | |
73 | // Only Primary CPU could run this line (the secondary cores have jumped from _IdentifyCpu to _SetupStack)\r | |
74 | LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r5)\r | |
75 | \r | |
76 | _SetupPrimaryCoreStack\r | |
77 | LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r2)\r | |
78 | LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecPrimaryStackSize), r3)\r | |
79 | // Calculate the Top of the Stack\r | |
80 | add r2, r2, r3\r | |
81 | LoadConstantToReg (FixedPcdGet32(PcdSecGlobalVariableSize), r3)\r | |
82 | \r | |
83 | // The reserved space for global variable must be 8-bytes aligned for pushing\r | |
84 | // 64-bit variable on the stack\r | |
85 | SetPrimaryStack (r2, r3, r1)\r | |
86 | \r | |
87 | // Set all the SEC global variables to 0\r | |
88 | mov r3, sp\r | |
89 | mov r1, #0x0\r | |
90 | _InitGlobals\r | |
91 | str r1, [r3], #4\r | |
92 | cmp r3, r2\r | |
031f52ce | 93 | bne _InitGlobals\r |
90d6a1bb | 94 | \r |
95 | b _PrepareArguments\r | |
96 | \r | |
97 | _SetupSecondaryCoreStack\r | |
98 | // Get the Core Position (ClusterId * 4) + CoreId\r | |
99 | GetCorePositionInStack(r0, r5, r1)\r | |
100 | // The stack starts at the top of the stack region. Add '1' to the Core Position to get the top of the stack\r | |
101 | add r0, r0, #1\r | |
102 | \r | |
103 | // Get the base of the stack for the secondary cores\r | |
104 | LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r1)\r | |
105 | LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecSecondaryStackSize), r2)\r | |
106 | add r1, r1, r2\r | |
107 | \r | |
108 | // StackOffset = CorePos * StackSize\r | |
109 | mul r0, r0, r2\r | |
110 | // SP = StackBase + StackOffset\r | |
111 | add sp, r1, r0\r | |
112 | \r | |
113 | \r | |
114 | _PrepareArguments\r | |
115 | // Move sec startup address into a data register\r | |
116 | // Ensure we're jumping to FV version of the code (not boot remapped alias)\r | |
117 | ldr r3, StartupAddr\r | |
118 | \r | |
119 | // Jump to SEC C code\r | |
120 | // r0 = mp_id\r | |
121 | mov r0, r5\r | |
122 | blx r3\r | |
123 | \r | |
124 | _NeverReturn\r | |
125 | b _NeverReturn\r | |
126 | END\r |