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1d5d0ae9 | 1 | // |
2 | // Copyright (c) 2011, ARM Limited. All rights reserved. | |
3 | // | |
4 | // This program and the accompanying materials | |
5 | // are licensed and made available under the terms and conditions of the BSD License | |
6 | // which accompanies this distribution. The full text of the license may be found at | |
7 | // http://opensource.org/licenses/bsd-license.php | |
8 | // | |
9 | // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, | |
10 | // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. | |
11 | // | |
12 | // | |
13 | ||
14 | #include <AutoGen.h> | |
15 | #include <AsmMacroIoLib.h> | |
16 | #include <Base.h> | |
17 | #include <Library/PcdLib.h> | |
18 | #include <Library/ArmPlatformLib.h> | |
19 | ||
20 | INCLUDE AsmMacroIoLib.inc | |
21 | ||
22 | IMPORT CEntryPoint | |
44e272fd | 23 | IMPORT ArmPlatformSecBootAction |
1d5d0ae9 | 24 | IMPORT ArmPlatformInitializeBootMemory |
25 | IMPORT ArmDisableInterrupts | |
26 | IMPORT ArmDisableCachesAndMmu | |
27 | IMPORT ArmWriteVBar | |
28 | IMPORT ArmReadMpidr | |
29 | IMPORT SecVectorTable | |
30 | EXPORT _ModuleEntryPoint | |
31 | ||
32 | #if (FixedPcdGet32(PcdMPCoreSupport)) | |
33 | IMPORT ArmIsScuEnable | |
34 | #endif | |
35 | ||
36 | PRESERVE8 | |
37 | AREA SecEntryPoint, CODE, READONLY | |
38 | ||
39 | StartupAddr DCD CEntryPoint | |
40 | ||
41 | _ModuleEntryPoint | |
1d5d0ae9 | 42 | // First ensure all interrupts are disabled |
43 | blx ArmDisableInterrupts | |
44 | ||
45 | // Ensure that the MMU and caches are off | |
46 | blx ArmDisableCachesAndMmu | |
47 | ||
44e272fd | 48 | // Jump to Platform Specific Boot Action function |
49 | blx ArmPlatformSecBootAction | |
50 | ||
51 | // Set VBAR to the start of the exception vectors in Secure Mode | |
52 | ldr r0, =SecVectorTable | |
53 | blx ArmWriteVBar | |
54 | ||
1d5d0ae9 | 55 | _IdentifyCpu |
56 | // Identify CPU ID | |
57 | bl ArmReadMpidr | |
0787bc61 | 58 | // Get ID of this CPU in Multicore system |
59 | LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCoreMask), r1) | |
60 | and r5, r0, r1 | |
1d5d0ae9 | 61 | |
0787bc61 | 62 | // Is it the Primary Core ? |
63 | LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r1) | |
64 | cmp r5, r1 | |
1d5d0ae9 | 65 | // Only the primary core initialize the memory (SMC) |
66 | beq _InitMem | |
67 | ||
68 | #if (FixedPcdGet32(PcdMPCoreSupport)) | |
69 | // ... The secondary cores wait for SCU to be enabled | |
70 | _WaitForEnabledScu | |
71 | bl ArmIsScuEnable | |
72 | tst r1, #1 | |
73 | beq _WaitForEnabledScu | |
2dbcb8f0 | 74 | b _SetupSecondaryCoreStack |
1d5d0ae9 | 75 | #endif |
76 | ||
77 | _InitMem | |
f156d5b4 | 78 | // Initialize Init Boot Memory |
1d5d0ae9 | 79 | bl ArmPlatformInitializeBootMemory |
2dbcb8f0 | 80 | |
1d5d0ae9 | 81 | // Only Primary CPU could run this line (the secondary cores have jumped from _IdentifyCpu to _SetupStack) |
2dbcb8f0 | 82 | LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r5) |
83 | ||
84 | _SetupPrimaryCoreStack | |
85 | LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r2) | |
86 | LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecPrimaryStackSize), r3) | |
87 | // Calculate the Top of the Stack | |
88 | add r2, r2, r3 | |
89 | LoadConstantToReg (FixedPcdGet32(PcdSecGlobalVariableSize), r3) | |
90 | ||
91 | // The reserved space for global variable must be 8-bytes aligned for pushing | |
92 | // 64-bit variable on the stack | |
93 | SetPrimaryStack (r2, r3, r1) | |
94 | ||
95 | // Set all the SEC global variables to 0 | |
96 | mov r3, sp | |
97 | mov r1, #0x0 | |
98 | _InitGlobals | |
99 | str r1, [r3], #4 | |
100 | cmp r3, r2 | |
101 | blt _InitGlobals | |
1d5d0ae9 | 102 | |
2dbcb8f0 | 103 | b _PrepareArguments |
104 | ||
105 | _SetupSecondaryCoreStack | |
106 | // Get the Core Position (ClusterId * 4) + CoreId | |
107 | GetCorePositionInStack(r0, r5, r1) | |
108 | // The stack starts at the top of the stack region. Add '1' to the Core Position to get the top of the stack | |
109 | add r0, r0, #1 | |
110 | ||
111 | // Get the base of the stack for the secondary cores | |
1d5d0ae9 | 112 | LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r1) |
2dbcb8f0 | 113 | LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecSecondaryStackSize), r2) |
114 | add r1, r1, r2 | |
1d5d0ae9 | 115 | |
2dbcb8f0 | 116 | // StackOffset = CorePos * StackSize |
117 | mul r0, r0, r2 | |
118 | // SP = StackBase + StackOffset | |
119 | add sp, r1, r0 | |
1d5d0ae9 | 120 | |
2dbcb8f0 | 121 | |
122 | _PrepareArguments | |
1d5d0ae9 | 123 | // Move sec startup address into a data register |
2dbcb8f0 | 124 | // Ensure we're jumping to FV version of the code (not boot remapped alias) |
1d5d0ae9 | 125 | ldr r3, StartupAddr |
126 | ||
127 | // Jump to SEC C code | |
0787bc61 | 128 | // r0 = mp_id |
1d5d0ae9 | 129 | mov r0, r5 |
130 | blx r3 | |
131 | ||
2dbcb8f0 | 132 | _NeverReturn |
133 | b _NeverReturn | |
1d5d0ae9 | 134 | END |