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5b1928ff | 1 | /** @file\r |
2 | * Main file supporting the SEC Phase on ARM PLatforms\r | |
3 | *\r | |
4 | * Copyright (c) 2011, ARM Limited. All rights reserved.\r | |
5 | *\r | |
6 | * This program and the accompanying materials\r | |
7 | * are licensed and made available under the terms and conditions of the BSD License\r | |
8 | * which accompanies this distribution. The full text of the license may be found at\r | |
9 | * http://opensource.org/licenses/bsd-license.php\r | |
10 | *\r | |
11 | * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
12 | * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
13 | *\r | |
14 | **/\r | |
15 | \r | |
16 | #ifndef __SEC_H__\r | |
17 | #define __SEC_H__\r | |
18 | \r | |
19 | #include <Base.h>\r | |
90d6a1bb | 20 | #include <Library/ArmLib.h>\r |
21 | #include <Library/ArmCpuLib.h>\r | |
22 | #include <Library/ArmPlatformLib.h>\r | |
5b1928ff | 23 | #include <Library/BaseLib.h>\r |
24 | #include <Library/DebugLib.h>\r | |
90d6a1bb | 25 | #include <Library/PcdLib.h>\r |
5b1928ff | 26 | \r |
27 | #define IS_ALIGNED(Address, Align) (((UINTN)Address & (Align-1)) == 0)\r | |
28 | \r | |
29 | VOID\r | |
30 | ArmSetupGicNonSecure (\r | |
31 | IN INTN GicDistributorBase,\r | |
32 | IN INTN GicInterruptInterfaceBase\r | |
33 | );\r | |
34 | \r | |
35 | // Vector Table for Sec Phase\r | |
36 | VOID\r | |
37 | SecVectorTable (\r | |
38 | VOID\r | |
39 | );\r | |
40 | \r | |
41 | VOID\r | |
42 | NonSecureWaitForFirmware (\r | |
43 | VOID\r | |
44 | );\r | |
45 | \r | |
46 | VOID\r | |
47 | enter_monitor_mode (\r | |
48 | IN VOID* Stack\r | |
49 | );\r | |
50 | \r | |
51 | VOID\r | |
52 | return_from_exception (\r | |
53 | IN UINTN NonSecureBase\r | |
54 | );\r | |
55 | \r | |
56 | VOID\r | |
57 | copy_cpsr_into_spsr (\r | |
58 | VOID\r | |
59 | );\r | |
60 | \r | |
513aa349 | 61 | VOID\r |
62 | set_non_secure_mode (\r | |
63 | IN ARM_PROCESSOR_MODE Mode\r | |
64 | );\r | |
65 | \r | |
5b1928ff | 66 | VOID\r |
67 | SecCommonExceptionEntry (\r | |
68 | IN UINT32 Entry,\r | |
69 | IN UINT32 LR\r | |
70 | );\r | |
71 | \r | |
72 | #endif\r |