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1fde2f61 | 1 | #------------------------------------------------------------------------------ \r |
2 | #\r | |
4ade93d0 | 3 | # ARM EB Entry point. Reset vector in FV header will brach to\r |
4 | # _ModuleEntryPoint. \r | |
5 | #\r | |
6 | # We use crazy macros, like LoadConstantToReg, since Xcode assembler \r | |
7 | # does not support = assembly syntax for ldr.\r | |
8 | #\r | |
cf748a1a | 9 | # Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r |
1fde2f61 | 10 | #\r |
cf748a1a | 11 | # This program and the accompanying materials\r |
1fde2f61 | 12 | # are licensed and made available under the terms and conditions of the BSD License\r |
13 | # which accompanies this distribution. The full text of the license may be found at\r | |
14 | # http://opensource.org/licenses/bsd-license.php\r | |
15 | #\r | |
16 | # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
17 | # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
18 | #\r | |
19 | #------------------------------------------------------------------------------\r | |
20 | \r | |
21 | #include <AsmMacroIoLib.h>\r | |
4ade93d0 | 22 | #include <Base.h>\r |
1fde2f61 | 23 | #include <Library/PcdLib.h>\r |
4ade93d0 | 24 | #include <ArmEb/ArmEb.h>\r |
1fde2f61 | 25 | \r |
26 | .text\r | |
27 | .align 3\r | |
28 | \r | |
29 | .globl ASM_PFX(CEntryPoint)\r | |
30 | .globl ASM_PFX(_ModuleEntryPoint)\r | |
afdfe8f0 | 31 | .globl ASM_PFX(StartupAddr)\r |
1fde2f61 | 32 | \r |
8b4eff76 | 33 | \r |
7668305c | 34 | ASM_PFX(StartupAddr): .word ASM_PFX(CEntryPoint)\r |
8b4eff76 | 35 | \r |
1fde2f61 | 36 | ASM_PFX(_ModuleEntryPoint):\r |
4ade93d0 | 37 | \r |
38 | // Turn off remapping NOR to 0. We can now use DRAM in low memory\r | |
afdfe8f0 | 39 | // CAN'T DO THIS HERE -- BRANCH FROM RESET VECTOR IS RELATIVE AND REMAINS IN REMAPPED NOR\r |
40 | //MmioOr32 (0x10001000 ,BIT8) //EB_SP810_CTRL_BASE\r | |
4ade93d0 | 41 | \r |
42 | // Enable NEON register in case folks want to use them for optimizations (CopyMem)\r | |
43 | mrc p15, 0, r0, c1, c0, 2\r | |
afdfe8f0 | 44 | orr r0, r0, #0x00f00000 // Enable VFP access (V* instructions)\r |
4ade93d0 | 45 | mcr p15, 0, r0, c1, c0, 2\r |
46 | mov r0, #0x40000000 // Set EN bit in FPEXC\r | |
fe211121 | 47 | mcr p10,#0x7,r0,c8,c0,#0 // msr FPEXC,r0 in ARM assembly\r |
4ade93d0 | 48 | \r |
afdfe8f0 | 49 | // Set CPU vectors to 0 (which is currently flash)\r |
4ade93d0 | 50 | LoadConstantToReg (FixedPcdGet32(PcdCpuVectorBaseAddress) ,r0) // Get vector base\r |
51 | mcr p15, 0, r0, c12, c0, 0\r | |
52 | isb // Sync changes to control registers\r | |
53 | \r | |
1fde2f61 | 54 | //\r |
55 | // Set stack based on PCD values. Need to do it this way to make C code work \r | |
56 | // when it runs from FLASH. \r | |
57 | // \r | |
afdfe8f0 | 58 | LoadConstantToReg (FixedPcdGet32(PcdPrePiStackBase) ,r0) // temp ram base arg 0 TODO: change "stackbase" to "temprambase"\r |
59 | LoadConstantToReg (FixedPcdGet32(PcdPrePiStackSize) ,r1) // temp ram size arg 1\r | |
60 | lsr r3, r1, #1 // r4 = size of temp mem / 2\r | |
61 | add r3, r3, r0 // r2 = temp ram base + r4\r | |
62 | mov r13, r3 // result: stack pointer = temp ram base + (size of temp mem / 2)\r | |
63 | \r | |
64 | // lr points to area in reset vector block containing PEI core address\r | |
65 | ldr r2, [lr] // pei core arg 3\r | |
66 | \r | |
67 | // move sec startup address into a data register\r | |
68 | // ensure we're jumping to FV version of the code (not boot remapped alias)\r | |
7668305c | 69 | ldr r4, ASM_PFX(StartupAddr) // Extra level of indirection fixes Xcode relocation issue\r |
1fde2f61 | 70 | \r |
afdfe8f0 | 71 | // jump to SEC C code\r |
72 | blx r4\r | |
afdfe8f0 | 73 | \r |
1fde2f61 | 74 | \r |
afdfe8f0 | 75 | ASM_PFX(ShouldNeverGetHere):\r |
4ade93d0 | 76 | // _CEntryPoint should never return \r |
afdfe8f0 | 77 | b ASM_PFX(ShouldNeverGetHere)\r |
1fde2f61 | 78 | \r |
4ade93d0 | 79 | \r |