projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| 7f21c4a2 | 1 | /** @file\r |
| 2 | *\r | |
| 3 | * Copyright (c) 2011, ARM Limited. All rights reserved.\r | |
| 7f21c4a2 | 4 | *\r |
| a1594be9 | 5 | * SPDX-License-Identifier: BSD-2-Clause-Patent\r |
| 7f21c4a2 | 6 | *\r |
| 7 | **/\r | |
| 8 | \r | |
| 9 | #include <Library/ArmPlatformLib.h>\r | |
| 10 | #include <Library/DebugLib.h>\r | |
| 11 | #include <Library/PcdLib.h>\r | |
| 12 | #include <Library/MemoryAllocationLib.h>\r | |
| 13 | #include <Library/IoLib.h>\r | |
| 14 | \r | |
| 15 | #include <BeagleBoard.h>\r | |
| 16 | \r | |
| 17 | #define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 4\r | |
| 18 | \r | |
| 19 | /**\r | |
| 20 | Return the Virtual Memory Map of your platform\r | |
| 21 | \r | |
| 22 | This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform.\r | |
| 23 | \r | |
| 24 | @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-\r | |
| 25 | Virtual Memory mapping. This array must be ended by a zero-filled\r | |
| 26 | entry\r | |
| 27 | \r | |
| 28 | **/\r | |
| 29 | VOID\r | |
| 30 | ArmPlatformGetVirtualMemoryMap (\r | |
| 31 | IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap\r | |
| 32 | )\r | |
| 33 | {\r | |
| 34 | ARM_MEMORY_REGION_ATTRIBUTES CacheAttributes;\r | |
| 35 | UINTN Index = 0;\r | |
| 36 | ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;\r | |
| 37 | \r | |
| 38 | ASSERT(VirtualMemoryMap != NULL);\r | |
| 39 | \r | |
| 40 | VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(EFI_SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS));\r | |
| 41 | if (VirtualMemoryTable == NULL) {\r | |
| 42 | return;\r | |
| 43 | }\r | |
| 44 | \r | |
| f72df138 | 45 | CacheAttributes = DDR_ATTRIBUTES_CACHED;\r |
| 7f21c4a2 | 46 | \r |
| 47 | // ReMap (Either NOR Flash or DRAM)\r | |
| c357fd6a OM |
48 | VirtualMemoryTable[Index].PhysicalBase = PcdGet64 (PcdSystemMemoryBase);\r |
| 49 | VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdSystemMemoryBase);\r | |
| 50 | VirtualMemoryTable[Index].Length = PcdGet64 (PcdSystemMemorySize);\r | |
| 7f21c4a2 | 51 | VirtualMemoryTable[Index].Attributes = CacheAttributes;\r |
| 52 | \r | |
| 53 | // SOC Registers. L3 interconnects\r | |
| 54 | VirtualMemoryTable[++Index].PhysicalBase = SOC_REGISTERS_L3_PHYSICAL_BASE;\r | |
| 55 | VirtualMemoryTable[Index].VirtualBase = SOC_REGISTERS_L3_PHYSICAL_BASE;\r | |
| 56 | VirtualMemoryTable[Index].Length = SOC_REGISTERS_L3_PHYSICAL_LENGTH;\r | |
| 57 | VirtualMemoryTable[Index].Attributes = SOC_REGISTERS_L3_ATTRIBUTES;\r | |
| 58 | \r | |
| 59 | // SOC Registers. L4 interconnects\r | |
| 60 | VirtualMemoryTable[++Index].PhysicalBase = SOC_REGISTERS_L4_PHYSICAL_BASE;\r | |
| 61 | VirtualMemoryTable[Index].VirtualBase = SOC_REGISTERS_L4_PHYSICAL_BASE;\r | |
| 62 | VirtualMemoryTable[Index].Length = SOC_REGISTERS_L4_PHYSICAL_LENGTH;\r | |
| 63 | VirtualMemoryTable[Index].Attributes = SOC_REGISTERS_L4_ATTRIBUTES;\r | |
| 64 | \r | |
| 65 | // End of Table\r | |
| 66 | VirtualMemoryTable[++Index].PhysicalBase = 0;\r | |
| 67 | VirtualMemoryTable[Index].VirtualBase = 0;\r | |
| 68 | VirtualMemoryTable[Index].Length = 0;\r | |
| 69 | VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0;\r | |
| 70 | \r | |
| 71 | ASSERT((Index + 1) == MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);\r | |
| 72 | \r | |
| 73 | *VirtualMemoryMap = VirtualMemoryTable;\r | |
| 74 | }\r |