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1 | #------------------------------------------------------------------------------ \r |
2 | #\r | |
3 | # Copyright (c) 2008-2009 Apple Inc. All rights reserved.\r | |
4 | #\r | |
5 | # All rights reserved. This program and the accompanying materials\r | |
6 | # are licensed and made available under the terms and conditions of the BSD License\r | |
7 | # which accompanies this distribution. The full text of the license may be found at\r | |
8 | # http://opensource.org/licenses/bsd-license.php\r | |
9 | #\r | |
10 | # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
12 | #\r | |
13 | #------------------------------------------------------------------------------\r | |
14 | \r | |
15 | #include <AsmMacroIoLib.h>\r | |
16 | #include <Library/PcdLib.h>\r | |
17 | \r | |
18 | .text\r | |
19 | .align 3\r | |
20 | \r | |
21 | .globl ASM_PFX(CEntryPoint)\r | |
22 | .globl ASM_PFX(_ModuleEntryPoint)\r | |
23 | \r | |
24 | ASM_PFX(_ModuleEntryPoint):\r | |
25 | \r | |
26 | //Disable L2 cache\r | |
27 | mrc p15, 0, r0, c1, c0, 1 // read Auxiliary Control Register\r | |
28 | bic r0, r0, #0x00000002 // disable L2 cache\r | |
29 | mcr p15, 0, r0, c1, c0, 1 // store Auxiliary Control Register\r | |
30 | \r | |
31 | //Enable Strict alignment checking & Instruction cache\r | |
32 | mrc p15, 0, r0, c1, c0, 0\r | |
33 | bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */\r | |
34 | bic r0, r0, #0x00000005 /* clear bits 0, 2 (---- -C-M) */\r | |
35 | orr r0, r0, #0x00000002 /* set bit 1 (A) Align */\r | |
36 | orr r0, r0, #0x00001000 /* set bit 12 (I) enable I-Cache */\r | |
37 | mcr p15, 0, r0, c1, c0, 0\r | |
38 | \r | |
39 | // Set CPU vectors to start of DRAM\r | |
40 | mov r0, #0x80000000\r | |
41 | mcr p15, 0, r0, c12, c0, 0\r | |
42 | \r | |
43 | /* before we call C code, lets setup the stack pointer */\r | |
44 | stack_pointer_setup:\r | |
45 | \r | |
46 | //\r | |
47 | // Set stack based on PCD values. Need to do it this way to make C code work \r | |
48 | // when it runs from FLASH. \r | |
49 | // \r | |
50 | LoadConstantToReg (FixedPcdGet32(PcdPrePiStackBase) ,r2) /* stack base arg2 */\r | |
51 | LoadConstantToReg (FixedPcdGet32(PcdPrePiStackSize) ,r3) /* stack size arg3 */\r | |
52 | add r4, r2, r3\r | |
53 | \r | |
54 | //Enter IRQ mode and set up IRQ stack pointer\r | |
55 | mov r0,#0x12|0x80|0x40\r | |
56 | msr CPSR_c,r0\r | |
57 | mov r13,r4\r | |
58 | \r | |
59 | //Enter Abort mode and set up Abort stack pointer\r | |
60 | mov r0,#0x17|0x80|0x40\r | |
61 | msr CPSR_c,r0\r | |
62 | sub r4, r4, #0x400\r | |
63 | mov r13,r4\r | |
64 | \r | |
65 | //Enter Undefined mode and set up Undefined stack pointer\r | |
66 | mov r0,#0x1b|0x80|0x40\r | |
67 | msr CPSR_c,r0\r | |
68 | sub r4, r4, #0x400\r | |
69 | mov r13,r4\r | |
70 | \r | |
71 | //Enter SVC mode and set up SVC stack pointer\r | |
72 | mov r0,#0x13|0x80|0x40\r | |
73 | msr CPSR_c,r0\r | |
74 | sub r4, r4, #0x400\r | |
75 | mov r13,r4\r | |
76 | \r | |
77 | //Enter System mode and set up System stack pointer\r | |
78 | mov r0,#0x1f|0x80|0x40\r | |
79 | msr CPSR_c,r0\r | |
80 | sub r4, r4, #0x400\r | |
81 | mov r13,r4\r | |
82 | \r | |
83 | // Call C entry point\r | |
753816a3 | 84 | LoadConstantToReg (FixedPcdGet32(PcdMemorySize) ,r1) /* memory size arg1 */\r |
85 | LoadConstantToReg (FixedPcdGet32(PcdMemoryBase) ,r0) /* memory size arg0 */\r | |
86 | \r | |
2ef2b01e | 87 | \r |
753816a3 | 88 | blx ASM_PFX(CEntryPoint) /* Assume C code is ARM */\r |
2ef2b01e A |
89 | \r |
90 | ShouldNeverGetHere:\r | |
91 | /* _CEntryPoint should never return */\r | |
92 | b ShouldNeverGetHere\r | |
93 | \r | |
94 | \r |