projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| 2ef2b01e A |
1 | //------------------------------------------------------------------------------ \r |
| 2 | //\r | |
| 3 | // Copyright (c) 2008-2009 Apple Inc. All rights reserved.\r | |
| 4 | //\r | |
| 5 | // All rights reserved. This program and the accompanying materials\r | |
| 6 | // are licensed and made available under the terms and conditions of the BSD License\r | |
| 7 | // which accompanies this distribution. The full text of the license may be found at\r | |
| 8 | // http://opensource.org/licenses/bsd-license.php\r | |
| 9 | //\r | |
| 10 | // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
| 11 | // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
| 12 | //\r | |
| 13 | //------------------------------------------------------------------------------\r | |
| 14 | \r | |
| 15 | #include <AsmMacroIoLib.h>\r | |
| 16 | #include <Library/PcdLib.h>\r | |
| 17 | #include <AutoGen.h>\r | |
| 18 | INCLUDE AsmMacroIoLib.inc\r | |
| 19 | \r | |
| 20 | IMPORT CEntryPoint\r | |
| 21 | EXPORT _ModuleEntryPoint\r | |
| 22 | \r | |
| 23 | PRESERVE8\r | |
| 24 | AREA ModuleEntryPoint, CODE, READONLY\r | |
| 25 | \r | |
| 26 | \r | |
| 27 | _ModuleEntryPoint\r | |
| 28 | \r | |
| 29 | //Disable L2 cache\r | |
| 30 | mrc p15, 0, r0, c1, c0, 1 // read Auxiliary Control Register\r | |
| 31 | bic r0, r0, #0x00000002 // disable L2 cache\r | |
| 32 | mcr p15, 0, r0, c1, c0, 1 // store Auxiliary Control Register\r | |
| 33 | \r | |
| 34 | //Enable Strict alignment checking & Instruction cache\r | |
| 35 | mrc p15, 0, r0, c1, c0, 0\r | |
| 36 | bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */\r | |
| 37 | bic r0, r0, #0x00000005 /* clear bits 0, 2 (---- -C-M) */\r | |
| 38 | orr r0, r0, #0x00000002 /* set bit 1 (A) Align */\r | |
| 39 | orr r0, r0, #0x00001000 /* set bit 12 (I) enable I-Cache */\r | |
| 40 | mcr p15, 0, r0, c1, c0, 0\r | |
| 41 | \r | |
| 42 | // Set CPU vectors to start of DRAM\r | |
| 43 | mov r0, #0x80000000\r | |
| 44 | mcr p15, 0, r0, c12, c0, 0\r | |
| 45 | /* before we call C code, lets setup the stack pointer in internal RAM*/\r | |
| 46 | stack_pointer_setup\r | |
| 47 | \r | |
| 48 | //\r | |
| 49 | // Set stack based on PCD values. Need to do it this way to make C code work \r | |
| 50 | // when it runs from FLASH. \r | |
| 51 | // \r | |
| 52 | LoadConstantToReg (FixedPcdGet32(PcdPrePiStackBase) ,r2) /* stack base arg2 */\r | |
| 53 | LoadConstantToReg (FixedPcdGet32(PcdPrePiStackSize) ,r3) /* stack size arg3 */\r | |
| 54 | add r4, r2, r3\r | |
| 55 | \r | |
| 56 | //Enter IRQ mode and set up IRQ stack pointer\r | |
| 57 | mov r0,#0x12|0x80|0x40\r | |
| 58 | msr CPSR_c,r0\r | |
| 59 | mov r13,r4\r | |
| 60 | \r | |
| 61 | //Enter Abort mode and set up Abort stack pointer\r | |
| 62 | mov r0,#0x17|0x80|0x40\r | |
| 63 | msr CPSR_c,r0\r | |
| 64 | sub r4, r4, #0x400\r | |
| 65 | mov r13,r4\r | |
| 66 | \r | |
| 67 | //Enter Undefined mode and set up Undefined stack pointer\r | |
| 68 | mov r0,#0x1b|0x80|0x40\r | |
| 69 | msr CPSR_c,r0\r | |
| 70 | sub r4, r4, #0x400\r | |
| 71 | mov r13,r4\r | |
| 72 | \r | |
| 73 | //Enter SVC mode and set up SVC stack pointer\r | |
| 74 | mov r0,#0x13|0x80|0x40\r | |
| 75 | msr CPSR_c,r0\r | |
| 76 | sub r4, r4, #0x400\r | |
| 77 | mov r13,r4\r | |
| 78 | \r | |
| 79 | //Enter System mode and set up System stack pointer\r | |
| 80 | mov r0,#0x1f|0x80|0x40\r | |
| 81 | msr CPSR_c,r0\r | |
| 82 | sub r4, r4, #0x400\r | |
| 83 | mov r13,r4\r | |
| 84 | \r | |
| 85 | // Call C entry point\r | |
| 86 | mov r0, #0x80000000 /* memory base arg0 */\r | |
| 87 | mov r1, #0x08000000 /* memory size arg1 */\r | |
| 88 | blx CEntryPoint /* Assume C code is thumb */\r | |
| 89 | \r | |
| 90 | ShouldNeverGetHere\r | |
| 91 | /* _CEntryPoint should never return */\r | |
| 92 | b ShouldNeverGetHere\r | |
| 93 | \r | |
| 94 | END\r | |
| 95 | \r |