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bae5ddc0 SZ |
1 | /** @file\r |
2 | Platform Hook Library instance for UART device upon coreboot.\r | |
3 | \r | |
4 | Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>\r | |
5 | This program and the accompanying materials\r | |
6 | are licensed and made available under the terms and conditions of the BSD License\r | |
7 | which accompanies this distribution. The full text of the license may be found at\r | |
8 | http://opensource.org/licenses/bsd-license.php\r | |
9 | \r | |
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
12 | \r | |
13 | **/\r | |
14 | \r | |
15 | #include <Base.h>\r | |
16 | #include <Uefi/UefiBaseType.h>\r | |
24ca2f35 | 17 | #include <Library/PciLib.h> |
bae5ddc0 SZ |
18 | #include <Library/PlatformHookLib.h>\r |
19 | #include <Library/CbParseLib.h>\r | |
20 | #include <Library/PcdLib.h>\r | |
21 | \r | |
24ca2f35 LL |
22 | typedef struct { |
23 | UINT16 VendorId; ///< Vendor ID to match the PCI device. The value 0xFFFF terminates the list of entries. | |
24 | UINT16 DeviceId; ///< Device ID to match the PCI device | |
25 | UINT32 ClockRate; ///< UART clock rate. Set to 0 for default clock rate of 1843200 Hz | |
26 | UINT64 Offset; ///< The byte offset into to the BAR | |
27 | UINT8 BarIndex; ///< Which BAR to get the UART base address | |
28 | UINT8 RegisterStride; ///< UART register stride in bytes. Set to 0 for default register stride of 1 byte. | |
29 | UINT16 ReceiveFifoDepth; ///< UART receive FIFO depth in bytes. Set to 0 for a default FIFO depth of 16 bytes. | |
30 | UINT16 TransmitFifoDepth; ///< UART transmit FIFO depth in bytes. Set to 0 for a default FIFO depth of 16 bytes. | |
31 | UINT8 Reserved[2]; | |
32 | } PCI_SERIAL_PARAMETER; | |
33 | ||
bae5ddc0 SZ |
34 | /**\r |
35 | Performs platform specific initialization required for the CPU to access\r | |
36 | the hardware associated with a SerialPortLib instance. This function does\r | |
37 | not intiailzie the serial port hardware itself. Instead, it initializes\r | |
38 | hardware devices that are required for the CPU to access the serial port\r | |
39 | hardware. This function may be called more than once.\r | |
40 | \r | |
41 | @retval RETURN_SUCCESS The platform specific initialization succeeded.\r | |
42 | @retval RETURN_DEVICE_ERROR The platform specific initialization could not be completed.\r | |
43 | \r | |
44 | **/\r | |
45 | RETURN_STATUS\r | |
46 | EFIAPI\r | |
47 | PlatformHookSerialPortInitialize (\r | |
48 | VOID\r | |
49 | )\r | |
50 | {\r | |
51 | RETURN_STATUS Status;\r | |
52 | UINT32 SerialRegBase;\r | |
53 | UINT32 SerialRegAccessType;\r | |
24ca2f35 LL |
54 | UINT32 BaudRate; |
55 | UINT32 RegWidth; | |
56 | UINT32 InputHertz; | |
57 | UINT32 PayloadParam; | |
58 | UINT32 DeviceVendor; | |
59 | PCI_SERIAL_PARAMETER *SerialParam; | |
bae5ddc0 | 60 | \r |
24ca2f35 LL |
61 | Status = CbParseSerialInfo (&SerialRegBase, &SerialRegAccessType, |
62 | &RegWidth, &BaudRate, &InputHertz, | |
63 | &PayloadParam); | |
bae5ddc0 SZ |
64 | if (RETURN_ERROR (Status)) {\r |
65 | return Status;\r | |
66 | }\r | |
67 | \r | |
68 | if (SerialRegAccessType == 2) { //MMIO\r | |
53f97bdc | 69 | Status = PcdSetBoolS (PcdSerialUseMmio, TRUE);\r |
bae5ddc0 | 70 | } else { //IO\r |
53f97bdc SZ |
71 | Status = PcdSetBoolS (PcdSerialUseMmio, FALSE);\r |
72 | }\r | |
73 | if (RETURN_ERROR (Status)) {\r | |
74 | return Status;\r | |
75 | }\r | |
76 | Status = PcdSet64S (PcdSerialRegisterBase, (UINT64) SerialRegBase);\r | |
77 | if (RETURN_ERROR (Status)) {\r | |
78 | return Status;\r | |
bae5ddc0 | 79 | }\r |
bae5ddc0 | 80 | \r |
24ca2f35 LL |
81 | Status = PcdSet32S (PcdSerialRegisterStride, RegWidth); |
82 | if (RETURN_ERROR (Status)) { | |
83 | return Status; | |
84 | } | |
85 | ||
86 | Status = PcdSet32S (PcdSerialBaudRate, BaudRate); | |
87 | if (RETURN_ERROR (Status)) { | |
88 | return Status; | |
89 | } | |
90 | ||
91 | Status = PcdSet64S (PcdUartDefaultBaudRate, BaudRate); | |
92 | if (RETURN_ERROR (Status)) { | |
93 | return Status; | |
94 | } | |
95 | ||
96 | Status = PcdSet32S (PcdSerialClockRate, InputHertz); | |
97 | if (RETURN_ERROR (Status)) { | |
98 | return Status; | |
99 | } | |
100 | ||
101 | if (PayloadParam >= 0x80000000) { | |
102 | DeviceVendor = PciRead32 (PayloadParam & 0x0ffff000); | |
103 | SerialParam = PcdGetPtr(PcdPciSerialParameters); | |
104 | SerialParam->VendorId = (UINT16)DeviceVendor; | |
105 | SerialParam->DeviceId = DeviceVendor >> 16; | |
106 | SerialParam->ClockRate = InputHertz; | |
107 | SerialParam->RegisterStride = (UINT8)RegWidth; | |
108 | } | |
109 | ||
bae5ddc0 SZ |
110 | return RETURN_SUCCESS;\r |
111 | }\r |