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Commit | Line | Data |
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b3f7ed03 RH |
1 | * ARM Generic Interrupt Controller |
2 | ||
3 | ARM SMP cores are often associated with a GIC, providing per processor | |
4 | interrupts (PPI), shared processor interrupts (SPI) and software | |
5 | generated interrupts (SGI). | |
6 | ||
7 | Primary GIC is attached directly to the CPU and typically has PPIs and SGIs. | |
8 | Secondary GICs are cascaded into the upward interrupt controller and do not | |
9 | have PPIs or SGIs. | |
10 | ||
11 | Main node required properties: | |
12 | ||
13 | - compatible : should be one of: | |
8709b9eb GU |
14 | "arm,arm1176jzf-devchip-gic" |
15 | "arm,arm11mp-gic" | |
0a68214b | 16 | "arm,cortex-a15-gic" |
0a68214b | 17 | "arm,cortex-a7-gic" |
8709b9eb | 18 | "arm,cortex-a9-gic" |
82b0a434 | 19 | "arm,eb11mp-gic" |
8709b9eb GU |
20 | "arm,gic-400" |
21 | "arm,pl390" | |
126aebd0 | 22 | "arm,tc11mp-gic" |
f80b7139 | 23 | "brcm,brahma-b15-gic" |
39f8f23d | 24 | "nvidia,tegra210-agic" |
2d9ad4f8 KG |
25 | "qcom,msm-8660-qgic" |
26 | "qcom,msm-qgic2" | |
b3f7ed03 RH |
27 | - interrupt-controller : Identifies the node as an interrupt controller |
28 | - #interrupt-cells : Specifies the number of cells needed to encode an | |
29 | interrupt source. The type shall be a <u32> and the value shall be 3. | |
30 | ||
31 | The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI | |
32 | interrupts. | |
33 | ||
34 | The 2nd cell contains the interrupt number for the interrupt type. | |
35 | SPI interrupts are in the range [0-987]. PPI interrupts are in the | |
36 | range [0-15]. | |
37 | ||
38 | The 3rd cell is the flags, encoded as follows: | |
39 | bits[3:0] trigger type and level flags. | |
40 | 1 = low-to-high edge triggered | |
fb7e7deb | 41 | 2 = high-to-low edge triggered (invalid for SPIs) |
b3f7ed03 | 42 | 4 = active high level-sensitive |
fb7e7deb | 43 | 8 = active low level-sensitive (invalid for SPIs). |
b3f7ed03 RH |
44 | bits[15:8] PPI interrupt cpu mask. Each bit corresponds to each of |
45 | the 8 possible cpus attached to the GIC. A bit set to '1' indicated | |
46 | the interrupt is wired to that CPU. Only valid for PPI interrupts. | |
fb7e7deb LD |
47 | Also note that the configurability of PPI interrupts is IMPLEMENTATION |
48 | DEFINED and as such not guaranteed to be present (most SoC available | |
49 | in 2014 seem to ignore the setting of this flag and use the hardware | |
50 | default value). | |
b3f7ed03 RH |
51 | |
52 | - reg : Specifies base physical address(s) and size of the GIC registers. The | |
53 | first region is the GIC distributor register base and size. The 2nd region is | |
54 | the GIC cpu interface register base and size. | |
55 | ||
56 | Optional | |
0a68214b | 57 | - interrupts : Interrupt source of the parent interrupt controller on |
f21ccfa0 | 58 | secondary GICs, or VGIC maintenance interrupt on primary GIC (see |
0a68214b | 59 | below). |
b3f7ed03 | 60 | |
db0d4db2 MZ |
61 | - cpu-offset : per-cpu offset within the distributor and cpu interface |
62 | regions, used when the GIC doesn't have banked registers. The offset is | |
63 | cpu-offset * cpu-nr. | |
64 | ||
afbbd233 GU |
65 | - clocks : List of phandle and clock-specific pairs, one for each entry |
66 | in clock-names. | |
67 | - clock-names : List of names for the GIC clock input(s). Valid clock names | |
68 | depend on the GIC variant: | |
69 | "ic_clk" (for "arm,arm11mp-gic") | |
70 | "PERIPHCLKEN" (for "arm,cortex-a15-gic") | |
71 | "PERIPHCLK", "PERIPHCLKEN" (for "arm,cortex-a9-gic") | |
39f8f23d | 72 | "clk" (for "arm,gic-400" and "nvidia,tegra210") |
afbbd233 GU |
73 | "gclk" (for "arm,pl390") |
74 | ||
75 | - power-domains : A phandle and PM domain specifier as defined by bindings of | |
76 | the power controller specified by phandle, used when the GIC | |
77 | is part of a Power or Clock Domain. | |
78 | ||
79 | ||
b3f7ed03 RH |
80 | Example: |
81 | ||
82 | intc: interrupt-controller@fff11000 { | |
83 | compatible = "arm,cortex-a9-gic"; | |
84 | #interrupt-cells = <3>; | |
85 | #address-cells = <1>; | |
86 | interrupt-controller; | |
87 | reg = <0xfff11000 0x1000>, | |
88 | <0xfff10100 0x100>; | |
89 | }; | |
90 | ||
0a68214b MZ |
91 | |
92 | * GIC virtualization extensions (VGIC) | |
93 | ||
94 | For ARM cores that support the virtualization extensions, additional | |
95 | properties must be described (they only exist if the GIC is the | |
96 | primary interrupt controller). | |
97 | ||
98 | Required properties: | |
99 | ||
100 | - reg : Additional regions specifying the base physical address and | |
101 | size of the VGIC registers. The first additional region is the GIC | |
102 | virtual interface control register base and size. The 2nd additional | |
103 | region is the GIC virtual cpu interface register base and size. | |
104 | ||
f21ccfa0 | 105 | - interrupts : VGIC maintenance interrupt. |
0a68214b MZ |
106 | |
107 | Example: | |
108 | ||
109 | interrupt-controller@2c001000 { | |
110 | compatible = "arm,cortex-a15-gic"; | |
111 | #interrupt-cells = <3>; | |
112 | interrupt-controller; | |
113 | reg = <0x2c001000 0x1000>, | |
1defa60e | 114 | <0x2c002000 0x2000>, |
0a68214b MZ |
115 | <0x2c004000 0x2000>, |
116 | <0x2c006000 0x2000>; | |
117 | interrupts = <1 9 0xf04>; | |
118 | }; | |
e684e258 SS |
119 | |
120 | ||
121 | * GICv2m extension for MSI/MSI-x support (Optional) | |
122 | ||
123 | Certain revisions of GIC-400 supports MSI/MSI-x via V2M register frame(s). | |
124 | This is enabled by specifying v2m sub-node(s). | |
125 | ||
126 | Required properties: | |
127 | ||
128 | - compatible : The value here should contain "arm,gic-v2m-frame". | |
129 | ||
130 | - msi-controller : Identifies the node as an MSI controller. | |
131 | ||
132 | - reg : GICv2m MSI interface register base and size | |
133 | ||
134 | Optional properties: | |
135 | ||
136 | - arm,msi-base-spi : When the MSI_TYPER register contains an incorrect | |
137 | value, this property should contain the SPI base of | |
138 | the MSI frame, overriding the HW value. | |
139 | ||
140 | - arm,msi-num-spis : When the MSI_TYPER register contains an incorrect | |
141 | value, this property should contain the number of | |
142 | SPIs assigned to the frame, overriding the HW value. | |
143 | ||
144 | Example: | |
145 | ||
146 | interrupt-controller@e1101000 { | |
147 | compatible = "arm,gic-400"; | |
148 | #interrupt-cells = <3>; | |
149 | #address-cells = <2>; | |
150 | #size-cells = <2>; | |
151 | interrupt-controller; | |
152 | interrupts = <1 8 0xf04>; | |
153 | ranges = <0 0 0 0xe1100000 0 0x100000>; | |
154 | reg = <0x0 0xe1110000 0 0x01000>, | |
155 | <0x0 0xe112f000 0 0x02000>, | |
156 | <0x0 0xe1140000 0 0x10000>, | |
157 | <0x0 0xe1160000 0 0x10000>; | |
4c9847b7 | 158 | v2m0: v2m@8000 { |
e684e258 SS |
159 | compatible = "arm,gic-v2m-frame"; |
160 | msi-controller; | |
161 | reg = <0x0 0x80000 0 0x1000>; | |
162 | }; | |
163 | ||
164 | .... | |
165 | ||
4c9847b7 | 166 | v2mN: v2m@9000 { |
e684e258 SS |
167 | compatible = "arm,gic-v2m-frame"; |
168 | msi-controller; | |
169 | reg = <0x0 0x90000 0 0x1000>; | |
170 | }; | |
171 | }; |