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18b84857 | 1 | /** @file\r |
ca162103 | 2 | \r |
b1f700a8 HT |
3 | Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r |
4 | This program and the accompanying materials \r | |
ca162103 | 5 | are licensed and made available under the terms and conditions of the BSD License \r |
6 | which accompanies this distribution. The full text of the license may be found at \r | |
7 | http://opensource.org/licenses/bsd-license.php \r | |
8 | \r | |
9 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r | |
10 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r | |
11 | \r | |
12 | Module Name:\r | |
13 | VirtualMemory.h\r | |
14 | \r | |
15 | Abstract:\r | |
16 | \r | |
17 | Revision History:\r | |
18 | \r | |
18b84857 | 19 | **/\r |
ca162103 | 20 | \r |
21 | #ifndef _VIRTUAL_MEMORY_H_\r | |
22 | #define _VIRTUAL_MEMORY_H_\r | |
23 | \r | |
24 | #pragma pack(1)\r | |
25 | \r | |
26 | //\r | |
27 | // Page Directory Entry 4K\r | |
28 | //\r | |
29 | typedef union {\r | |
30 | struct {\r | |
31 | UINT32 Present:1; // 0 = Not present in memory, 1 = Present in memory\r | |
32 | UINT32 ReadWrite:1; // 0 = Read-Only, 1= Read/Write\r | |
33 | UINT32 UserSupervisor:1; // 0 = Supervisor, 1=User\r | |
34 | UINT32 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching\r | |
35 | UINT32 CacheDisabled:1; // 0 = Cached, 1=Non-Cached\r | |
36 | UINT32 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)\r | |
37 | UINT32 MustBeZero:3; // Must Be Zero\r | |
38 | UINT32 Available:3; // Available for use by system software\r | |
39 | UINT32 PageTableBaseAddress:20; // Page Table Base Address\r | |
40 | } Bits;\r | |
41 | UINT32 Uint32;\r | |
42 | } IA32_PAGE_DIRECTORY_ENTRY_4K;\r | |
43 | \r | |
44 | //\r | |
45 | // Page Table Entry 4K\r | |
46 | //\r | |
47 | typedef union {\r | |
48 | struct {\r | |
49 | UINT32 Present:1; // 0 = Not present in memory, 1 = Present in memory \r | |
50 | UINT32 ReadWrite:1; // 0 = Read-Only, 1= Read/Write\r | |
51 | UINT32 UserSupervisor:1; // 0 = Supervisor, 1=User\r | |
52 | UINT32 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching\r | |
53 | UINT32 CacheDisabled:1; // 0 = Cached, 1=Non-Cached\r | |
54 | UINT32 Accessed:1; // 0 = Not accessed (cleared by software), 1 = Accessed (set by CPU)\r | |
55 | UINT32 Dirty:1; // 0 = Not written to (cleared by software), 1 = Written to (set by CPU)\r | |
56 | UINT32 PAT:1; // 0 = Disable PAT, 1 = Enable PAT\r | |
57 | UINT32 Global:1; // Ignored\r | |
58 | UINT32 Available:3; // Available for use by system software\r | |
59 | UINT32 PageTableBaseAddress:20; // Page Table Base Address\r | |
60 | } Bits;\r | |
61 | UINT32 Uint32;\r | |
62 | } IA32_PAGE_TABLE_ENTRY_4K;\r | |
63 | \r | |
64 | //\r | |
65 | // Page Table Entry 4M\r | |
66 | //\r | |
67 | typedef union {\r | |
68 | struct {\r | |
69 | UINT32 Present:1; // 0 = Not present in memory, 1 = Present in memory\r | |
70 | UINT32 ReadWrite:1; // 0 = Read-Only, 1= Read/Write\r | |
71 | UINT32 UserSupervisor:1; // 0 = Supervisor, 1=User\r | |
72 | UINT32 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching\r | |
73 | UINT32 CacheDisabled:1; // 0 = Cached, 1=Non-Cached\r | |
74 | UINT32 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)\r | |
75 | UINT32 Dirty:1; // 0 = Not Dirty, 1 = written by processor on access to page\r | |
76 | UINT32 MustBe1:1; // Must be 1 \r | |
77 | UINT32 Global:1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write\r | |
78 | UINT32 Available:3; // Available for use by system software\r | |
79 | UINT32 PAT:1; //\r | |
80 | UINT32 MustBeZero:9; // Must be zero;\r | |
81 | UINT32 PageTableBaseAddress:10; // Page Table Base Address\r | |
82 | } Bits;\r | |
83 | UINT32 Uint32;\r | |
84 | } IA32_PAGE_TABLE_ENTRY_4M;\r | |
85 | \r | |
86 | #pragma pack()\r | |
87 | \r | |
88 | #endif \r |