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18b84857 | 1 | /** @file\r |
ca162103 | 2 | \r |
3 | Copyright (c) 2006, Intel Corporation. All rights reserved.\r | |
4 | This software and associated documentation (if any) is furnished\r | |
5 | under a license and may only be used or copied in accordance\r | |
6 | with the terms of the license. Except as permitted by such\r | |
7 | license, no part of this software or documentation may be\r | |
8 | reproduced, stored in a retrieval system, or transmitted in any\r | |
9 | form or by any means without the express written consent of\r | |
10 | Intel Corporation.\r | |
11 | \r | |
12 | Module Name:\r | |
13 | \r | |
14 | CpuIA32.h\r | |
15 | \r | |
16 | Abstract:\r | |
17 | \r | |
18 | Basic Definition for IA32 Architecture.\r | |
19 | \r | |
18b84857 | 20 | **/\r |
ca162103 | 21 | \r |
22 | #ifndef _CPU_IA32_H_\r | |
23 | #define _CPU_IA32_H_\r | |
24 | \r | |
25 | typedef struct {\r | |
26 | UINT32 RegEax;\r | |
27 | UINT32 RegEbx;\r | |
28 | UINT32 RegEcx;\r | |
29 | UINT32 RegEdx;\r | |
30 | } EFI_CPUID_REGISTER;\r | |
31 | \r | |
32 | #pragma pack(1)\r | |
33 | //\r | |
34 | // Definition for IA32 microcode format\r | |
35 | //\r | |
36 | typedef struct {\r | |
37 | UINT32 HeaderVersion;\r | |
38 | UINT32 UpdateRevision;\r | |
39 | UINT32 Date;\r | |
40 | UINT32 ProcessorId;\r | |
41 | UINT32 Checksum;\r | |
42 | UINT32 LoaderRevision;\r | |
43 | UINT32 ProcessorFlags;\r | |
44 | UINT32 DataSize;\r | |
45 | UINT32 TotalSize;\r | |
46 | UINT8 Reserved[12];\r | |
47 | } EFI_CPU_MICROCODE_HEADER;\r | |
48 | \r | |
49 | typedef struct {\r | |
50 | UINT32 ExtendedSignatureCount;\r | |
51 | UINT32 ExtendedTableChecksum;\r | |
52 | UINT8 Reserved[12];\r | |
53 | } EFI_CPU_MICROCODE_EXTENDED_TABLE_HEADER;\r | |
54 | \r | |
55 | typedef struct {\r | |
56 | UINT32 ProcessorSignature;\r | |
57 | UINT32 ProcessorFlag;\r | |
58 | UINT32 ProcessorChecksum;\r | |
59 | } EFI_CPU_MICROCODE_EXTENDED_TABLE;\r | |
60 | \r | |
61 | //\r | |
62 | // The MS compiler doesn't handle QWORDs very well. So break\r | |
63 | // them into DWORDs to circumvent the problem.\r | |
64 | //\r | |
65 | typedef union _MSR_REGISTER {\r | |
66 | UINT64 Qword;\r | |
67 | \r | |
68 | struct _DWORDS {\r | |
69 | UINT32 Low;\r | |
70 | UINT32 High;\r | |
71 | } Dwords;\r | |
72 | \r | |
73 | struct _BYTES {\r | |
74 | UINT8 FirstByte;\r | |
75 | UINT8 SecondByte;\r | |
76 | UINT8 ThirdByte;\r | |
77 | UINT8 FouthByte;\r | |
78 | UINT8 FifthByte;\r | |
79 | UINT8 SixthByte;\r | |
80 | UINT8 SeventhByte;\r | |
81 | UINT8 EighthByte;\r | |
82 | } Bytes;\r | |
83 | \r | |
84 | } MSR_REGISTER;\r | |
85 | \r | |
86 | #pragma pack()\r | |
87 | \r | |
88 | //\r | |
89 | // Definition for CPUID Index\r | |
90 | //\r | |
91 | #define EFI_CPUID_SIGNATURE 0x0\r | |
92 | #define EFI_CPUID_VERSION_INFO 0x1\r | |
93 | #define EFI_CPUID_CACHE_INFO 0x2\r | |
94 | #define EFI_CPUID_SERIAL_NUMBER 0x3\r | |
95 | #define EFI_CPUID_EXTENDED_FUNCTION 0x80000000\r | |
96 | #define EFI_CPUID_EXTENDED_CPU_SIG 0x80000001\r | |
97 | #define EFI_CPUID_BRAND_STRING1 0x80000002\r | |
98 | #define EFI_CPUID_BRAND_STRING2 0x80000003\r | |
99 | #define EFI_CPUID_BRAND_STRING3 0x80000004\r | |
100 | #define EFI_CPUID_ADDRESS_SIZE 0x80000008\r | |
101 | \r | |
102 | //\r | |
103 | // Definition for MSR address\r | |
104 | //\r | |
105 | #define EFI_MSR_IA32_PLATFORM_ID 0x17\r | |
106 | #define EFI_MSR_IA32_APIC_BASE 0x1B\r | |
107 | #define EFI_MSR_EBC_HARD_POWERON 0x2A\r | |
108 | #define EFI_MSR_EBC_SOFT_POWERON 0x2B\r | |
109 | #define EFI_MSR_EBC_FREQUENCY_ID 0x2C\r | |
110 | #define MSR_IA32_FEATURE_CONTROL 0x3A\r | |
111 | #define EFI_MSR_IA32_BIOS_UPDT_TRIG 0x79\r | |
112 | #define EFI_MSR_IA32_BIOS_SIGN_ID 0x8B\r | |
113 | #define EFI_MSR_PSB_CLOCK_STATUS 0xCD\r | |
114 | #define MSR_EXT_CONFIG 0xEE\r | |
115 | #define EFI_IA32_MCG_CAP 0x179\r | |
116 | #define EFI_IA32_MCG_CTL 0x17B\r | |
117 | \r | |
118 | #define EFI_MSR_IA32_PERF_STS 0x198\r | |
119 | #define EFI_MSR_IA32_PERF_CTL 0x199\r | |
120 | #define EFI_MSR_IA32_CLOCK_MODULATION 0x19A\r | |
121 | #define MSR_IA32_THERMAL_INTERRUPT 0x19B\r | |
122 | #define EFI_MSR_IA32_THERM_STATUS 0x19C\r | |
123 | #define EFI_MSR_GV_THERM 0x19D\r | |
124 | #define MSR_IA32_MISC_ENABLE 0x1A0\r | |
125 | #define MSR_PIC_SENS_CFG 0x1AA\r | |
126 | \r | |
127 | #define EFI_IA32_MC0_CTL 0x400\r | |
128 | #define EFI_IA32_MC0_STATUS 0x401\r | |
129 | #define MSR_PECI_CONTROL 0x5A0\r | |
130 | \r | |
131 | //\r | |
132 | // Definition for MTRR address and related values\r | |
133 | //\r | |
134 | #define EFI_IA32_MTRR_FIX64K_00000 0x250\r | |
135 | #define EFI_IA32_MTRR_FIX16K_80000 0x258\r | |
136 | #define EFI_IA32_MTRR_FIX16K_A0000 0x259\r | |
137 | #define EFI_IA32_MTRR_FIX4K_C0000 0x268\r | |
138 | #define EFI_IA32_MTRR_FIX4K_C8000 0x269\r | |
139 | #define EFI_IA32_MTRR_FIX4K_D0000 0x26A\r | |
140 | #define EFI_IA32_MTRR_FIX4K_D8000 0x26B\r | |
141 | #define EFI_IA32_MTRR_FIX4K_E0000 0x26C\r | |
142 | #define EFI_IA32_MTRR_FIX4K_E8000 0x26D\r | |
143 | #define EFI_IA32_MTRR_FIX4K_F0000 0x26E\r | |
144 | #define EFI_IA32_MTRR_FIX4K_F8000 0x26F\r | |
145 | #define EFI_CACHE_VARIABLE_MTRR_BASE 0x200\r | |
146 | #define EFI_CACHE_VARIABLE_MTRR_END 0x20F\r | |
147 | #define EFI_CACHE_IA32_MTRR_DEF_TYPE 0x2FF\r | |
148 | \r | |
149 | #define EFI_CACHE_VALID_ADDRESS 0xFFFFFF000\r | |
150 | #define EFI_MSR_VALID_MASK 0xFFFFFFFFF\r | |
151 | #define EFI_CACHE_MTRR_VALID 0x800\r | |
152 | #define EFI_CACHE_FIXED_MTRR_VALID 0x400\r | |
153 | \r | |
154 | #define EFI_CACHE_UNCACHEABLE 0\r | |
155 | #define EFI_CACHE_WRITECOMBINING 1\r | |
156 | #define EFI_CACHE_WRITETHROUGH 4\r | |
157 | #define EFI_CACHE_WRITEPROTECTED 5\r | |
158 | #define EFI_CACHE_WRITEBACK 6\r | |
159 | \r | |
160 | //\r | |
161 | // Definition for Local APIC registers and related values\r | |
162 | //\r | |
163 | #define LOCAL_APIC_LVT_TIMER 0x320\r | |
164 | #define LOCAL_APIC_TIMER_INIT_COUNT 0x380\r | |
165 | #define LOCAL_APIC_TIMER_COUNT 0x390\r | |
166 | #define LOCAL_APIC_TIMER_DIVIDE 0x3E0\r | |
167 | \r | |
168 | \r | |
169 | #define DELIVERY_MODE_FIXED 0x0\r | |
170 | #define DELIVERY_MODE_LOWEST_PRIORITY 0x1\r | |
171 | #define DELIVERY_MODE_SMI 0x2\r | |
172 | #define DELIVERY_MODE_REMOTE_READ 0x3\r | |
173 | #define DELIVERY_MODE_NMI 0x4\r | |
174 | #define DELIVERY_MODE_INIT 0x5\r | |
175 | #define DELIVERY_MODE_SIPI 0x6\r | |
176 | \r | |
177 | #define TRIGGER_MODE_EDGE 0x0\r | |
178 | #define TRIGGER_MODE_LEVEL 0x1\r | |
179 | \r | |
180 | //\r | |
181 | // CPU System Memory Map Definition\r | |
182 | //\r | |
183 | #define CPU_MSI_MEMORY_BASE 0xFEE00000\r | |
184 | #define CPU_MSI_MEMORY_SIZE 0x100000\r | |
185 | \r | |
186 | \r | |
187 | #endif\r |