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10590588 | 1 | /*++\r |
2 | \r | |
3 | Copyright (c) 2005 - 2006, Intel Corporation \r | |
4 | All rights reserved. This program and the accompanying materials \r | |
5 | are licensed and made available under the terms and conditions of the BSD License \r | |
6 | which accompanies this distribution. The full text of the license may be found at \r | |
7 | http://opensource.org/licenses/bsd-license.php \r | |
8 | \r | |
9 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r | |
10 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r | |
11 | \r | |
12 | Module Name:\r | |
13 | \r | |
14 | PciCommand.h\r | |
15 | \r | |
16 | Abstract:\r | |
17 | \r | |
18 | PCI Bus Driver\r | |
19 | \r | |
20 | Revision History\r | |
21 | \r | |
22 | --*/\r | |
23 | \r | |
24 | #ifndef _EFI_PCI_COMMAND_H\r | |
25 | #define _EFI_PCI_COMMAND_H\r | |
26 | \r | |
27 | #include "PciBus.h"\r | |
28 | \r | |
29 | //\r | |
30 | // The PCI Command register bits owned by PCI Bus driver.\r | |
31 | //\r | |
32 | // They should be cleared at the beginning. The other registers\r | |
33 | // are owned by chipset, we should not touch them.\r | |
34 | //\r | |
35 | #define EFI_PCI_COMMAND_BITS_OWNED ( \\r | |
36 | EFI_PCI_COMMAND_IO_SPACE | \\r | |
37 | EFI_PCI_COMMAND_MEMORY_SPACE | \\r | |
38 | EFI_PCI_COMMAND_BUS_MASTER | \\r | |
39 | EFI_PCI_COMMAND_MEMORY_WRITE_AND_INVALIDATE | \\r | |
40 | EFI_PCI_COMMAND_VGA_PALETTE_SNOOP | \\r | |
41 | EFI_PCI_COMMAND_FAST_BACK_TO_BACK \\r | |
42 | )\r | |
43 | \r | |
44 | //\r | |
45 | // The PCI Bridge Control register bits owned by PCI Bus driver.\r | |
46 | // \r | |
47 | // They should be cleared at the beginning. The other registers\r | |
48 | // are owned by chipset, we should not touch them.\r | |
49 | //\r | |
50 | #define EFI_PCI_BRIDGE_CONTROL_BITS_OWNED ( \\r | |
51 | EFI_PCI_BRIDGE_CONTROL_ISA | \\r | |
52 | EFI_PCI_BRIDGE_CONTROL_VGA | \\r | |
53 | EFI_PCI_BRIDGE_CONTROL_VGA_16 | \\r | |
54 | EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK \\r | |
55 | )\r | |
56 | \r | |
57 | //\r | |
58 | // The PCCard Bridge Control register bits owned by PCI Bus driver.\r | |
59 | // \r | |
60 | // They should be cleared at the beginning. The other registers\r | |
61 | // are owned by chipset, we should not touch them.\r | |
62 | //\r | |
63 | #define EFI_PCCARD_BRIDGE_CONTROL_BITS_OWNED ( \\r | |
64 | EFI_PCI_BRIDGE_CONTROL_ISA | \\r | |
65 | EFI_PCI_BRIDGE_CONTROL_VGA | \\r | |
66 | EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK \\r | |
67 | )\r | |
68 | \r | |
69 | EFI_STATUS \r | |
70 | PciReadCommandRegister (\r | |
71 | IN PCI_IO_DEVICE *PciIoDevice,\r | |
72 | OUT UINT16 *Command\r | |
73 | );\r | |
74 | \r | |
75 | \r | |
76 | EFI_STATUS \r | |
77 | PciSetCommandRegister (\r | |
78 | IN PCI_IO_DEVICE *PciIoDevice,\r | |
79 | IN UINT16 Command\r | |
80 | );\r | |
81 | \r | |
82 | EFI_STATUS \r | |
83 | PciEnableCommandRegister (\r | |
84 | IN PCI_IO_DEVICE *PciIoDevice,\r | |
85 | IN UINT16 Command\r | |
86 | );\r | |
87 | \r | |
88 | EFI_STATUS \r | |
89 | PciDisableCommandRegister (\r | |
90 | IN PCI_IO_DEVICE *PciIoDevice,\r | |
91 | IN UINT16 Command\r | |
92 | );\r | |
93 | \r | |
94 | EFI_STATUS \r | |
95 | PciDisableBridgeControlRegister (\r | |
96 | IN PCI_IO_DEVICE *PciIoDevice,\r | |
97 | IN UINT16 Command\r | |
98 | );\r | |
99 | \r | |
100 | \r | |
101 | EFI_STATUS \r | |
102 | PciEnableBridgeControlRegister (\r | |
103 | IN PCI_IO_DEVICE *PciIoDevice,\r | |
104 | IN UINT16 Command\r | |
105 | );\r | |
106 | \r | |
107 | EFI_STATUS \r | |
108 | PciReadBridgeControlRegister (\r | |
109 | IN PCI_IO_DEVICE *PciIoDevice,\r | |
110 | OUT UINT16 *Command\r | |
111 | );\r | |
112 | \r | |
113 | BOOLEAN\r | |
114 | PciCapabilitySupport (\r | |
115 | IN PCI_IO_DEVICE *PciIoDevice\r | |
116 | )\r | |
117 | /*++\r | |
118 | \r | |
119 | Routine Description:\r | |
120 | \r | |
121 | TODO: Add function description\r | |
122 | \r | |
123 | Arguments:\r | |
124 | \r | |
125 | PciIoDevice - TODO: add argument description\r | |
126 | \r | |
127 | Returns:\r | |
128 | \r | |
129 | TODO: add return values\r | |
130 | \r | |
131 | --*/\r | |
132 | ;\r | |
133 | \r | |
134 | EFI_STATUS\r | |
135 | LocateCapabilityRegBlock (\r | |
136 | IN PCI_IO_DEVICE *PciIoDevice,\r | |
137 | IN UINT8 CapId,\r | |
138 | IN OUT UINT8 *Offset,\r | |
139 | OUT UINT8 *NextRegBlock OPTIONAL\r | |
140 | )\r | |
141 | /*++\r | |
142 | \r | |
143 | Routine Description:\r | |
144 | \r | |
145 | Locate Capability register.\r | |
146 | \r | |
147 | Arguments:\r | |
148 | \r | |
149 | PciIoDevice - A pointer to the PCI_IO_DEVICE.\r | |
150 | CapId - The capability ID.\r | |
151 | Offset - A pointer to the offset. \r | |
152 | As input: the default offset; \r | |
153 | As output: the offset of the found block.\r | |
154 | NextRegBlock - An optional pointer to return the value of next block.\r | |
155 | \r | |
156 | Returns:\r | |
157 | \r | |
158 | EFI_UNSUPPORTED - The Pci Io device is not supported.\r | |
159 | EFI_NOT_FOUND - The Pci Io device cannot be found.\r | |
160 | EFI_SUCCESS - The Pci Io device is successfully located.\r | |
161 | \r | |
162 | --*/\r | |
163 | ;\r | |
164 | \r | |
165 | \r | |
166 | #endif\r | |
167 | \r |