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26147c77 SM |
1 | /** @file\r |
2 | \r | |
de200b7e | 3 | Copyright (c) 2017 - 2022, Arm Limited. All rights reserved.<BR>\r |
26147c77 | 4 | \r |
9cd9bdc6 | 5 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
26147c77 SM |
6 | \r |
7 | @par Glossary:\r | |
8 | - Cm or CM - Configuration Manager\r | |
9 | - Obj or OBJ - Object\r | |
10 | - Std or STD - Standard\r | |
11 | **/\r | |
12 | \r | |
13 | #ifndef ARM_NAMESPACE_OBJECTS_H_\r | |
14 | #define ARM_NAMESPACE_OBJECTS_H_\r | |
15 | \r | |
09c90532 | 16 | #include <AmlCpcInfo.h>\r |
26147c77 SM |
17 | #include <StandardNameSpaceObjects.h>\r |
18 | \r | |
19 | #pragma pack(1)\r | |
20 | \r | |
21 | /** The EARM_OBJECT_ID enum describes the Object IDs\r | |
22 | in the ARM Namespace\r | |
23 | */\r | |
24 | typedef enum ArmObjectID {\r | |
dab7bac9 PG |
25 | EArmObjReserved, ///< 0 - Reserved\r |
26 | EArmObjBootArchInfo, ///< 1 - Boot Architecture Info\r | |
27 | EArmObjCpuInfo, ///< 2 - CPU Info\r | |
28 | EArmObjPowerManagementProfileInfo, ///< 3 - Power Management Profile Info\r | |
29 | EArmObjGicCInfo, ///< 4 - GIC CPU Interface Info\r | |
30 | EArmObjGicDInfo, ///< 5 - GIC Distributor Info\r | |
31 | EArmObjGicMsiFrameInfo, ///< 6 - GIC MSI Frame Info\r | |
32 | EArmObjGicRedistributorInfo, ///< 7 - GIC Redistributor Info\r | |
33 | EArmObjGicItsInfo, ///< 8 - GIC ITS Info\r | |
34 | EArmObjSerialConsolePortInfo, ///< 9 - Serial Console Port Info\r | |
35 | EArmObjSerialDebugPortInfo, ///< 10 - Serial Debug Port Info\r | |
36 | EArmObjGenericTimerInfo, ///< 11 - Generic Timer Info\r | |
37 | EArmObjPlatformGTBlockInfo, ///< 12 - Platform GT Block Info\r | |
38 | EArmObjGTBlockTimerFrameInfo, ///< 13 - Generic Timer Block Frame Info\r | |
39 | EArmObjPlatformGenericWatchdogInfo, ///< 14 - Platform Generic Watchdog\r | |
40 | EArmObjPciConfigSpaceInfo, ///< 15 - PCI Configuration Space Info\r | |
41 | EArmObjHypervisorVendorIdentity, ///< 16 - Hypervisor Vendor Id\r | |
42 | EArmObjFixedFeatureFlags, ///< 17 - Fixed feature flags for FADT\r | |
43 | EArmObjItsGroup, ///< 18 - ITS Group\r | |
44 | EArmObjNamedComponent, ///< 19 - Named Component\r | |
45 | EArmObjRootComplex, ///< 20 - Root Complex\r | |
46 | EArmObjSmmuV1SmmuV2, ///< 21 - SMMUv1 or SMMUv2\r | |
47 | EArmObjSmmuV3, ///< 22 - SMMUv3\r | |
48 | EArmObjPmcg, ///< 23 - PMCG\r | |
49 | EArmObjGicItsIdentifierArray, ///< 24 - GIC ITS Identifier Array\r | |
50 | EArmObjIdMappingArray, ///< 25 - ID Mapping Array\r | |
51 | EArmObjSmmuInterruptArray, ///< 26 - SMMU Interrupt Array\r | |
52 | EArmObjProcHierarchyInfo, ///< 27 - Processor Hierarchy Info\r | |
53 | EArmObjCacheInfo, ///< 28 - Cache Info\r | |
54 | EArmObjReserved29, ///< 29 - Reserved\r | |
55 | EArmObjCmRef, ///< 30 - CM Object Reference\r | |
56 | EArmObjMemoryAffinityInfo, ///< 31 - Memory Affinity Info\r | |
57 | EArmObjDeviceHandleAcpi, ///< 32 - Device Handle Acpi\r | |
58 | EArmObjDeviceHandlePci, ///< 33 - Device Handle Pci\r | |
59 | EArmObjGenericInitiatorAffinityInfo, ///< 34 - Generic Initiator Affinity\r | |
60 | EArmObjSerialPortInfo, ///< 35 - Generic Serial Port Info\r | |
61 | EArmObjCmn600Info, ///< 36 - CMN-600 Info\r | |
62 | EArmObjLpiInfo, ///< 37 - Lpi Info\r | |
63 | EArmObjPciAddressMapInfo, ///< 38 - Pci Address Map Info\r | |
64 | EArmObjPciInterruptMapInfo, ///< 39 - Pci Interrupt Map Info\r | |
65 | EArmObjRmr, ///< 40 - Reserved Memory Range Node\r | |
66 | EArmObjMemoryRangeDescriptor, ///< 41 - Memory Range Descriptor\r | |
67 | EArmObjCpcInfo, ///< 42 - Continuous Performance Control Info\r | |
68 | EArmObjPccSubspaceType0Info, ///< 43 - Pcc Subspace Type 0 Info\r | |
69 | EArmObjPccSubspaceType1Info, ///< 44 - Pcc Subspace Type 2 Info\r | |
70 | EArmObjPccSubspaceType2Info, ///< 45 - Pcc Subspace Type 2 Info\r | |
71 | EArmObjPccSubspaceType3Info, ///< 46 - Pcc Subspace Type 3 Info\r | |
72 | EArmObjPccSubspaceType4Info, ///< 47 - Pcc Subspace Type 4 Info\r | |
73 | EArmObjPccSubspaceType5Info, ///< 48 - Pcc Subspace Type 5 Info\r | |
26147c77 SM |
74 | EArmObjMax\r |
75 | } EARM_OBJECT_ID;\r | |
76 | \r | |
77 | /** A structure that describes the\r | |
78 | ARM Boot Architecture flags.\r | |
c606f472 SM |
79 | \r |
80 | ID: EArmObjBootArchInfo\r | |
26147c77 SM |
81 | */\r |
82 | typedef struct CmArmBootArchInfo {\r | |
83 | /** This is the ARM_BOOT_ARCH flags field of the FADT Table\r | |
84 | described in the ACPI Table Specification.\r | |
85 | */\r | |
731c67e1 | 86 | UINT16 BootArchFlags;\r |
26147c77 SM |
87 | } CM_ARM_BOOT_ARCH_INFO;\r |
88 | \r | |
26147c77 SM |
89 | /** A structure that describes the\r |
90 | Power Management Profile Information for the Platform.\r | |
c606f472 SM |
91 | \r |
92 | ID: EArmObjPowerManagementProfileInfo\r | |
26147c77 SM |
93 | */\r |
94 | typedef struct CmArmPowerManagementProfileInfo {\r | |
95 | /** This is the Preferred_PM_Profile field of the FADT Table\r | |
96 | described in the ACPI Specification\r | |
97 | */\r | |
731c67e1 | 98 | UINT8 PowerManagementProfile;\r |
26147c77 SM |
99 | } CM_ARM_POWER_MANAGEMENT_PROFILE_INFO;\r |
100 | \r | |
101 | /** A structure that describes the\r | |
102 | GIC CPU Interface for the Platform.\r | |
c606f472 SM |
103 | \r |
104 | ID: EArmObjGicCInfo\r | |
26147c77 SM |
105 | */\r |
106 | typedef struct CmArmGicCInfo {\r | |
107 | /// The GIC CPU Interface number.\r | |
09c90532 | 108 | UINT32 CPUInterfaceNumber;\r |
26147c77 SM |
109 | \r |
110 | /** The ACPI Processor UID. This must match the\r | |
111 | _UID of the CPU Device object information described\r | |
112 | in the DSDT/SSDT for the CPU.\r | |
113 | */\r | |
09c90532 | 114 | UINT32 AcpiProcessorUid;\r |
26147c77 SM |
115 | \r |
116 | /** The flags field as described by the GICC structure\r | |
117 | in the ACPI Specification.\r | |
118 | */\r | |
09c90532 | 119 | UINT32 Flags;\r |
26147c77 SM |
120 | \r |
121 | /** The parking protocol version field as described by\r | |
122 | the GICC structure in the ACPI Specification.\r | |
123 | */\r | |
09c90532 | 124 | UINT32 ParkingProtocolVersion;\r |
26147c77 SM |
125 | \r |
126 | /** The Performance Interrupt field as described by\r | |
127 | the GICC structure in the ACPI Specification.\r | |
128 | */\r | |
09c90532 | 129 | UINT32 PerformanceInterruptGsiv;\r |
26147c77 SM |
130 | \r |
131 | /** The CPU Parked address field as described by\r | |
132 | the GICC structure in the ACPI Specification.\r | |
133 | */\r | |
09c90532 | 134 | UINT64 ParkedAddress;\r |
26147c77 SM |
135 | \r |
136 | /** The base address for the GIC CPU Interface\r | |
137 | as described by the GICC structure in the\r | |
138 | ACPI Specification.\r | |
139 | */\r | |
09c90532 | 140 | UINT64 PhysicalBaseAddress;\r |
26147c77 SM |
141 | \r |
142 | /** The base address for GICV interface\r | |
143 | as described by the GICC structure in the\r | |
144 | ACPI Specification.\r | |
145 | */\r | |
09c90532 | 146 | UINT64 GICV;\r |
26147c77 SM |
147 | \r |
148 | /** The base address for GICH interface\r | |
149 | as described by the GICC structure in the\r | |
150 | ACPI Specification.\r | |
151 | */\r | |
09c90532 | 152 | UINT64 GICH;\r |
26147c77 SM |
153 | \r |
154 | /** The GICV maintenance interrupt\r | |
155 | as described by the GICC structure in the\r | |
156 | ACPI Specification.\r | |
157 | */\r | |
09c90532 | 158 | UINT32 VGICMaintenanceInterrupt;\r |
26147c77 SM |
159 | \r |
160 | /** The base address for GICR interface\r | |
161 | as described by the GICC structure in the\r | |
162 | ACPI Specification.\r | |
163 | */\r | |
09c90532 | 164 | UINT64 GICRBaseAddress;\r |
26147c77 SM |
165 | \r |
166 | /** The MPIDR for the CPU\r | |
167 | as described by the GICC structure in the\r | |
168 | ACPI Specification.\r | |
169 | */\r | |
09c90532 | 170 | UINT64 MPIDR;\r |
26147c77 SM |
171 | \r |
172 | /** The Processor Power Efficiency class\r | |
173 | as described by the GICC structure in the\r | |
174 | ACPI Specification.\r | |
175 | */\r | |
09c90532 | 176 | UINT8 ProcessorPowerEfficiencyClass;\r |
5506701f KK |
177 | \r |
178 | /** Statistical Profiling Extension buffer overflow GSIV. Zero if\r | |
179 | unsupported by this processor. This field was introduced in\r | |
180 | ACPI 6.3 (MADT revision 5) and is therefore ignored when\r | |
181 | generating MADT revision 4 or lower.\r | |
182 | */\r | |
09c90532 | 183 | UINT16 SpeOverflowInterrupt;\r |
f413d9be SM |
184 | \r |
185 | /** The proximity domain to which the logical processor belongs.\r | |
186 | This field is used to populate the GICC affinity structure\r | |
187 | in the SRAT table.\r | |
188 | */\r | |
09c90532 | 189 | UINT32 ProximityDomain;\r |
f413d9be SM |
190 | \r |
191 | /** The clock domain to which the logical processor belongs.\r | |
192 | This field is used to populate the GICC affinity structure\r | |
193 | in the SRAT table.\r | |
194 | */\r | |
09c90532 | 195 | UINT32 ClockDomain;\r |
f413d9be SM |
196 | \r |
197 | /** The GICC Affinity flags field as described by the GICC Affinity structure\r | |
198 | in the SRAT table.\r | |
199 | */\r | |
09c90532 JB |
200 | UINT32 AffinityFlags;\r |
201 | \r | |
202 | /** Optional field: Reference Token for the Cpc info of this processor.\r | |
203 | i.e. a token referencing a CM_ARM_CPC_INFO object.\r | |
204 | */\r | |
205 | CM_OBJECT_TOKEN CpcToken;\r | |
26147c77 SM |
206 | } CM_ARM_GICC_INFO;\r |
207 | \r | |
208 | /** A structure that describes the\r | |
209 | GIC Distributor information for the Platform.\r | |
c606f472 SM |
210 | \r |
211 | ID: EArmObjGicDInfo\r | |
26147c77 SM |
212 | */\r |
213 | typedef struct CmArmGicDInfo {\r | |
26147c77 | 214 | /// The Physical Base address for the GIC Distributor.\r |
731c67e1 | 215 | UINT64 PhysicalBaseAddress;\r |
26147c77 SM |
216 | \r |
217 | /** The global system interrupt\r | |
218 | number where this GIC Distributor's\r | |
219 | interrupt inputs start.\r | |
220 | */\r | |
731c67e1 | 221 | UINT32 SystemVectorBase;\r |
26147c77 SM |
222 | \r |
223 | /** The GIC version as described\r | |
224 | by the GICD structure in the\r | |
225 | ACPI Specification.\r | |
226 | */\r | |
731c67e1 | 227 | UINT8 GicVersion;\r |
26147c77 SM |
228 | } CM_ARM_GICD_INFO;\r |
229 | \r | |
230 | /** A structure that describes the\r | |
231 | GIC MSI Frame information for the Platform.\r | |
c606f472 SM |
232 | \r |
233 | ID: EArmObjGicMsiFrameInfo\r | |
26147c77 SM |
234 | */\r |
235 | typedef struct CmArmGicMsiFrameInfo {\r | |
236 | /// The GIC MSI Frame ID\r | |
731c67e1 | 237 | UINT32 GicMsiFrameId;\r |
26147c77 SM |
238 | \r |
239 | /// The Physical base address for the MSI Frame\r | |
731c67e1 | 240 | UINT64 PhysicalBaseAddress;\r |
26147c77 SM |
241 | \r |
242 | /** The GIC MSI Frame flags\r | |
243 | as described by the GIC MSI frame\r | |
244 | structure in the ACPI Specification.\r | |
245 | */\r | |
731c67e1 | 246 | UINT32 Flags;\r |
26147c77 SM |
247 | \r |
248 | /// SPI Count used by this frame\r | |
731c67e1 | 249 | UINT16 SPICount;\r |
26147c77 SM |
250 | \r |
251 | /// SPI Base used by this frame\r | |
731c67e1 | 252 | UINT16 SPIBase;\r |
26147c77 SM |
253 | } CM_ARM_GIC_MSI_FRAME_INFO;\r |
254 | \r | |
255 | /** A structure that describes the\r | |
256 | GIC Redistributor information for the Platform.\r | |
c606f472 SM |
257 | \r |
258 | ID: EArmObjGicRedistributorInfo\r | |
26147c77 SM |
259 | */\r |
260 | typedef struct CmArmGicRedistInfo {\r | |
261 | /** The physical address of a page range\r | |
262 | containing all GIC Redistributors.\r | |
263 | */\r | |
731c67e1 | 264 | UINT64 DiscoveryRangeBaseAddress;\r |
26147c77 SM |
265 | \r |
266 | /// Length of the GIC Redistributor Discovery page range\r | |
731c67e1 | 267 | UINT32 DiscoveryRangeLength;\r |
26147c77 SM |
268 | } CM_ARM_GIC_REDIST_INFO;\r |
269 | \r | |
270 | /** A structure that describes the\r | |
271 | GIC Interrupt Translation Service information for the Platform.\r | |
c606f472 SM |
272 | \r |
273 | ID: EArmObjGicItsInfo\r | |
26147c77 SM |
274 | */\r |
275 | typedef struct CmArmGicItsInfo {\r | |
276 | /// The GIC ITS ID\r | |
731c67e1 | 277 | UINT32 GicItsId;\r |
26147c77 SM |
278 | \r |
279 | /// The physical address for the Interrupt Translation Service\r | |
731c67e1 | 280 | UINT64 PhysicalBaseAddress;\r |
f413d9be SM |
281 | \r |
282 | /** The proximity domain to which the logical processor belongs.\r | |
283 | This field is used to populate the GIC ITS affinity structure\r | |
284 | in the SRAT table.\r | |
285 | */\r | |
731c67e1 | 286 | UINT32 ProximityDomain;\r |
26147c77 SM |
287 | } CM_ARM_GIC_ITS_INFO;\r |
288 | \r | |
289 | /** A structure that describes the\r | |
290 | Serial Port information for the Platform.\r | |
c606f472 SM |
291 | \r |
292 | ID: EArmObjSerialConsolePortInfo or\r | |
bade7f42 PG |
293 | EArmObjSerialDebugPortInfo or\r |
294 | EArmObjSerialPortInfo\r | |
26147c77 SM |
295 | */\r |
296 | typedef struct CmArmSerialPortInfo {\r | |
297 | /// The physical base address for the serial port\r | |
731c67e1 | 298 | UINT64 BaseAddress;\r |
26147c77 SM |
299 | \r |
300 | /// The serial port interrupt\r | |
731c67e1 | 301 | UINT32 Interrupt;\r |
26147c77 SM |
302 | \r |
303 | /// The serial port baud rate\r | |
731c67e1 | 304 | UINT64 BaudRate;\r |
26147c77 SM |
305 | \r |
306 | /// The serial port clock\r | |
731c67e1 | 307 | UINT32 Clock;\r |
26147c77 SM |
308 | \r |
309 | /// Serial Port subtype\r | |
731c67e1 | 310 | UINT16 PortSubtype;\r |
bade7f42 PG |
311 | \r |
312 | /// The Base address length\r | |
731c67e1 | 313 | UINT64 BaseAddressLength;\r |
c8cf71ec JG |
314 | \r |
315 | /// The access size\r | |
731c67e1 | 316 | UINT8 AccessSize;\r |
26147c77 SM |
317 | } CM_ARM_SERIAL_PORT_INFO;\r |
318 | \r | |
319 | /** A structure that describes the\r | |
320 | Generic Timer information for the Platform.\r | |
c606f472 SM |
321 | \r |
322 | ID: EArmObjGenericTimerInfo\r | |
26147c77 SM |
323 | */\r |
324 | typedef struct CmArmGenericTimerInfo {\r | |
325 | /// The physical base address for the counter control frame\r | |
731c67e1 | 326 | UINT64 CounterControlBaseAddress;\r |
26147c77 SM |
327 | \r |
328 | /// The physical base address for the counter read frame\r | |
731c67e1 | 329 | UINT64 CounterReadBaseAddress;\r |
26147c77 SM |
330 | \r |
331 | /// The secure PL1 timer interrupt\r | |
731c67e1 | 332 | UINT32 SecurePL1TimerGSIV;\r |
26147c77 SM |
333 | \r |
334 | /// The secure PL1 timer flags\r | |
731c67e1 | 335 | UINT32 SecurePL1TimerFlags;\r |
26147c77 SM |
336 | \r |
337 | /// The non-secure PL1 timer interrupt\r | |
731c67e1 | 338 | UINT32 NonSecurePL1TimerGSIV;\r |
26147c77 SM |
339 | \r |
340 | /// The non-secure PL1 timer flags\r | |
731c67e1 | 341 | UINT32 NonSecurePL1TimerFlags;\r |
26147c77 SM |
342 | \r |
343 | /// The virtual timer interrupt\r | |
731c67e1 | 344 | UINT32 VirtualTimerGSIV;\r |
26147c77 SM |
345 | \r |
346 | /// The virtual timer flags\r | |
731c67e1 | 347 | UINT32 VirtualTimerFlags;\r |
26147c77 SM |
348 | \r |
349 | /// The non-secure PL2 timer interrupt\r | |
731c67e1 | 350 | UINT32 NonSecurePL2TimerGSIV;\r |
26147c77 SM |
351 | \r |
352 | /// The non-secure PL2 timer flags\r | |
731c67e1 | 353 | UINT32 NonSecurePL2TimerFlags;\r |
e8015f2f PG |
354 | \r |
355 | /// GSIV for the virtual EL2 timer\r | |
731c67e1 | 356 | UINT32 VirtualPL2TimerGSIV;\r |
e8015f2f PG |
357 | \r |
358 | /// Flags for the virtual EL2 timer\r | |
731c67e1 | 359 | UINT32 VirtualPL2TimerFlags;\r |
26147c77 SM |
360 | } CM_ARM_GENERIC_TIMER_INFO;\r |
361 | \r | |
a64cc435 PG |
362 | /** A structure that describes the\r |
363 | Platform Generic Block Timer information for the Platform.\r | |
364 | \r | |
365 | ID: EArmObjPlatformGTBlockInfo\r | |
366 | */\r | |
367 | typedef struct CmArmGTBlockInfo {\r | |
368 | /// The physical base address for the GT Block Timer structure\r | |
369 | UINT64 GTBlockPhysicalAddress;\r | |
370 | \r | |
371 | /// The number of timer frames implemented in the GT Block\r | |
372 | UINT32 GTBlockTimerFrameCount;\r | |
373 | \r | |
374 | /// Reference token for the GT Block timer frame list\r | |
375 | CM_OBJECT_TOKEN GTBlockTimerFrameToken;\r | |
376 | } CM_ARM_GTBLOCK_INFO;\r | |
377 | \r | |
26147c77 SM |
378 | /** A structure that describes the\r |
379 | Platform Generic Block Timer Frame information for the Platform.\r | |
c606f472 SM |
380 | \r |
381 | ID: EArmObjGTBlockTimerFrameInfo\r | |
26147c77 SM |
382 | */\r |
383 | typedef struct CmArmGTBlockTimerFrameInfo {\r | |
384 | /// The Generic Timer frame number\r | |
731c67e1 | 385 | UINT8 FrameNumber;\r |
26147c77 SM |
386 | \r |
387 | /// The physical base address for the CntBase block\r | |
731c67e1 | 388 | UINT64 PhysicalAddressCntBase;\r |
26147c77 SM |
389 | \r |
390 | /// The physical base address for the CntEL0Base block\r | |
731c67e1 | 391 | UINT64 PhysicalAddressCntEL0Base;\r |
26147c77 SM |
392 | \r |
393 | /// The physical timer interrupt\r | |
731c67e1 | 394 | UINT32 PhysicalTimerGSIV;\r |
26147c77 SM |
395 | \r |
396 | /** The physical timer flags as described by the GT Block\r | |
397 | Timer frame Structure in the ACPI Specification.\r | |
398 | */\r | |
731c67e1 | 399 | UINT32 PhysicalTimerFlags;\r |
26147c77 SM |
400 | \r |
401 | /// The virtual timer interrupt\r | |
731c67e1 | 402 | UINT32 VirtualTimerGSIV;\r |
26147c77 SM |
403 | \r |
404 | /** The virtual timer flags as described by the GT Block\r | |
405 | Timer frame Structure in the ACPI Specification.\r | |
406 | */\r | |
731c67e1 | 407 | UINT32 VirtualTimerFlags;\r |
26147c77 SM |
408 | \r |
409 | /** The common timer flags as described by the GT Block\r | |
410 | Timer frame Structure in the ACPI Specification.\r | |
411 | */\r | |
731c67e1 | 412 | UINT32 CommonFlags;\r |
26147c77 SM |
413 | } CM_ARM_GTBLOCK_TIMER_FRAME_INFO;\r |
414 | \r | |
26147c77 | 415 | /** A structure that describes the\r |
f09dbf20 | 416 | Arm Generic Watchdog information for the Platform.\r |
c606f472 SM |
417 | \r |
418 | ID: EArmObjPlatformGenericWatchdogInfo\r | |
26147c77 SM |
419 | */\r |
420 | typedef struct CmArmGenericWatchdogInfo {\r | |
f09dbf20 | 421 | /// The physical base address of the Arm Watchdog control frame\r |
731c67e1 | 422 | UINT64 ControlFrameAddress;\r |
26147c77 | 423 | \r |
f09dbf20 | 424 | /// The physical base address of the Arm Watchdog refresh frame\r |
731c67e1 | 425 | UINT64 RefreshFrameAddress;\r |
26147c77 SM |
426 | \r |
427 | /// The watchdog interrupt\r | |
731c67e1 | 428 | UINT32 TimerGSIV;\r |
26147c77 | 429 | \r |
f09dbf20 | 430 | /** The flags for the watchdog as described by the Arm watchdog\r |
26147c77 SM |
431 | structure in the ACPI specification.\r |
432 | */\r | |
731c67e1 | 433 | UINT32 Flags;\r |
26147c77 SM |
434 | } CM_ARM_GENERIC_WATCHDOG_INFO;\r |
435 | \r | |
436 | /** A structure that describes the\r | |
437 | PCI Configuration Space information for the Platform.\r | |
c606f472 SM |
438 | \r |
439 | ID: EArmObjPciConfigSpaceInfo\r | |
26147c77 SM |
440 | */\r |
441 | typedef struct CmArmPciConfigSpaceInfo {\r | |
442 | /// The physical base address for the PCI segment\r | |
ce306e48 | 443 | UINT64 BaseAddress;\r |
26147c77 SM |
444 | \r |
445 | /// The PCI segment group number\r | |
ce306e48 | 446 | UINT16 PciSegmentGroupNumber;\r |
26147c77 SM |
447 | \r |
448 | /// The start bus number\r | |
ce306e48 | 449 | UINT8 StartBusNumber;\r |
26147c77 SM |
450 | \r |
451 | /// The end bus number\r | |
ce306e48 PG |
452 | UINT8 EndBusNumber;\r |
453 | \r | |
454 | /// Optional field: Reference Token for address mapping.\r | |
455 | /// Token identifying a CM_ARM_OBJ_REF structure.\r | |
456 | CM_OBJECT_TOKEN AddressMapToken;\r | |
457 | \r | |
458 | /// Optional field: Reference Token for interrupt mapping.\r | |
459 | /// Token identifying a CM_ARM_OBJ_REF structure.\r | |
460 | CM_OBJECT_TOKEN InterruptMapToken;\r | |
26147c77 SM |
461 | } CM_ARM_PCI_CONFIG_SPACE_INFO;\r |
462 | \r | |
463 | /** A structure that describes the\r | |
464 | Hypervisor Vendor ID information for the Platform.\r | |
c606f472 SM |
465 | \r |
466 | ID: EArmObjHypervisorVendorIdentity\r | |
26147c77 SM |
467 | */\r |
468 | typedef struct CmArmHypervisorVendorId {\r | |
469 | /// The hypervisor Vendor ID\r | |
731c67e1 | 470 | UINT64 HypervisorVendorId;\r |
26147c77 SM |
471 | } CM_ARM_HYPERVISOR_VENDOR_ID;\r |
472 | \r | |
473 | /** A structure that describes the\r | |
474 | Fixed feature flags for the Platform.\r | |
c606f472 SM |
475 | \r |
476 | ID: EArmObjFixedFeatureFlags\r | |
26147c77 SM |
477 | */\r |
478 | typedef struct CmArmFixedFeatureFlags {\r | |
479 | /// The Fixed feature flags\r | |
731c67e1 | 480 | UINT32 Flags;\r |
26147c77 SM |
481 | } CM_ARM_FIXED_FEATURE_FLAGS;\r |
482 | \r | |
483 | /** A structure that describes the\r | |
484 | ITS Group node for the Platform.\r | |
c606f472 SM |
485 | \r |
486 | ID: EArmObjItsGroup\r | |
26147c77 SM |
487 | */\r |
488 | typedef struct CmArmItsGroupNode {\r | |
c606f472 | 489 | /// An unique token used to identify this object\r |
731c67e1 | 490 | CM_OBJECT_TOKEN Token;\r |
26147c77 | 491 | /// The number of ITS identifiers in the ITS node\r |
731c67e1 | 492 | UINT32 ItsIdCount;\r |
26147c77 | 493 | /// Reference token for the ITS identifier array\r |
731c67e1 | 494 | CM_OBJECT_TOKEN ItsIdToken;\r |
de200b7e SM |
495 | \r |
496 | /// Unique identifier for this node.\r | |
497 | UINT32 Identifier;\r | |
26147c77 SM |
498 | } CM_ARM_ITS_GROUP_NODE;\r |
499 | \r | |
26147c77 SM |
500 | /** A structure that describes the\r |
501 | Named component node for the Platform.\r | |
c606f472 SM |
502 | \r |
503 | ID: EArmObjNamedComponent\r | |
26147c77 SM |
504 | */\r |
505 | typedef struct CmArmNamedComponentNode {\r | |
c606f472 | 506 | /// An unique token used to identify this object\r |
731c67e1 | 507 | CM_OBJECT_TOKEN Token;\r |
26147c77 | 508 | /// Number of ID mappings\r |
731c67e1 | 509 | UINT32 IdMappingCount;\r |
26147c77 | 510 | /// Reference token for the ID mapping array\r |
731c67e1 | 511 | CM_OBJECT_TOKEN IdMappingToken;\r |
26147c77 SM |
512 | \r |
513 | /// Flags for the named component\r | |
731c67e1 | 514 | UINT32 Flags;\r |
26147c77 SM |
515 | \r |
516 | /// Memory access properties : Cache coherent attributes\r | |
731c67e1 | 517 | UINT32 CacheCoherent;\r |
26147c77 | 518 | /// Memory access properties : Allocation hints\r |
731c67e1 | 519 | UINT8 AllocationHints;\r |
26147c77 | 520 | /// Memory access properties : Memory access flags\r |
731c67e1 | 521 | UINT8 MemoryAccessFlags;\r |
26147c77 SM |
522 | \r |
523 | /// Memory access properties : Address size limit\r | |
731c67e1 MK |
524 | UINT8 AddressSizeLimit;\r |
525 | \r | |
26147c77 SM |
526 | /** ASCII Null terminated string with the full path to\r |
527 | the entry in the namespace for this object.\r | |
528 | */\r | |
731c67e1 | 529 | CHAR8 *ObjectName;\r |
de200b7e SM |
530 | \r |
531 | /// Unique identifier for this node.\r | |
532 | UINT32 Identifier;\r | |
26147c77 SM |
533 | } CM_ARM_NAMED_COMPONENT_NODE;\r |
534 | \r | |
535 | /** A structure that describes the\r | |
536 | Root complex node for the Platform.\r | |
c606f472 SM |
537 | \r |
538 | ID: EArmObjRootComplex\r | |
26147c77 SM |
539 | */\r |
540 | typedef struct CmArmRootComplexNode {\r | |
c606f472 | 541 | /// An unique token used to identify this object\r |
731c67e1 | 542 | CM_OBJECT_TOKEN Token;\r |
26147c77 | 543 | /// Number of ID mappings\r |
731c67e1 | 544 | UINT32 IdMappingCount;\r |
26147c77 | 545 | /// Reference token for the ID mapping array\r |
731c67e1 | 546 | CM_OBJECT_TOKEN IdMappingToken;\r |
26147c77 SM |
547 | \r |
548 | /// Memory access properties : Cache coherent attributes\r | |
731c67e1 | 549 | UINT32 CacheCoherent;\r |
26147c77 | 550 | /// Memory access properties : Allocation hints\r |
731c67e1 | 551 | UINT8 AllocationHints;\r |
26147c77 | 552 | /// Memory access properties : Memory access flags\r |
731c67e1 | 553 | UINT8 MemoryAccessFlags;\r |
26147c77 SM |
554 | \r |
555 | /// ATS attributes\r | |
731c67e1 | 556 | UINT32 AtsAttribute;\r |
26147c77 | 557 | /// PCI segment number\r |
731c67e1 | 558 | UINT32 PciSegmentNumber;\r |
26147c77 | 559 | /// Memory address size limit\r |
731c67e1 | 560 | UINT8 MemoryAddressSize;\r |
de200b7e SM |
561 | /// PASID capabilities\r |
562 | UINT16 PasidCapabilities;\r | |
563 | /// Flags\r | |
564 | UINT32 Flags;\r | |
565 | \r | |
566 | /// Unique identifier for this node.\r | |
567 | UINT32 Identifier;\r | |
26147c77 SM |
568 | } CM_ARM_ROOT_COMPLEX_NODE;\r |
569 | \r | |
570 | /** A structure that describes the\r | |
571 | SMMUv1 or SMMUv2 node for the Platform.\r | |
c606f472 SM |
572 | \r |
573 | ID: EArmObjSmmuV1SmmuV2\r | |
26147c77 SM |
574 | */\r |
575 | typedef struct CmArmSmmuV1SmmuV2Node {\r | |
c606f472 | 576 | /// An unique token used to identify this object\r |
731c67e1 | 577 | CM_OBJECT_TOKEN Token;\r |
26147c77 | 578 | /// Number of ID mappings\r |
731c67e1 | 579 | UINT32 IdMappingCount;\r |
26147c77 | 580 | /// Reference token for the ID mapping array\r |
731c67e1 | 581 | CM_OBJECT_TOKEN IdMappingToken;\r |
26147c77 SM |
582 | \r |
583 | /// SMMU Base Address\r | |
731c67e1 | 584 | UINT64 BaseAddress;\r |
26147c77 | 585 | /// Length of the memory range covered by the SMMU\r |
731c67e1 | 586 | UINT64 Span;\r |
26147c77 | 587 | /// SMMU Model\r |
731c67e1 | 588 | UINT32 Model;\r |
26147c77 | 589 | /// SMMU flags\r |
731c67e1 | 590 | UINT32 Flags;\r |
26147c77 SM |
591 | \r |
592 | /// Number of context interrupts\r | |
731c67e1 | 593 | UINT32 ContextInterruptCount;\r |
26147c77 | 594 | /// Reference token for the context interrupt array\r |
731c67e1 | 595 | CM_OBJECT_TOKEN ContextInterruptToken;\r |
26147c77 SM |
596 | \r |
597 | /// Number of PMU interrupts\r | |
731c67e1 | 598 | UINT32 PmuInterruptCount;\r |
26147c77 | 599 | /// Reference token for the PMU interrupt array\r |
731c67e1 | 600 | CM_OBJECT_TOKEN PmuInterruptToken;\r |
26147c77 SM |
601 | \r |
602 | /// GSIV of the SMMU_NSgIrpt interrupt\r | |
731c67e1 | 603 | UINT32 SMMU_NSgIrpt;\r |
26147c77 | 604 | /// SMMU_NSgIrpt interrupt flags\r |
731c67e1 | 605 | UINT32 SMMU_NSgIrptFlags;\r |
26147c77 | 606 | /// GSIV of the SMMU_NSgCfgIrpt interrupt\r |
731c67e1 | 607 | UINT32 SMMU_NSgCfgIrpt;\r |
26147c77 | 608 | /// SMMU_NSgCfgIrpt interrupt flags\r |
731c67e1 | 609 | UINT32 SMMU_NSgCfgIrptFlags;\r |
de200b7e SM |
610 | \r |
611 | /// Unique identifier for this node.\r | |
612 | UINT32 Identifier;\r | |
26147c77 SM |
613 | } CM_ARM_SMMUV1_SMMUV2_NODE;\r |
614 | \r | |
615 | /** A structure that describes the\r | |
616 | SMMUv3 node for the Platform.\r | |
c606f472 SM |
617 | \r |
618 | ID: EArmObjSmmuV3\r | |
26147c77 SM |
619 | */\r |
620 | typedef struct CmArmSmmuV3Node {\r | |
c606f472 | 621 | /// An unique token used to identify this object\r |
731c67e1 | 622 | CM_OBJECT_TOKEN Token;\r |
26147c77 | 623 | /// Number of ID mappings\r |
731c67e1 | 624 | UINT32 IdMappingCount;\r |
26147c77 | 625 | /// Reference token for the ID mapping array\r |
731c67e1 | 626 | CM_OBJECT_TOKEN IdMappingToken;\r |
26147c77 SM |
627 | \r |
628 | /// SMMU Base Address\r | |
731c67e1 | 629 | UINT64 BaseAddress;\r |
26147c77 | 630 | /// SMMU flags\r |
731c67e1 | 631 | UINT32 Flags;\r |
26147c77 | 632 | /// VATOS address\r |
731c67e1 | 633 | UINT64 VatosAddress;\r |
26147c77 | 634 | /// Model\r |
731c67e1 | 635 | UINT32 Model;\r |
26147c77 | 636 | /// GSIV of the Event interrupt if SPI based\r |
731c67e1 | 637 | UINT32 EventInterrupt;\r |
26147c77 | 638 | /// PRI Interrupt if SPI based\r |
731c67e1 | 639 | UINT32 PriInterrupt;\r |
26147c77 | 640 | /// GERR interrupt if GSIV based\r |
731c67e1 | 641 | UINT32 GerrInterrupt;\r |
26147c77 | 642 | /// Sync interrupt if GSIV based\r |
731c67e1 | 643 | UINT32 SyncInterrupt;\r |
26147c77 SM |
644 | \r |
645 | /// Proximity domain flag\r | |
731c67e1 | 646 | UINT32 ProximityDomain;\r |
26147c77 | 647 | /// Index into the array of ID mapping\r |
731c67e1 | 648 | UINT32 DeviceIdMappingIndex;\r |
de200b7e SM |
649 | \r |
650 | /// Unique identifier for this node.\r | |
651 | UINT32 Identifier;\r | |
26147c77 SM |
652 | } CM_ARM_SMMUV3_NODE;\r |
653 | \r | |
654 | /** A structure that describes the\r | |
655 | PMCG node for the Platform.\r | |
c606f472 SM |
656 | \r |
657 | ID: EArmObjPmcg\r | |
26147c77 SM |
658 | */\r |
659 | typedef struct CmArmPmcgNode {\r | |
c606f472 | 660 | /// An unique token used to identify this object\r |
731c67e1 | 661 | CM_OBJECT_TOKEN Token;\r |
26147c77 | 662 | /// Number of ID mappings\r |
731c67e1 | 663 | UINT32 IdMappingCount;\r |
26147c77 | 664 | /// Reference token for the ID mapping array\r |
731c67e1 | 665 | CM_OBJECT_TOKEN IdMappingToken;\r |
26147c77 SM |
666 | \r |
667 | /// Base Address for performance monitor counter group\r | |
731c67e1 | 668 | UINT64 BaseAddress;\r |
26147c77 | 669 | /// GSIV for the Overflow interrupt\r |
731c67e1 | 670 | UINT32 OverflowInterrupt;\r |
26147c77 | 671 | /// Page 1 Base address\r |
731c67e1 | 672 | UINT64 Page1BaseAddress;\r |
26147c77 SM |
673 | \r |
674 | /// Reference token for the IORT node associated with this node\r | |
731c67e1 | 675 | CM_OBJECT_TOKEN ReferenceToken;\r |
de200b7e SM |
676 | \r |
677 | /// Unique identifier for this node.\r | |
678 | UINT32 Identifier;\r | |
26147c77 SM |
679 | } CM_ARM_PMCG_NODE;\r |
680 | \r | |
cc00dbcb PG |
681 | /** A structure that describes the\r |
682 | GIC ITS Identifiers for an ITS Group node.\r | |
683 | \r | |
684 | ID: EArmObjGicItsIdentifierArray\r | |
685 | */\r | |
686 | typedef struct CmArmGicItsIdentifier {\r | |
687 | /// The ITS Identifier\r | |
731c67e1 | 688 | UINT32 ItsId;\r |
cc00dbcb PG |
689 | } CM_ARM_ITS_IDENTIFIER;\r |
690 | \r | |
26147c77 SM |
691 | /** A structure that describes the\r |
692 | ID Mappings for the Platform.\r | |
c606f472 SM |
693 | \r |
694 | ID: EArmObjIdMappingArray\r | |
26147c77 SM |
695 | */\r |
696 | typedef struct CmArmIdMapping {\r | |
697 | /// Input base\r | |
731c67e1 | 698 | UINT32 InputBase;\r |
26147c77 | 699 | /// Number of input IDs\r |
731c67e1 | 700 | UINT32 NumIds;\r |
26147c77 | 701 | /// Output Base\r |
731c67e1 | 702 | UINT32 OutputBase;\r |
26147c77 | 703 | /// Reference token for the output node\r |
731c67e1 | 704 | CM_OBJECT_TOKEN OutputReferenceToken;\r |
26147c77 | 705 | /// Flags\r |
731c67e1 | 706 | UINT32 Flags;\r |
26147c77 SM |
707 | } CM_ARM_ID_MAPPING;\r |
708 | \r | |
37568365 PG |
709 | /** A structure that describes the Arm\r |
710 | Generic Interrupts.\r | |
26147c77 | 711 | */\r |
37568365 | 712 | typedef struct CmArmGenericInterrupt {\r |
26147c77 SM |
713 | /// Interrupt number\r |
714 | UINT32 Interrupt;\r | |
715 | \r | |
716 | /// Flags\r | |
ce306e48 PG |
717 | /// BIT0: 0: Interrupt is Level triggered\r |
718 | /// 1: Interrupt is Edge triggered\r | |
719 | /// BIT1: 0: Interrupt is Active high\r | |
720 | /// 1: Interrupt is Active low\r | |
26147c77 | 721 | UINT32 Flags;\r |
37568365 PG |
722 | } CM_ARM_GENERIC_INTERRUPT;\r |
723 | \r | |
724 | /** A structure that describes the SMMU interrupts for the Platform.\r | |
725 | \r | |
726 | Interrupt Interrupt number.\r | |
727 | Flags Interrupt flags as defined for SMMU node.\r | |
728 | \r | |
729 | ID: EArmObjSmmuInterruptArray\r | |
730 | */\r | |
731 | typedef CM_ARM_GENERIC_INTERRUPT CM_ARM_SMMU_INTERRUPT;\r | |
732 | \r | |
733 | /** A structure that describes the AML Extended Interrupts.\r | |
734 | \r | |
735 | Interrupt Interrupt number.\r | |
736 | Flags Interrupt flags as defined by the Interrupt\r | |
737 | Vector Flags (Byte 3) of the Extended Interrupt\r | |
738 | resource descriptor.\r | |
739 | See EFI_ACPI_EXTENDED_INTERRUPT_FLAG_xxx in Acpi10.h\r | |
37568365 PG |
740 | */\r |
741 | typedef CM_ARM_GENERIC_INTERRUPT CM_ARM_EXTENDED_INTERRUPT;\r | |
26147c77 | 742 | \r |
77db1156 KK |
743 | /** A structure that describes the Processor Hierarchy Node (Type 0) in PPTT\r |
744 | \r | |
745 | ID: EArmObjProcHierarchyInfo\r | |
746 | */\r | |
747 | typedef struct CmArmProcHierarchyInfo {\r | |
748 | /// A unique token used to identify this object\r | |
731c67e1 | 749 | CM_OBJECT_TOKEN Token;\r |
77db1156 | 750 | /// Processor structure flags (ACPI 6.3 - January 2019, PPTT, Table 5-155)\r |
731c67e1 | 751 | UINT32 Flags;\r |
77db1156 KK |
752 | /// Token for the parent CM_ARM_PROC_HIERARCHY_INFO object in the processor\r |
753 | /// topology. A value of CM_NULL_TOKEN means this node has no parent.\r | |
731c67e1 | 754 | CM_OBJECT_TOKEN ParentToken;\r |
77db1156 KK |
755 | /// Token of the associated CM_ARM_GICC_INFO object which has the\r |
756 | /// corresponding ACPI Processor ID. A value of CM_NULL_TOKEN means this\r | |
757 | /// node represents a group of associated processors and it does not have an\r | |
758 | /// associated GIC CPU interface.\r | |
731c67e1 | 759 | CM_OBJECT_TOKEN GicCToken;\r |
77db1156 | 760 | /// Number of resources private to this Node\r |
731c67e1 | 761 | UINT32 NoOfPrivateResources;\r |
77db1156 KK |
762 | /// Token of the array which contains references to the resources private to\r |
763 | /// this CM_ARM_PROC_HIERARCHY_INFO instance. This field is ignored if\r | |
e3f8605a | 764 | /// the NoOfPrivateResources is 0, in which case it is recommended to set\r |
77db1156 | 765 | /// this field to CM_NULL_TOKEN.\r |
731c67e1 | 766 | CM_OBJECT_TOKEN PrivateResourcesArrayToken;\r |
f17ef10e PG |
767 | /// Optional field: Reference Token for the Lpi state of this processor.\r |
768 | /// Token identifying a CM_ARM_OBJ_REF structure, itself referencing\r | |
769 | /// CM_ARM_LPI_INFO objects.\r | |
731c67e1 | 770 | CM_OBJECT_TOKEN LpiToken;\r |
5fb3f572 JB |
771 | /// Set to TRUE if UID should override index for name and _UID\r |
772 | /// for processor container nodes and name of processors.\r | |
773 | /// This should be consistently set for containers or processors to avoid\r | |
774 | /// duplicate values\r | |
775 | BOOLEAN OverrideNameUidEnabled;\r | |
776 | /// If OverrideNameUidEnabled is TRUE then this value will be used for name of\r | |
777 | /// processors and processor containers.\r | |
778 | UINT16 OverrideName;\r | |
779 | /// If OverrideNameUidEnabled is TRUE then this value will be used for\r | |
780 | /// the UID of processor containers.\r | |
781 | UINT32 OverrideUid;\r | |
77db1156 KK |
782 | } CM_ARM_PROC_HIERARCHY_INFO;\r |
783 | \r | |
784 | /** A structure that describes the Cache Type Structure (Type 1) in PPTT\r | |
785 | \r | |
786 | ID: EArmObjCacheInfo\r | |
787 | */\r | |
788 | typedef struct CmArmCacheInfo {\r | |
789 | /// A unique token used to identify this object\r | |
731c67e1 | 790 | CM_OBJECT_TOKEN Token;\r |
77db1156 KK |
791 | /// Reference token for the next level of cache that is private to the same\r |
792 | /// CM_ARM_PROC_HIERARCHY_INFO instance. A value of CM_NULL_TOKEN means this\r | |
793 | /// entry represents the last cache level appropriate to the processor\r | |
794 | /// hierarchy node structures using this entry.\r | |
731c67e1 | 795 | CM_OBJECT_TOKEN NextLevelOfCacheToken;\r |
77db1156 | 796 | /// Size of the cache in bytes\r |
731c67e1 | 797 | UINT32 Size;\r |
77db1156 | 798 | /// Number of sets in the cache\r |
731c67e1 | 799 | UINT32 NumberOfSets;\r |
77db1156 KK |
800 | /// Integer number of ways. The maximum associativity supported by\r |
801 | /// ACPI Cache type structure is limited to MAX_UINT8. However,\r | |
802 | /// the maximum number of ways supported by the architecture is\r | |
803 | /// PPTT_ARM_CCIDX_CACHE_ASSOCIATIVITY_MAX. Therfore this field\r | |
804 | /// is 32-bit wide.\r | |
731c67e1 | 805 | UINT32 Associativity;\r |
e81a81e5 | 806 | /// Cache attributes (ACPI 6.4 - January 2021, PPTT, Table 5.140)\r |
731c67e1 | 807 | UINT8 Attributes;\r |
77db1156 | 808 | /// Line size in bytes\r |
731c67e1 | 809 | UINT16 LineSize;\r |
e81a81e5 CJ |
810 | /// Unique ID for the cache\r |
811 | UINT32 CacheId;\r | |
77db1156 KK |
812 | } CM_ARM_CACHE_INFO;\r |
813 | \r | |
77db1156 KK |
814 | /** A structure that describes a reference to another Configuration Manager\r |
815 | object.\r | |
816 | \r | |
817 | This is useful for creating an array of reference tokens. The framework\r | |
818 | can then query the configuration manager for these arrays using the\r | |
819 | object ID EArmObjCmRef.\r | |
820 | \r | |
821 | This can be used is to represent one-to-many relationships between objects.\r | |
822 | \r | |
823 | ID: EArmObjCmRef\r | |
824 | */\r | |
825 | typedef struct CmArmObjRef {\r | |
826 | /// Token of the CM object being referenced\r | |
731c67e1 | 827 | CM_OBJECT_TOKEN ReferenceToken;\r |
77db1156 KK |
828 | } CM_ARM_OBJ_REF;\r |
829 | \r | |
f413d9be SM |
830 | /** A structure that describes the Memory Affinity Structure (Type 1) in SRAT\r |
831 | \r | |
832 | ID: EArmObjMemoryAffinityInfo\r | |
833 | */\r | |
834 | typedef struct CmArmMemoryAffinityInfo {\r | |
835 | /// The proximity domain to which the "range of memory" belongs.\r | |
731c67e1 | 836 | UINT32 ProximityDomain;\r |
f413d9be SM |
837 | \r |
838 | /// Base Address\r | |
731c67e1 | 839 | UINT64 BaseAddress;\r |
f413d9be SM |
840 | \r |
841 | /// Length\r | |
731c67e1 | 842 | UINT64 Length;\r |
f413d9be SM |
843 | \r |
844 | /// Flags\r | |
731c67e1 | 845 | UINT32 Flags;\r |
f413d9be SM |
846 | } CM_ARM_MEMORY_AFFINITY_INFO;\r |
847 | \r | |
848 | /** A structure that describes the ACPI Device Handle (Type 0) in the\r | |
849 | Generic Initiator Affinity structure in SRAT\r | |
850 | \r | |
851 | ID: EArmObjDeviceHandleAcpi\r | |
852 | */\r | |
853 | typedef struct CmArmDeviceHandleAcpi {\r | |
854 | /// Hardware ID\r | |
731c67e1 | 855 | UINT64 Hid;\r |
f413d9be SM |
856 | \r |
857 | /// Unique Id\r | |
731c67e1 | 858 | UINT32 Uid;\r |
f413d9be SM |
859 | } CM_ARM_DEVICE_HANDLE_ACPI;\r |
860 | \r | |
861 | /** A structure that describes the PCI Device Handle (Type 1) in the\r | |
862 | Generic Initiator Affinity structure in SRAT\r | |
863 | \r | |
864 | ID: EArmObjDeviceHandlePci\r | |
865 | */\r | |
866 | typedef struct CmArmDeviceHandlePci {\r | |
867 | /// PCI Segment Number\r | |
731c67e1 | 868 | UINT16 SegmentNumber;\r |
f413d9be SM |
869 | \r |
870 | /// PCI Bus Number - Max 256 busses (Bits 15:8 of BDF)\r | |
731c67e1 | 871 | UINT8 BusNumber;\r |
f413d9be | 872 | \r |
e3f8605a | 873 | /// PCI Device Number - Max 32 devices (Bits 7:3 of BDF)\r |
731c67e1 | 874 | UINT8 DeviceNumber;\r |
f413d9be SM |
875 | \r |
876 | /// PCI Function Number - Max 8 functions (Bits 2:0 of BDF)\r | |
731c67e1 | 877 | UINT8 FunctionNumber;\r |
f413d9be SM |
878 | } CM_ARM_DEVICE_HANDLE_PCI;\r |
879 | \r | |
880 | /** A structure that describes the Generic Initiator Affinity structure in SRAT\r | |
881 | \r | |
882 | ID: EArmObjGenericInitiatorAffinityInfo\r | |
883 | */\r | |
884 | typedef struct CmArmGenericInitiatorAffinityInfo {\r | |
885 | /// The proximity domain to which the generic initiator belongs.\r | |
731c67e1 | 886 | UINT32 ProximityDomain;\r |
f413d9be SM |
887 | \r |
888 | /// Flags\r | |
731c67e1 | 889 | UINT32 Flags;\r |
f413d9be SM |
890 | \r |
891 | /// Device Handle Type\r | |
731c67e1 | 892 | UINT8 DeviceHandleType;\r |
f413d9be SM |
893 | \r |
894 | /// Reference Token for the Device Handle\r | |
731c67e1 | 895 | CM_OBJECT_TOKEN DeviceHandleToken;\r |
f413d9be SM |
896 | } CM_ARM_GENERIC_INITIATOR_AFFINITY_INFO;\r |
897 | \r | |
37568365 PG |
898 | /** A structure that describes the CMN-600 hardware.\r |
899 | \r | |
900 | ID: EArmObjCmn600Info\r | |
901 | */\r | |
902 | typedef struct CmArmCmn600Info {\r | |
903 | /// The PERIPHBASE address.\r | |
904 | /// Corresponds to the Configuration Node Region (CFGR) base address.\r | |
731c67e1 | 905 | UINT64 PeriphBaseAddress;\r |
37568365 PG |
906 | \r |
907 | /// The PERIPHBASE address length.\r | |
908 | /// Corresponds to the CFGR base address length.\r | |
731c67e1 | 909 | UINT64 PeriphBaseAddressLength;\r |
37568365 PG |
910 | \r |
911 | /// The ROOTNODEBASE address.\r | |
912 | /// Corresponds to the Root node (ROOT) base address.\r | |
731c67e1 | 913 | UINT64 RootNodeBaseAddress;\r |
37568365 PG |
914 | \r |
915 | /// The Debug and Trace Logic Controller (DTC) count.\r | |
916 | /// CMN-600 can have maximum 4 DTCs.\r | |
731c67e1 | 917 | UINT8 DtcCount;\r |
37568365 PG |
918 | \r |
919 | /// DTC Interrupt list.\r | |
920 | /// The first interrupt resource descriptor pertains to\r | |
921 | /// DTC[0], the second to DTC[1] and so on.\r | |
922 | /// DtcCount determines the number of DTC Interrupts that\r | |
923 | /// are populated. If DTC count is 2 then DtcInterrupt[2]\r | |
924 | /// and DtcInterrupt[3] are ignored.\r | |
925 | /// Note: The size of CM_ARM_CMN_600_INFO structure remains\r | |
926 | /// constant and does not vary with the DTC count.\r | |
731c67e1 | 927 | CM_ARM_EXTENDED_INTERRUPT DtcInterrupt[4];\r |
37568365 PG |
928 | } CM_ARM_CMN_600_INFO;\r |
929 | \r | |
f17ef10e PG |
930 | /** A structure that describes the Lpi information.\r |
931 | \r | |
932 | The Low Power Idle states are described in DSDT/SSDT and associated\r | |
933 | to cpus/clusters in the cpu topology.\r | |
934 | \r | |
935 | ID: EArmObjLpiInfo\r | |
936 | */\r | |
937 | typedef struct CmArmLpiInfo {\r | |
938 | /** Minimum Residency. Time in microseconds after which a\r | |
939 | state becomes more energy efficient than any shallower state.\r | |
940 | */\r | |
731c67e1 | 941 | UINT32 MinResidency;\r |
f17ef10e PG |
942 | \r |
943 | /** Worst case time in microseconds from a wake interrupt\r | |
944 | being asserted to the return to a running state\r | |
945 | */\r | |
731c67e1 | 946 | UINT32 WorstCaseWakeLatency;\r |
f17ef10e PG |
947 | \r |
948 | /** Flags.\r | |
949 | */\r | |
731c67e1 | 950 | UINT32 Flags;\r |
f17ef10e PG |
951 | \r |
952 | /** Architecture specific context loss flags.\r | |
953 | */\r | |
731c67e1 | 954 | UINT32 ArchFlags;\r |
f17ef10e PG |
955 | \r |
956 | /** Residency counter frequency in cycles-per-second (Hz).\r | |
957 | */\r | |
731c67e1 | 958 | UINT32 ResCntFreq;\r |
f17ef10e PG |
959 | \r |
960 | /** Every shallower power state in the parent is also enabled.\r | |
961 | */\r | |
731c67e1 | 962 | UINT32 EnableParentState;\r |
f17ef10e PG |
963 | \r |
964 | /** The EntryMethod _LPI field can be described as an integer\r | |
965 | or in a Register resource data descriptor.\r | |
966 | \r | |
967 | If IsInteger is TRUE, the IntegerEntryMethod field is used.\r | |
968 | If IsInteger is FALSE, the RegisterEntryMethod field is used.\r | |
969 | */\r | |
731c67e1 | 970 | BOOLEAN IsInteger;\r |
f17ef10e PG |
971 | \r |
972 | /** EntryMethod described as an Integer.\r | |
973 | */\r | |
731c67e1 | 974 | UINT64 IntegerEntryMethod;\r |
f17ef10e PG |
975 | \r |
976 | /** EntryMethod described as a EFI_ACPI_GENERIC_REGISTER_DESCRIPTOR.\r | |
977 | */\r | |
731c67e1 | 978 | EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE RegisterEntryMethod;\r |
f17ef10e PG |
979 | \r |
980 | /** Residency counter register.\r | |
981 | */\r | |
731c67e1 | 982 | EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE ResidencyCounterRegister;\r |
f17ef10e PG |
983 | \r |
984 | /** Usage counter register.\r | |
985 | */\r | |
731c67e1 | 986 | EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE UsageCounterRegister;\r |
f17ef10e PG |
987 | \r |
988 | /** String representing the Lpi state\r | |
989 | */\r | |
731c67e1 | 990 | CHAR8 StateName[16];\r |
f17ef10e PG |
991 | } CM_ARM_LPI_INFO;\r |
992 | \r | |
ce306e48 PG |
993 | /** A structure that describes a PCI Address Map.\r |
994 | \r | |
995 | The memory-ranges used by the PCI bus are described by this object.\r | |
996 | \r | |
997 | ID: EArmObjPciAddressMapInfo\r | |
998 | */\r | |
999 | typedef struct CmArmPciAddressMapInfo {\r | |
1000 | /** Pci address space code\r | |
1001 | \r | |
1002 | Available values are:\r | |
1003 | - 0: Configuration Space\r | |
1004 | - 1: I/O Space\r | |
1005 | - 2: 32-bit-address Memory Space\r | |
1006 | - 3: 64-bit-address Memory Space\r | |
1007 | */\r | |
1008 | UINT8 SpaceCode;\r | |
1009 | \r | |
1010 | /// PCI address\r | |
1011 | UINT64 PciAddress;\r | |
1012 | \r | |
1013 | /// Cpu address\r | |
1014 | UINT64 CpuAddress;\r | |
1015 | \r | |
1016 | /// Address size\r | |
1017 | UINT64 AddressSize;\r | |
1018 | } CM_ARM_PCI_ADDRESS_MAP_INFO;\r | |
1019 | \r | |
1020 | /** A structure that describes a PCI Interrupt Map.\r | |
1021 | \r | |
1022 | The legacy PCI interrupts used by PCI devices are described by this object.\r | |
1023 | \r | |
1024 | Cf Devicetree Specification - Release v0.3\r | |
1025 | s2.4.3 "Interrupt Nexus Properties"\r | |
1026 | \r | |
1027 | ID: EArmObjPciInterruptMapInfo\r | |
1028 | */\r | |
1029 | typedef struct CmArmPciInterruptMapInfo {\r | |
1030 | /// Pci Bus.\r | |
1031 | /// Value on 8 bits (max 255).\r | |
1032 | UINT8 PciBus;\r | |
1033 | \r | |
a5672d43 | 1034 | /// Pci Device.\r |
ce306e48 PG |
1035 | /// Value on 5 bits (max 31).\r |
1036 | UINT8 PciDevice;\r | |
1037 | \r | |
1038 | /** PCI interrupt\r | |
1039 | \r | |
1040 | ACPI bindings are used:\r | |
1041 | Cf. ACPI 6.4, s6.2.13 _PRT (PCI Routing Table):\r | |
1042 | "0-INTA, 1-INTB, 2-INTC, 3-INTD"\r | |
1043 | \r | |
1044 | Device-tree bindings are shifted by 1:\r | |
1045 | "INTA=1, INTB=2, INTC=3, INTD=4"\r | |
1046 | */\r | |
1047 | UINT8 PciInterrupt;\r | |
1048 | \r | |
1049 | /** Interrupt controller interrupt.\r | |
1050 | \r | |
1051 | Cf Devicetree Specification - Release v0.3\r | |
1052 | s2.4.3 "Interrupt Nexus Properties": "parent interrupt specifier"\r | |
1053 | */\r | |
1054 | CM_ARM_GENERIC_INTERRUPT IntcInterrupt;\r | |
1055 | } CM_ARM_PCI_INTERRUPT_MAP_INFO;\r | |
1056 | \r | |
de200b7e SM |
1057 | /** A structure that describes the\r |
1058 | RMR node for the Platform.\r | |
1059 | \r | |
1060 | ID: EArmObjRmr\r | |
1061 | */\r | |
1062 | typedef struct CmArmRmrNode {\r | |
1063 | /// An unique token used to identify this object\r | |
1064 | CM_OBJECT_TOKEN Token;\r | |
1065 | /// Number of ID mappings\r | |
1066 | UINT32 IdMappingCount;\r | |
1067 | /// Reference token for the ID mapping array\r | |
1068 | CM_OBJECT_TOKEN IdMappingToken;\r | |
1069 | \r | |
1070 | /// Unique identifier for this node.\r | |
1071 | UINT32 Identifier;\r | |
1072 | \r | |
1073 | /// Reserved Memory Range flags.\r | |
1074 | UINT32 Flags;\r | |
1075 | \r | |
1076 | /// Memory range descriptor count.\r | |
1077 | UINT32 MemRangeDescCount;\r | |
1078 | /// Reference token for the Memory Range descriptor array\r | |
1079 | CM_OBJECT_TOKEN MemRangeDescToken;\r | |
1080 | } CM_ARM_RMR_NODE;\r | |
1081 | \r | |
1082 | /** A structure that describes the\r | |
1083 | Memory Range descriptor.\r | |
1084 | \r | |
1085 | ID: EArmObjMemoryRangeDescriptor\r | |
1086 | */\r | |
1087 | typedef struct CmArmRmrDescriptor {\r | |
1088 | /// Base address of Reserved Memory Range,\r | |
1089 | /// aligned to a page size of 64K.\r | |
1090 | UINT64 BaseAddress;\r | |
1091 | \r | |
1092 | /// Length of the Reserved Memory range.\r | |
1093 | /// Must be a multiple of the page size of 64K.\r | |
1094 | UINT64 Length;\r | |
1095 | } CM_ARM_MEMORY_RANGE_DESCRIPTOR;\r | |
1096 | \r | |
09c90532 JB |
1097 | /** A structure that describes the Cpc information.\r |
1098 | \r | |
1099 | Continuous Performance Control is described in DSDT/SSDT and associated\r | |
1100 | to cpus/clusters in the cpu topology.\r | |
1101 | \r | |
1102 | Unsupported Optional registers should be encoded with NULL resource\r | |
1103 | Register {(SystemMemory, 0, 0, 0, 0)}\r | |
1104 | \r | |
1105 | For values that support Integer or Buffer, integer will be used\r | |
1106 | if buffer is NULL resource.\r | |
1107 | If resource is not NULL then Integer must be 0\r | |
1108 | \r | |
1109 | Cf. ACPI 6.4, s8.4.7.1 _CPC (Continuous Performance Control)\r | |
1110 | \r | |
1111 | ID: EArmObjCpcInfo\r | |
1112 | */\r | |
1113 | typedef AML_CPC_INFO CM_ARM_CPC_INFO;\r | |
1114 | \r | |
dab7bac9 PG |
1115 | /** A structure that describes a\r |
1116 | PCC Mailbox Register.\r | |
1117 | */\r | |
1118 | typedef struct PccMailboxRegisterInfo {\r | |
1119 | /// GAS describing the Register.\r | |
1120 | EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE Register;\r | |
1121 | \r | |
1122 | /** Mask of bits to preserve when writing.\r | |
1123 | \r | |
1124 | This mask is also used for registers. The Register is only read\r | |
1125 | and there is no write mask required. E.g.:\r | |
1126 | - Error Status mask (Cf. PCC Subspace types 3/4/5).\r | |
1127 | - Command Complete Check mask (Cf. PCC Subspace types 3/4/5).\r | |
1128 | */\r | |
1129 | UINT64 PreserveMask;\r | |
1130 | \r | |
1131 | /// Mask of bits to set when writing.\r | |
1132 | UINT64 WriteMask;\r | |
1133 | } PCC_MAILBOX_REGISTER_INFO;\r | |
1134 | \r | |
1135 | /** A structure that describes the\r | |
1136 | PCC Subspace CHannel Timings.\r | |
1137 | */\r | |
1138 | typedef struct PccSubspaceChannelTimingInfo {\r | |
1139 | /// Expected latency to process a command, in microseconds.\r | |
1140 | UINT32 NominalLatency;\r | |
1141 | \r | |
1142 | /** Maximum number of periodic requests that the subspace channel can\r | |
1143 | support, reported in commands per minute. 0 indicates no limitation.\r | |
1144 | \r | |
1145 | This field is ignored for the PCC Subspace type 5 (HW Registers based).\r | |
1146 | */\r | |
1147 | UINT32 MaxPeriodicAccessRate;\r | |
1148 | \r | |
1149 | /** Minimum amount of time that OSPM must wait after the completion\r | |
1150 | of a command before issuing the next command, in microseconds.\r | |
1151 | */\r | |
1152 | UINT16 MinRequestTurnaroundTime;\r | |
1153 | } PCC_SUBSPACE_CHANNEL_TIMING_INFO;\r | |
1154 | \r | |
1155 | /** A structure that describes a\r | |
1156 | Generic PCC Subspace (Type 0).\r | |
1157 | */\r | |
1158 | typedef struct CmArmPccSubspaceGenericInfo {\r | |
1159 | /** Subspace Id.\r | |
1160 | \r | |
1161 | Cf. ACPI 6.4, s14.7 Referencing the PCC address space\r | |
1162 | Cf. s14.1.2 Platform Communications Channel Subspace Structures\r | |
1163 | The subspace ID of a PCC subspace is its index in the array of\r | |
1164 | subspace structures, starting with subspace 0.\r | |
1165 | \r | |
1166 | At most 256 subspaces are supported.\r | |
1167 | */\r | |
1168 | UINT8 SubspaceId;\r | |
1169 | \r | |
1170 | /// Table type (or subspace).\r | |
1171 | UINT8 Type;\r | |
1172 | \r | |
1173 | /// Base address of the shared memory range.\r | |
1174 | /// This field is ignored for the PCC Subspace type 5 (HW Registers based).\r | |
1175 | UINT64 BaseAddress;\r | |
1176 | \r | |
1177 | /// Address length.\r | |
1178 | UINT64 AddressLength;\r | |
1179 | \r | |
1180 | /// Doorbell Register.\r | |
1181 | PCC_MAILBOX_REGISTER_INFO DoorbellReg;\r | |
1182 | \r | |
1183 | /// Mailbox Timings.\r | |
1184 | PCC_SUBSPACE_CHANNEL_TIMING_INFO ChannelTiming;\r | |
1185 | } PCC_SUBSPACE_GENERIC_INFO;\r | |
1186 | \r | |
1187 | /** A structure that describes a\r | |
1188 | PCC Subspace of type 0 (Generic).\r | |
1189 | \r | |
1190 | ID: EArmObjPccSubspaceType0Info\r | |
1191 | */\r | |
1192 | typedef PCC_SUBSPACE_GENERIC_INFO CM_ARM_PCC_SUBSPACE_TYPE0_INFO;\r | |
1193 | \r | |
1194 | /** A structure that describes a\r | |
1195 | PCC Subspace of type 1 (HW-Reduced).\r | |
1196 | \r | |
1197 | ID: EArmObjPccSubspaceType1Info\r | |
1198 | */\r | |
1199 | typedef struct CmArmPccSubspaceType1Info {\r | |
1200 | /** Generic Pcc information.\r | |
1201 | \r | |
1202 | The Subspace of Type0 contains information that can be re-used\r | |
1203 | in other Subspace types.\r | |
1204 | */\r | |
1205 | PCC_SUBSPACE_GENERIC_INFO GenericPccInfo;\r | |
1206 | \r | |
1207 | /// Platform Interrupt.\r | |
1208 | CM_ARM_GENERIC_INTERRUPT PlatIrq;\r | |
1209 | } CM_ARM_PCC_SUBSPACE_TYPE1_INFO;\r | |
1210 | \r | |
1211 | /** A structure that describes a\r | |
1212 | PCC Subspace of type 2 (HW-Reduced).\r | |
1213 | \r | |
1214 | ID: EArmObjPccSubspaceType2Info\r | |
1215 | */\r | |
1216 | typedef struct CmArmPccSubspaceType2Info {\r | |
1217 | /** Generic Pcc information.\r | |
1218 | \r | |
1219 | The Subspace of Type0 contains information that can be re-used\r | |
1220 | in other Subspace types.\r | |
1221 | */\r | |
1222 | PCC_SUBSPACE_GENERIC_INFO GenericPccInfo;\r | |
1223 | \r | |
1224 | /// Platform Interrupt.\r | |
1225 | CM_ARM_GENERIC_INTERRUPT PlatIrq;\r | |
1226 | \r | |
1227 | /// Platform Interrupt Register.\r | |
1228 | PCC_MAILBOX_REGISTER_INFO PlatIrqAckReg;\r | |
1229 | } CM_ARM_PCC_SUBSPACE_TYPE2_INFO;\r | |
1230 | \r | |
1231 | /** A structure that describes a\r | |
1232 | PCC Subspace of type 3 (Extended)\r | |
1233 | \r | |
1234 | ID: EArmObjPccSubspaceType3Info\r | |
1235 | */\r | |
1236 | typedef struct CmArmPccSubspaceType3Info {\r | |
1237 | /** Generic Pcc information.\r | |
1238 | \r | |
1239 | The Subspace of Type0 contains information that can be re-used\r | |
1240 | in other Subspace types.\r | |
1241 | */\r | |
1242 | PCC_SUBSPACE_GENERIC_INFO GenericPccInfo;\r | |
1243 | \r | |
1244 | /// Platform Interrupt.\r | |
1245 | CM_ARM_GENERIC_INTERRUPT PlatIrq;\r | |
1246 | \r | |
1247 | /// Platform Interrupt Register.\r | |
1248 | PCC_MAILBOX_REGISTER_INFO PlatIrqAckReg;\r | |
1249 | \r | |
1250 | /// Command Complete Check Register.\r | |
1251 | /// The WriteMask field is not used.\r | |
1252 | PCC_MAILBOX_REGISTER_INFO CmdCompleteCheckReg;\r | |
1253 | \r | |
1254 | /// Command Complete Update Register.\r | |
1255 | PCC_MAILBOX_REGISTER_INFO CmdCompleteUpdateReg;\r | |
1256 | \r | |
1257 | /// Error Status Register.\r | |
1258 | /// The WriteMask field is not used.\r | |
1259 | PCC_MAILBOX_REGISTER_INFO ErrorStatusReg;\r | |
1260 | } CM_ARM_PCC_SUBSPACE_TYPE3_INFO;\r | |
1261 | \r | |
1262 | /** A structure that describes a\r | |
1263 | PCC Subspace of type 4 (Extended)\r | |
1264 | \r | |
1265 | ID: EArmObjPccSubspaceType4Info\r | |
1266 | */\r | |
1267 | typedef CM_ARM_PCC_SUBSPACE_TYPE3_INFO CM_ARM_PCC_SUBSPACE_TYPE4_INFO;\r | |
1268 | \r | |
1269 | /** A structure that describes a\r | |
1270 | PCC Subspace of type 5 (HW-Registers).\r | |
1271 | \r | |
1272 | ID: EArmObjPccSubspaceType5Info\r | |
1273 | */\r | |
1274 | typedef struct CmArmPccSubspaceType5Info {\r | |
1275 | /** Generic Pcc information.\r | |
1276 | \r | |
1277 | The Subspace of Type0 contains information that can be re-used\r | |
1278 | in other Subspace types.\r | |
1279 | \r | |
1280 | MaximumPeriodicAccessRate doesn't need to be populated for\r | |
1281 | this structure.\r | |
1282 | */\r | |
1283 | PCC_SUBSPACE_GENERIC_INFO GenericPccInfo;\r | |
1284 | \r | |
1285 | /// Version.\r | |
1286 | UINT16 Version;\r | |
1287 | \r | |
1288 | /// Platform Interrupt.\r | |
1289 | CM_ARM_GENERIC_INTERRUPT PlatIrq;\r | |
1290 | \r | |
1291 | /// Command Complete Check Register.\r | |
1292 | /// The WriteMask field is not used.\r | |
1293 | PCC_MAILBOX_REGISTER_INFO CmdCompleteCheckReg;\r | |
1294 | \r | |
1295 | /// Error Status Register.\r | |
1296 | /// The WriteMask field is not used.\r | |
1297 | PCC_MAILBOX_REGISTER_INFO ErrorStatusReg;\r | |
1298 | } CM_ARM_PCC_SUBSPACE_TYPE5_INFO;\r | |
1299 | \r | |
26147c77 SM |
1300 | #pragma pack()\r |
1301 | \r | |
1302 | #endif // ARM_NAMESPACE_OBJECTS_H_\r |