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1 | /** @file\r |
2 | \r | |
3 | Copyright (c) 2017 - 2018, ARM Limited. All rights reserved.\r | |
4 | \r | |
5 | This program and the accompanying materials\r | |
6 | are licensed and made available under the terms and conditions of the BSD License\r | |
7 | which accompanies this distribution. The full text of the license may be found at\r | |
8 | http://opensource.org/licenses/bsd-license.php\r | |
9 | \r | |
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
12 | \r | |
13 | @par Glossary:\r | |
14 | - Cm or CM - Configuration Manager\r | |
15 | - Obj or OBJ - Object\r | |
16 | - Std or STD - Standard\r | |
17 | **/\r | |
18 | \r | |
19 | #ifndef ARM_NAMESPACE_OBJECTS_H_\r | |
20 | #define ARM_NAMESPACE_OBJECTS_H_\r | |
21 | \r | |
22 | #include <StandardNameSpaceObjects.h>\r | |
23 | \r | |
24 | #pragma pack(1)\r | |
25 | \r | |
26 | /** The EARM_OBJECT_ID enum describes the Object IDs\r | |
27 | in the ARM Namespace\r | |
28 | */\r | |
29 | typedef enum ArmObjectID {\r | |
30 | EArmObjReserved, ///< 0 - Reserved\r | |
31 | EArmObjBootArchInfo, ///< 1 - Boot Architecture Info\r | |
32 | EArmObjCpuInfo, ///< 2 - CPU Info\r | |
33 | EArmObjPowerManagementProfileInfo, ///< 3 - Power Management Profile Info\r | |
34 | EArmObjGicCInfo, ///< 4 - GIC CPU Interface Info\r | |
35 | EArmObjGicDInfo, ///< 5 - GIC Distributor Info\r | |
36 | EArmObjGicMsiFrameInfo, ///< 6 - GIC MSI Frame Info\r | |
37 | EArmObjGicRedistributorInfo, ///< 7 - GIC Redistributor Info\r | |
38 | EArmObjGicItsInfo, ///< 8 - GIC ITS Info\r | |
39 | EArmObjSerialConsolePortInfo, ///< 9 - Serial Console Port Info\r | |
40 | EArmObjSerialDebugPortInfo, ///< 10 - Serial Debug Port Info\r | |
41 | EArmObjGenericTimerInfo, ///< 11 - Generic Timer Info\r | |
42 | EArmObjPlatformGTBlockInfo, ///< 12 - Platform GT Block Info\r | |
43 | EArmObjGTBlockTimerFrameInfo, ///< 13 - Generic Timer Block Frame Info\r | |
44 | EArmObjPlatformGenericWatchdogInfo, ///< 14 - Platform Generic Watchdog\r | |
45 | EArmObjPciConfigSpaceInfo, ///< 15 - PCI Configuration Space Info\r | |
46 | EArmObjHypervisorVendorIdentity, ///< 16 - Hypervisor Vendor Id\r | |
47 | EArmObjFixedFeatureFlags, ///< 17 - Fixed feature flags for FADT\r | |
48 | EArmObjItsGroup, ///< 18 - ITS Group\r | |
49 | EArmObjNamedComponent, ///< 19 - Named Component\r | |
50 | EArmObjRootComplex, ///< 20 - Root Complex\r | |
51 | EArmObjSmmuV1SmmuV2, ///< 21 - SMMUv1 or SMMUv2\r | |
52 | EArmObjSmmuV3, ///< 22 - SMMUv3\r | |
53 | EArmObjPmcg, ///< 23 - PMCG\r | |
54 | EArmObjGicItsIdentifierArray, ///< 24 - GIC ITS Identifier Array\r | |
55 | EArmObjIdMapping, ///< 25 - ID Mapping\r | |
56 | EArmObjSmmuInterruptArray, ///< 26 - SMMU Interrupt Array\r | |
57 | EArmObjMax\r | |
58 | } EARM_OBJECT_ID;\r | |
59 | \r | |
60 | /** A structure that describes the\r | |
61 | ARM Boot Architecture flags.\r | |
62 | */\r | |
63 | typedef struct CmArmBootArchInfo {\r | |
64 | /** This is the ARM_BOOT_ARCH flags field of the FADT Table\r | |
65 | described in the ACPI Table Specification.\r | |
66 | */\r | |
67 | UINT32 BootArchFlags;\r | |
68 | } CM_ARM_BOOT_ARCH_INFO;\r | |
69 | \r | |
70 | typedef struct CmArmCpuInfo {\r | |
71 | // Reserved for use when SMBIOS tables are implemented\r | |
72 | } CM_ARM_CPU_INFO;\r | |
73 | \r | |
74 | typedef struct CmArmCpuInfoList {\r | |
75 | UINT32 CpuCount;\r | |
76 | CM_ARM_CPU_INFO * CpuInfo;\r | |
77 | } CM_ARM_CPU_INFO_LIST;\r | |
78 | \r | |
79 | /** A structure that describes the\r | |
80 | Power Management Profile Information for the Platform.\r | |
81 | */\r | |
82 | typedef struct CmArmPowerManagementProfileInfo {\r | |
83 | /** This is the Preferred_PM_Profile field of the FADT Table\r | |
84 | described in the ACPI Specification\r | |
85 | */\r | |
86 | UINT8 PowerManagementProfile;\r | |
87 | } CM_ARM_POWER_MANAGEMENT_PROFILE_INFO;\r | |
88 | \r | |
89 | /** A structure that describes the\r | |
90 | GIC CPU Interface for the Platform.\r | |
91 | */\r | |
92 | typedef struct CmArmGicCInfo {\r | |
93 | /// The GIC CPU Interface number.\r | |
94 | UINT32 CPUInterfaceNumber;\r | |
95 | \r | |
96 | /** The ACPI Processor UID. This must match the\r | |
97 | _UID of the CPU Device object information described\r | |
98 | in the DSDT/SSDT for the CPU.\r | |
99 | */\r | |
100 | UINT32 AcpiProcessorUid;\r | |
101 | \r | |
102 | /** The flags field as described by the GICC structure\r | |
103 | in the ACPI Specification.\r | |
104 | */\r | |
105 | UINT32 Flags;\r | |
106 | \r | |
107 | /** The parking protocol version field as described by\r | |
108 | the GICC structure in the ACPI Specification.\r | |
109 | */\r | |
110 | UINT32 ParkingProtocolVersion;\r | |
111 | \r | |
112 | /** The Performance Interrupt field as described by\r | |
113 | the GICC structure in the ACPI Specification.\r | |
114 | */\r | |
115 | UINT32 PerformanceInterruptGsiv;\r | |
116 | \r | |
117 | /** The CPU Parked address field as described by\r | |
118 | the GICC structure in the ACPI Specification.\r | |
119 | */\r | |
120 | UINT64 ParkedAddress;\r | |
121 | \r | |
122 | /** The base address for the GIC CPU Interface\r | |
123 | as described by the GICC structure in the\r | |
124 | ACPI Specification.\r | |
125 | */\r | |
126 | UINT64 PhysicalBaseAddress;\r | |
127 | \r | |
128 | /** The base address for GICV interface\r | |
129 | as described by the GICC structure in the\r | |
130 | ACPI Specification.\r | |
131 | */\r | |
132 | UINT64 GICV;\r | |
133 | \r | |
134 | /** The base address for GICH interface\r | |
135 | as described by the GICC structure in the\r | |
136 | ACPI Specification.\r | |
137 | */\r | |
138 | UINT64 GICH;\r | |
139 | \r | |
140 | /** The GICV maintenance interrupt\r | |
141 | as described by the GICC structure in the\r | |
142 | ACPI Specification.\r | |
143 | */\r | |
144 | UINT32 VGICMaintenanceInterrupt;\r | |
145 | \r | |
146 | /** The base address for GICR interface\r | |
147 | as described by the GICC structure in the\r | |
148 | ACPI Specification.\r | |
149 | */\r | |
150 | UINT64 GICRBaseAddress;\r | |
151 | \r | |
152 | /** The MPIDR for the CPU\r | |
153 | as described by the GICC structure in the\r | |
154 | ACPI Specification.\r | |
155 | */\r | |
156 | UINT64 MPIDR;\r | |
157 | \r | |
158 | /** The Processor Power Efficiency class\r | |
159 | as described by the GICC structure in the\r | |
160 | ACPI Specification.\r | |
161 | */\r | |
162 | UINT8 ProcessorPowerEfficiencyClass;\r | |
163 | } CM_ARM_GICC_INFO;\r | |
164 | \r | |
165 | /** A structure that describes the\r | |
166 | GIC Distributor information for the Platform.\r | |
167 | */\r | |
168 | typedef struct CmArmGicDInfo {\r | |
169 | /// The GIC Distributor ID.\r | |
170 | UINT32 GicId;\r | |
171 | \r | |
172 | /// The Physical Base address for the GIC Distributor.\r | |
173 | UINT64 PhysicalBaseAddress;\r | |
174 | \r | |
175 | /** The global system interrupt\r | |
176 | number where this GIC Distributor's\r | |
177 | interrupt inputs start.\r | |
178 | */\r | |
179 | UINT32 SystemVectorBase;\r | |
180 | \r | |
181 | /** The GIC version as described\r | |
182 | by the GICD structure in the\r | |
183 | ACPI Specification.\r | |
184 | */\r | |
185 | UINT8 GicVersion;\r | |
186 | } CM_ARM_GICD_INFO;\r | |
187 | \r | |
188 | /** A structure that describes the\r | |
189 | GIC MSI Frame information for the Platform.\r | |
190 | */\r | |
191 | typedef struct CmArmGicMsiFrameInfo {\r | |
192 | /// The GIC MSI Frame ID\r | |
193 | UINT32 GicMsiFrameId;\r | |
194 | \r | |
195 | /// The Physical base address for the MSI Frame\r | |
196 | UINT64 PhysicalBaseAddress;\r | |
197 | \r | |
198 | /** The GIC MSI Frame flags\r | |
199 | as described by the GIC MSI frame\r | |
200 | structure in the ACPI Specification.\r | |
201 | */\r | |
202 | UINT32 Flags;\r | |
203 | \r | |
204 | /// SPI Count used by this frame\r | |
205 | UINT16 SPICount;\r | |
206 | \r | |
207 | /// SPI Base used by this frame\r | |
208 | UINT16 SPIBase;\r | |
209 | } CM_ARM_GIC_MSI_FRAME_INFO;\r | |
210 | \r | |
211 | /** A structure that describes the\r | |
212 | GIC Redistributor information for the Platform.\r | |
213 | */\r | |
214 | typedef struct CmArmGicRedistInfo {\r | |
215 | /** The physical address of a page range\r | |
216 | containing all GIC Redistributors.\r | |
217 | */\r | |
218 | UINT64 DiscoveryRangeBaseAddress;\r | |
219 | \r | |
220 | /// Length of the GIC Redistributor Discovery page range\r | |
221 | UINT32 DiscoveryRangeLength;\r | |
222 | } CM_ARM_GIC_REDIST_INFO;\r | |
223 | \r | |
224 | /** A structure that describes the\r | |
225 | GIC Interrupt Translation Service information for the Platform.\r | |
226 | */\r | |
227 | typedef struct CmArmGicItsInfo {\r | |
228 | /// The GIC ITS ID\r | |
229 | UINT32 GicItsId;\r | |
230 | \r | |
231 | /// The physical address for the Interrupt Translation Service\r | |
232 | UINT64 PhysicalBaseAddress;\r | |
233 | } CM_ARM_GIC_ITS_INFO;\r | |
234 | \r | |
235 | /** A structure that describes the\r | |
236 | Serial Port information for the Platform.\r | |
237 | */\r | |
238 | typedef struct CmArmSerialPortInfo {\r | |
239 | /// The physical base address for the serial port\r | |
240 | UINT64 BaseAddress;\r | |
241 | \r | |
242 | /// The serial port interrupt\r | |
243 | UINT32 Interrupt;\r | |
244 | \r | |
245 | /// The serial port baud rate\r | |
246 | UINT64 BaudRate;\r | |
247 | \r | |
248 | /// The serial port clock\r | |
249 | UINT32 Clock;\r | |
250 | \r | |
251 | /// Serial Port subtype\r | |
252 | UINT16 PortSubtype;\r | |
253 | } CM_ARM_SERIAL_PORT_INFO;\r | |
254 | \r | |
255 | /** A structure that describes the\r | |
256 | Generic Timer information for the Platform.\r | |
257 | */\r | |
258 | typedef struct CmArmGenericTimerInfo {\r | |
259 | /// The physical base address for the counter control frame\r | |
260 | UINT64 CounterControlBaseAddress;\r | |
261 | \r | |
262 | /// The physical base address for the counter read frame\r | |
263 | UINT64 CounterReadBaseAddress;\r | |
264 | \r | |
265 | /// The secure PL1 timer interrupt\r | |
266 | UINT32 SecurePL1TimerGSIV;\r | |
267 | \r | |
268 | /// The secure PL1 timer flags\r | |
269 | UINT32 SecurePL1TimerFlags;\r | |
270 | \r | |
271 | /// The non-secure PL1 timer interrupt\r | |
272 | UINT32 NonSecurePL1TimerGSIV;\r | |
273 | \r | |
274 | /// The non-secure PL1 timer flags\r | |
275 | UINT32 NonSecurePL1TimerFlags;\r | |
276 | \r | |
277 | /// The virtual timer interrupt\r | |
278 | UINT32 VirtualTimerGSIV;\r | |
279 | \r | |
280 | /// The virtual timer flags\r | |
281 | UINT32 VirtualTimerFlags;\r | |
282 | \r | |
283 | /// The non-secure PL2 timer interrupt\r | |
284 | UINT32 NonSecurePL2TimerGSIV;\r | |
285 | \r | |
286 | /// The non-secure PL2 timer flags\r | |
287 | UINT32 NonSecurePL2TimerFlags;\r | |
288 | } CM_ARM_GENERIC_TIMER_INFO;\r | |
289 | \r | |
290 | /** A structure that describes the\r | |
291 | Platform Generic Block Timer Frame information for the Platform.\r | |
292 | */\r | |
293 | typedef struct CmArmGTBlockTimerFrameInfo {\r | |
294 | /// The Generic Timer frame number\r | |
295 | UINT8 FrameNumber;\r | |
296 | \r | |
297 | /// The physical base address for the CntBase block\r | |
298 | UINT64 PhysicalAddressCntBase;\r | |
299 | \r | |
300 | /// The physical base address for the CntEL0Base block\r | |
301 | UINT64 PhysicalAddressCntEL0Base;\r | |
302 | \r | |
303 | /// The physical timer interrupt\r | |
304 | UINT32 PhysicalTimerGSIV;\r | |
305 | \r | |
306 | /** The physical timer flags as described by the GT Block\r | |
307 | Timer frame Structure in the ACPI Specification.\r | |
308 | */\r | |
309 | UINT32 PhysicalTimerFlags;\r | |
310 | \r | |
311 | /// The virtual timer interrupt\r | |
312 | UINT32 VirtualTimerGSIV;\r | |
313 | \r | |
314 | /** The virtual timer flags as described by the GT Block\r | |
315 | Timer frame Structure in the ACPI Specification.\r | |
316 | */\r | |
317 | UINT32 VirtualTimerFlags;\r | |
318 | \r | |
319 | /** The common timer flags as described by the GT Block\r | |
320 | Timer frame Structure in the ACPI Specification.\r | |
321 | */\r | |
322 | UINT32 CommonFlags;\r | |
323 | } CM_ARM_GTBLOCK_TIMER_FRAME_INFO;\r | |
324 | \r | |
325 | /** A structure that describes the\r | |
326 | Platform Generic Block Timer information for the Platform.\r | |
327 | */\r | |
328 | typedef struct CmArmGTBlockInfo {\r | |
329 | /// The physical base address for the GT Block Timer structure\r | |
330 | UINT64 GTBlockPhysicalAddress;\r | |
331 | \r | |
332 | /// The number of timer frames implemented in the GT Block\r | |
333 | UINT32 GTBlockTimerFrameCount;\r | |
334 | \r | |
335 | /// Reference token for the GT Block timer frame list\r | |
336 | CM_OBJECT_TOKEN GTBlockTimerFrameToken;\r | |
337 | } CM_ARM_GTBLOCK_INFO;\r | |
338 | \r | |
339 | /** A structure that describes the\r | |
340 | SBSA Generic Watchdog information for the Platform.\r | |
341 | */\r | |
342 | typedef struct CmArmGenericWatchdogInfo {\r | |
343 | /// The physical base address of the SBSA Watchdog control frame\r | |
344 | UINT64 ControlFrameAddress;\r | |
345 | \r | |
346 | /// The physical base address of the SBSA Watchdog refresh frame\r | |
347 | UINT64 RefreshFrameAddress;\r | |
348 | \r | |
349 | /// The watchdog interrupt\r | |
350 | UINT32 TimerGSIV;\r | |
351 | \r | |
352 | /** The flags for the watchdog as described by the SBSA watchdog\r | |
353 | structure in the ACPI specification.\r | |
354 | */\r | |
355 | UINT32 Flags;\r | |
356 | } CM_ARM_GENERIC_WATCHDOG_INFO;\r | |
357 | \r | |
358 | /** A structure that describes the\r | |
359 | PCI Configuration Space information for the Platform.\r | |
360 | */\r | |
361 | typedef struct CmArmPciConfigSpaceInfo {\r | |
362 | /// The physical base address for the PCI segment\r | |
363 | UINT64 BaseAddress;\r | |
364 | \r | |
365 | /// The PCI segment group number\r | |
366 | UINT16 PciSegmentGroupNumber;\r | |
367 | \r | |
368 | /// The start bus number\r | |
369 | UINT8 StartBusNumber;\r | |
370 | \r | |
371 | /// The end bus number\r | |
372 | UINT8 EndBusNumber;\r | |
373 | } CM_ARM_PCI_CONFIG_SPACE_INFO;\r | |
374 | \r | |
375 | /** A structure that describes the\r | |
376 | Hypervisor Vendor ID information for the Platform.\r | |
377 | */\r | |
378 | typedef struct CmArmHypervisorVendorId {\r | |
379 | /// The hypervisor Vendor ID\r | |
380 | UINT64 HypervisorVendorId;\r | |
381 | } CM_ARM_HYPERVISOR_VENDOR_ID;\r | |
382 | \r | |
383 | /** A structure that describes the\r | |
384 | Fixed feature flags for the Platform.\r | |
385 | */\r | |
386 | typedef struct CmArmFixedFeatureFlags {\r | |
387 | /// The Fixed feature flags\r | |
388 | UINT32 Flags;\r | |
389 | } CM_ARM_FIXED_FEATURE_FLAGS;\r | |
390 | \r | |
391 | /** A structure that describes the\r | |
392 | ITS Group node for the Platform.\r | |
393 | */\r | |
394 | typedef struct CmArmItsGroupNode {\r | |
395 | /// An unique token used to ideintify this object\r | |
396 | CM_OBJECT_TOKEN Token;\r | |
397 | /// The number of ITS identifiers in the ITS node\r | |
398 | UINT32 ItsIdCount;\r | |
399 | /// Reference token for the ITS identifier array\r | |
400 | CM_OBJECT_TOKEN ItsIdToken;\r | |
401 | } CM_ARM_ITS_GROUP_NODE;\r | |
402 | \r | |
403 | /** A structure that describes the\r | |
404 | GIC ITS Identifiers for an ITS Group node.\r | |
405 | */\r | |
406 | typedef struct CmArmGicItsIdentifier {\r | |
407 | /// The ITS Identifier\r | |
408 | UINT32 ItsId;\r | |
409 | } CM_ARM_ITS_IDENTIFIER;\r | |
410 | \r | |
411 | /** A structure that describes the\r | |
412 | Named component node for the Platform.\r | |
413 | */\r | |
414 | typedef struct CmArmNamedComponentNode {\r | |
415 | /// An unique token used to ideintify this object\r | |
416 | CM_OBJECT_TOKEN Token;\r | |
417 | /// Number of ID mappings\r | |
418 | UINT32 IdMappingCount;\r | |
419 | /// Reference token for the ID mapping array\r | |
420 | CM_OBJECT_TOKEN IdMappingToken;\r | |
421 | \r | |
422 | /// Flags for the named component\r | |
423 | UINT32 Flags;\r | |
424 | \r | |
425 | /// Memory access properties : Cache coherent attributes\r | |
426 | UINT32 CacheCoherent;\r | |
427 | /// Memory access properties : Allocation hints\r | |
428 | UINT8 AllocationHints;\r | |
429 | /// Memory access properties : Memory access flags\r | |
430 | UINT8 MemoryAccessFlags;\r | |
431 | \r | |
432 | /// Memory access properties : Address size limit\r | |
433 | UINT8 AddressSizeLimit;\r | |
434 | /** ASCII Null terminated string with the full path to\r | |
435 | the entry in the namespace for this object.\r | |
436 | */\r | |
437 | CHAR8* ObjectName;\r | |
438 | } CM_ARM_NAMED_COMPONENT_NODE;\r | |
439 | \r | |
440 | /** A structure that describes the\r | |
441 | Root complex node for the Platform.\r | |
442 | */\r | |
443 | typedef struct CmArmRootComplexNode {\r | |
444 | /// An unique token used to ideintify this object\r | |
445 | CM_OBJECT_TOKEN Token;\r | |
446 | /// Number of ID mappings\r | |
447 | UINT32 IdMappingCount;\r | |
448 | /// Reference token for the ID mapping array\r | |
449 | CM_OBJECT_TOKEN IdMappingToken;\r | |
450 | \r | |
451 | /// Memory access properties : Cache coherent attributes\r | |
452 | UINT32 CacheCoherent;\r | |
453 | /// Memory access properties : Allocation hints\r | |
454 | UINT8 AllocationHints;\r | |
455 | /// Memory access properties : Memory access flags\r | |
456 | UINT8 MemoryAccessFlags;\r | |
457 | \r | |
458 | /// ATS attributes\r | |
459 | UINT32 AtsAttribute;\r | |
460 | /// PCI segment number\r | |
461 | UINT32 PciSegmentNumber;\r | |
462 | /// Memory address size limit\r | |
463 | UINT8 MemoryAddressSize;\r | |
464 | } CM_ARM_ROOT_COMPLEX_NODE;\r | |
465 | \r | |
466 | /** A structure that describes the\r | |
467 | SMMUv1 or SMMUv2 node for the Platform.\r | |
468 | */\r | |
469 | typedef struct CmArmSmmuV1SmmuV2Node {\r | |
470 | /// An unique token used to ideintify this object\r | |
471 | CM_OBJECT_TOKEN Token;\r | |
472 | /// Number of ID mappings\r | |
473 | UINT32 IdMappingCount;\r | |
474 | /// Reference token for the ID mapping array\r | |
475 | CM_OBJECT_TOKEN IdMappingToken;\r | |
476 | \r | |
477 | /// SMMU Base Address\r | |
478 | UINT64 BaseAddress;\r | |
479 | /// Length of the memory range covered by the SMMU\r | |
480 | UINT64 Span;\r | |
481 | /// SMMU Model\r | |
482 | UINT32 Model;\r | |
483 | /// SMMU flags\r | |
484 | UINT32 Flags;\r | |
485 | \r | |
486 | /// Number of context interrupts\r | |
487 | UINT32 ContextInterruptCount;\r | |
488 | /// Reference token for the context interrupt array\r | |
489 | CM_OBJECT_TOKEN ContextInterruptToken;\r | |
490 | \r | |
491 | /// Number of PMU interrupts\r | |
492 | UINT32 PmuInterruptCount;\r | |
493 | /// Reference token for the PMU interrupt array\r | |
494 | CM_OBJECT_TOKEN PmuInterruptToken;\r | |
495 | \r | |
496 | /// GSIV of the SMMU_NSgIrpt interrupt\r | |
497 | UINT32 SMMU_NSgIrpt;\r | |
498 | /// SMMU_NSgIrpt interrupt flags\r | |
499 | UINT32 SMMU_NSgIrptFlags;\r | |
500 | /// GSIV of the SMMU_NSgCfgIrpt interrupt\r | |
501 | UINT32 SMMU_NSgCfgIrpt;\r | |
502 | /// SMMU_NSgCfgIrpt interrupt flags\r | |
503 | UINT32 SMMU_NSgCfgIrptFlags;\r | |
504 | } CM_ARM_SMMUV1_SMMUV2_NODE;\r | |
505 | \r | |
506 | /** A structure that describes the\r | |
507 | SMMUv3 node for the Platform.\r | |
508 | */\r | |
509 | typedef struct CmArmSmmuV3Node {\r | |
510 | /// An unique token used to ideintify this object\r | |
511 | CM_OBJECT_TOKEN Token;\r | |
512 | /// Number of ID mappings\r | |
513 | UINT32 IdMappingCount;\r | |
514 | /// Reference token for the ID mapping array\r | |
515 | CM_OBJECT_TOKEN IdMappingToken;\r | |
516 | \r | |
517 | /// SMMU Base Address\r | |
518 | UINT64 BaseAddress;\r | |
519 | /// SMMU flags\r | |
520 | UINT32 Flags;\r | |
521 | /// VATOS address\r | |
522 | UINT64 VatosAddress;\r | |
523 | /// Model\r | |
524 | UINT32 Model;\r | |
525 | /// GSIV of the Event interrupt if SPI based\r | |
526 | UINT32 EventInterrupt;\r | |
527 | /// PRI Interrupt if SPI based\r | |
528 | UINT32 PriInterrupt;\r | |
529 | /// GERR interrupt if GSIV based\r | |
530 | UINT32 GerrInterrupt;\r | |
531 | /// Sync interrupt if GSIV based\r | |
532 | UINT32 SyncInterrupt;\r | |
533 | \r | |
534 | /// Proximity domain flag\r | |
535 | UINT32 ProximityDomain;\r | |
536 | /// Index into the array of ID mapping\r | |
537 | UINT32 DeviceIdMappingIndex;\r | |
538 | } CM_ARM_SMMUV3_NODE;\r | |
539 | \r | |
540 | /** A structure that describes the\r | |
541 | PMCG node for the Platform.\r | |
542 | */\r | |
543 | typedef struct CmArmPmcgNode {\r | |
544 | /// An unique token used to ideintify this object\r | |
545 | CM_OBJECT_TOKEN Token;\r | |
546 | /// Number of ID mappings\r | |
547 | UINT32 IdMappingCount;\r | |
548 | /// Reference token for the ID mapping array\r | |
549 | CM_OBJECT_TOKEN IdMappingToken;\r | |
550 | \r | |
551 | /// Base Address for performance monitor counter group\r | |
552 | UINT64 BaseAddress;\r | |
553 | /// GSIV for the Overflow interrupt\r | |
554 | UINT32 OverflowInterrupt;\r | |
555 | /// Page 1 Base address\r | |
556 | UINT64 Page1BaseAddress;\r | |
557 | \r | |
558 | /// Reference token for the IORT node associated with this node\r | |
559 | CM_OBJECT_TOKEN ReferenceToken;\r | |
560 | } CM_ARM_PMCG_NODE;\r | |
561 | \r | |
562 | /** A structure that describes the\r | |
563 | ID Mappings for the Platform.\r | |
564 | */\r | |
565 | typedef struct CmArmIdMapping {\r | |
566 | /// Input base\r | |
567 | UINT32 InputBase;\r | |
568 | /// Number of input IDs\r | |
569 | UINT32 NumIds;\r | |
570 | /// Output Base\r | |
571 | UINT32 OutputBase;\r | |
572 | /// Reference token for the output node\r | |
573 | CM_OBJECT_TOKEN OutputReferenceToken;\r | |
574 | /// Flags\r | |
575 | UINT32 Flags;\r | |
576 | } CM_ARM_ID_MAPPING;\r | |
577 | \r | |
578 | /** A structure that describes the\r | |
579 | SMMU interrupts for the Platform.\r | |
580 | */\r | |
581 | typedef struct CmArmSmmuInterrupt {\r | |
582 | /// Interrupt number\r | |
583 | UINT32 Interrupt;\r | |
584 | \r | |
585 | /// Flags\r | |
586 | UINT32 Flags;\r | |
587 | } CM_ARM_SMMU_INTERRUPT;\r | |
588 | \r | |
589 | #pragma pack()\r | |
590 | \r | |
591 | #endif // ARM_NAMESPACE_OBJECTS_H_\r |