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26147c77 SM |
1 | /** @file\r |
2 | \r | |
24534823 | 3 | Copyright (c) 2017 - 2019, ARM Limited. All rights reserved.\r |
26147c77 | 4 | \r |
9cd9bdc6 | 5 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
26147c77 SM |
6 | \r |
7 | @par Glossary:\r | |
8 | - Cm or CM - Configuration Manager\r | |
9 | - Obj or OBJ - Object\r | |
10 | - Std or STD - Standard\r | |
11 | **/\r | |
12 | \r | |
13 | #ifndef ARM_NAMESPACE_OBJECTS_H_\r | |
14 | #define ARM_NAMESPACE_OBJECTS_H_\r | |
15 | \r | |
16 | #include <StandardNameSpaceObjects.h>\r | |
17 | \r | |
18 | #pragma pack(1)\r | |
19 | \r | |
20 | /** The EARM_OBJECT_ID enum describes the Object IDs\r | |
21 | in the ARM Namespace\r | |
22 | */\r | |
23 | typedef enum ArmObjectID {\r | |
24 | EArmObjReserved, ///< 0 - Reserved\r | |
25 | EArmObjBootArchInfo, ///< 1 - Boot Architecture Info\r | |
26 | EArmObjCpuInfo, ///< 2 - CPU Info\r | |
27 | EArmObjPowerManagementProfileInfo, ///< 3 - Power Management Profile Info\r | |
28 | EArmObjGicCInfo, ///< 4 - GIC CPU Interface Info\r | |
29 | EArmObjGicDInfo, ///< 5 - GIC Distributor Info\r | |
30 | EArmObjGicMsiFrameInfo, ///< 6 - GIC MSI Frame Info\r | |
31 | EArmObjGicRedistributorInfo, ///< 7 - GIC Redistributor Info\r | |
32 | EArmObjGicItsInfo, ///< 8 - GIC ITS Info\r | |
33 | EArmObjSerialConsolePortInfo, ///< 9 - Serial Console Port Info\r | |
34 | EArmObjSerialDebugPortInfo, ///< 10 - Serial Debug Port Info\r | |
35 | EArmObjGenericTimerInfo, ///< 11 - Generic Timer Info\r | |
36 | EArmObjPlatformGTBlockInfo, ///< 12 - Platform GT Block Info\r | |
37 | EArmObjGTBlockTimerFrameInfo, ///< 13 - Generic Timer Block Frame Info\r | |
38 | EArmObjPlatformGenericWatchdogInfo, ///< 14 - Platform Generic Watchdog\r | |
39 | EArmObjPciConfigSpaceInfo, ///< 15 - PCI Configuration Space Info\r | |
40 | EArmObjHypervisorVendorIdentity, ///< 16 - Hypervisor Vendor Id\r | |
41 | EArmObjFixedFeatureFlags, ///< 17 - Fixed feature flags for FADT\r | |
42 | EArmObjItsGroup, ///< 18 - ITS Group\r | |
43 | EArmObjNamedComponent, ///< 19 - Named Component\r | |
44 | EArmObjRootComplex, ///< 20 - Root Complex\r | |
45 | EArmObjSmmuV1SmmuV2, ///< 21 - SMMUv1 or SMMUv2\r | |
46 | EArmObjSmmuV3, ///< 22 - SMMUv3\r | |
47 | EArmObjPmcg, ///< 23 - PMCG\r | |
48 | EArmObjGicItsIdentifierArray, ///< 24 - GIC ITS Identifier Array\r | |
98a4a7a9 | 49 | EArmObjIdMappingArray, ///< 25 - ID Mapping Array\r |
26147c77 | 50 | EArmObjSmmuInterruptArray, ///< 26 - SMMU Interrupt Array\r |
77db1156 KK |
51 | EArmObjProcHierarchyInfo, ///< 27 - Processor Hierarchy Info\r |
52 | EArmObjCacheInfo, ///< 28 - Cache Info\r | |
53 | EArmObjProcNodeIdInfo, ///< 29 - Processor Hierarchy Node ID Info\r | |
54 | EArmObjCmRef, ///< 30 - CM Object Reference\r | |
26147c77 SM |
55 | EArmObjMax\r |
56 | } EARM_OBJECT_ID;\r | |
57 | \r | |
58 | /** A structure that describes the\r | |
59 | ARM Boot Architecture flags.\r | |
c606f472 SM |
60 | \r |
61 | ID: EArmObjBootArchInfo\r | |
26147c77 SM |
62 | */\r |
63 | typedef struct CmArmBootArchInfo {\r | |
64 | /** This is the ARM_BOOT_ARCH flags field of the FADT Table\r | |
65 | described in the ACPI Table Specification.\r | |
66 | */\r | |
67 | UINT32 BootArchFlags;\r | |
68 | } CM_ARM_BOOT_ARCH_INFO;\r | |
69 | \r | |
70 | typedef struct CmArmCpuInfo {\r | |
71 | // Reserved for use when SMBIOS tables are implemented\r | |
72 | } CM_ARM_CPU_INFO;\r | |
73 | \r | |
26147c77 SM |
74 | /** A structure that describes the\r |
75 | Power Management Profile Information for the Platform.\r | |
c606f472 SM |
76 | \r |
77 | ID: EArmObjPowerManagementProfileInfo\r | |
26147c77 SM |
78 | */\r |
79 | typedef struct CmArmPowerManagementProfileInfo {\r | |
80 | /** This is the Preferred_PM_Profile field of the FADT Table\r | |
81 | described in the ACPI Specification\r | |
82 | */\r | |
83 | UINT8 PowerManagementProfile;\r | |
84 | } CM_ARM_POWER_MANAGEMENT_PROFILE_INFO;\r | |
85 | \r | |
86 | /** A structure that describes the\r | |
87 | GIC CPU Interface for the Platform.\r | |
c606f472 SM |
88 | \r |
89 | ID: EArmObjGicCInfo\r | |
26147c77 SM |
90 | */\r |
91 | typedef struct CmArmGicCInfo {\r | |
92 | /// The GIC CPU Interface number.\r | |
93 | UINT32 CPUInterfaceNumber;\r | |
94 | \r | |
95 | /** The ACPI Processor UID. This must match the\r | |
96 | _UID of the CPU Device object information described\r | |
97 | in the DSDT/SSDT for the CPU.\r | |
98 | */\r | |
99 | UINT32 AcpiProcessorUid;\r | |
100 | \r | |
101 | /** The flags field as described by the GICC structure\r | |
102 | in the ACPI Specification.\r | |
103 | */\r | |
104 | UINT32 Flags;\r | |
105 | \r | |
106 | /** The parking protocol version field as described by\r | |
107 | the GICC structure in the ACPI Specification.\r | |
108 | */\r | |
109 | UINT32 ParkingProtocolVersion;\r | |
110 | \r | |
111 | /** The Performance Interrupt field as described by\r | |
112 | the GICC structure in the ACPI Specification.\r | |
113 | */\r | |
114 | UINT32 PerformanceInterruptGsiv;\r | |
115 | \r | |
116 | /** The CPU Parked address field as described by\r | |
117 | the GICC structure in the ACPI Specification.\r | |
118 | */\r | |
119 | UINT64 ParkedAddress;\r | |
120 | \r | |
121 | /** The base address for the GIC CPU Interface\r | |
122 | as described by the GICC structure in the\r | |
123 | ACPI Specification.\r | |
124 | */\r | |
125 | UINT64 PhysicalBaseAddress;\r | |
126 | \r | |
127 | /** The base address for GICV interface\r | |
128 | as described by the GICC structure in the\r | |
129 | ACPI Specification.\r | |
130 | */\r | |
131 | UINT64 GICV;\r | |
132 | \r | |
133 | /** The base address for GICH interface\r | |
134 | as described by the GICC structure in the\r | |
135 | ACPI Specification.\r | |
136 | */\r | |
137 | UINT64 GICH;\r | |
138 | \r | |
139 | /** The GICV maintenance interrupt\r | |
140 | as described by the GICC structure in the\r | |
141 | ACPI Specification.\r | |
142 | */\r | |
143 | UINT32 VGICMaintenanceInterrupt;\r | |
144 | \r | |
145 | /** The base address for GICR interface\r | |
146 | as described by the GICC structure in the\r | |
147 | ACPI Specification.\r | |
148 | */\r | |
149 | UINT64 GICRBaseAddress;\r | |
150 | \r | |
151 | /** The MPIDR for the CPU\r | |
152 | as described by the GICC structure in the\r | |
153 | ACPI Specification.\r | |
154 | */\r | |
155 | UINT64 MPIDR;\r | |
156 | \r | |
157 | /** The Processor Power Efficiency class\r | |
158 | as described by the GICC structure in the\r | |
159 | ACPI Specification.\r | |
160 | */\r | |
161 | UINT8 ProcessorPowerEfficiencyClass;\r | |
5506701f KK |
162 | \r |
163 | /** Statistical Profiling Extension buffer overflow GSIV. Zero if\r | |
164 | unsupported by this processor. This field was introduced in\r | |
165 | ACPI 6.3 (MADT revision 5) and is therefore ignored when\r | |
166 | generating MADT revision 4 or lower.\r | |
167 | */\r | |
168 | UINT16 SpeOverflowInterrupt;\r | |
26147c77 SM |
169 | } CM_ARM_GICC_INFO;\r |
170 | \r | |
171 | /** A structure that describes the\r | |
172 | GIC Distributor information for the Platform.\r | |
c606f472 SM |
173 | \r |
174 | ID: EArmObjGicDInfo\r | |
26147c77 SM |
175 | */\r |
176 | typedef struct CmArmGicDInfo {\r | |
26147c77 SM |
177 | /// The Physical Base address for the GIC Distributor.\r |
178 | UINT64 PhysicalBaseAddress;\r | |
179 | \r | |
180 | /** The global system interrupt\r | |
181 | number where this GIC Distributor's\r | |
182 | interrupt inputs start.\r | |
183 | */\r | |
184 | UINT32 SystemVectorBase;\r | |
185 | \r | |
186 | /** The GIC version as described\r | |
187 | by the GICD structure in the\r | |
188 | ACPI Specification.\r | |
189 | */\r | |
190 | UINT8 GicVersion;\r | |
191 | } CM_ARM_GICD_INFO;\r | |
192 | \r | |
193 | /** A structure that describes the\r | |
194 | GIC MSI Frame information for the Platform.\r | |
c606f472 SM |
195 | \r |
196 | ID: EArmObjGicMsiFrameInfo\r | |
26147c77 SM |
197 | */\r |
198 | typedef struct CmArmGicMsiFrameInfo {\r | |
199 | /// The GIC MSI Frame ID\r | |
200 | UINT32 GicMsiFrameId;\r | |
201 | \r | |
202 | /// The Physical base address for the MSI Frame\r | |
203 | UINT64 PhysicalBaseAddress;\r | |
204 | \r | |
205 | /** The GIC MSI Frame flags\r | |
206 | as described by the GIC MSI frame\r | |
207 | structure in the ACPI Specification.\r | |
208 | */\r | |
209 | UINT32 Flags;\r | |
210 | \r | |
211 | /// SPI Count used by this frame\r | |
212 | UINT16 SPICount;\r | |
213 | \r | |
214 | /// SPI Base used by this frame\r | |
215 | UINT16 SPIBase;\r | |
216 | } CM_ARM_GIC_MSI_FRAME_INFO;\r | |
217 | \r | |
218 | /** A structure that describes the\r | |
219 | GIC Redistributor information for the Platform.\r | |
c606f472 SM |
220 | \r |
221 | ID: EArmObjGicRedistributorInfo\r | |
26147c77 SM |
222 | */\r |
223 | typedef struct CmArmGicRedistInfo {\r | |
224 | /** The physical address of a page range\r | |
225 | containing all GIC Redistributors.\r | |
226 | */\r | |
227 | UINT64 DiscoveryRangeBaseAddress;\r | |
228 | \r | |
229 | /// Length of the GIC Redistributor Discovery page range\r | |
230 | UINT32 DiscoveryRangeLength;\r | |
231 | } CM_ARM_GIC_REDIST_INFO;\r | |
232 | \r | |
233 | /** A structure that describes the\r | |
234 | GIC Interrupt Translation Service information for the Platform.\r | |
c606f472 SM |
235 | \r |
236 | ID: EArmObjGicItsInfo\r | |
26147c77 SM |
237 | */\r |
238 | typedef struct CmArmGicItsInfo {\r | |
239 | /// The GIC ITS ID\r | |
240 | UINT32 GicItsId;\r | |
241 | \r | |
242 | /// The physical address for the Interrupt Translation Service\r | |
243 | UINT64 PhysicalBaseAddress;\r | |
244 | } CM_ARM_GIC_ITS_INFO;\r | |
245 | \r | |
246 | /** A structure that describes the\r | |
247 | Serial Port information for the Platform.\r | |
c606f472 SM |
248 | \r |
249 | ID: EArmObjSerialConsolePortInfo or\r | |
250 | EArmObjSerialDebugPortInfo\r | |
26147c77 SM |
251 | */\r |
252 | typedef struct CmArmSerialPortInfo {\r | |
253 | /// The physical base address for the serial port\r | |
254 | UINT64 BaseAddress;\r | |
255 | \r | |
256 | /// The serial port interrupt\r | |
257 | UINT32 Interrupt;\r | |
258 | \r | |
259 | /// The serial port baud rate\r | |
260 | UINT64 BaudRate;\r | |
261 | \r | |
262 | /// The serial port clock\r | |
263 | UINT32 Clock;\r | |
264 | \r | |
265 | /// Serial Port subtype\r | |
266 | UINT16 PortSubtype;\r | |
267 | } CM_ARM_SERIAL_PORT_INFO;\r | |
268 | \r | |
269 | /** A structure that describes the\r | |
270 | Generic Timer information for the Platform.\r | |
c606f472 SM |
271 | \r |
272 | ID: EArmObjGenericTimerInfo\r | |
26147c77 SM |
273 | */\r |
274 | typedef struct CmArmGenericTimerInfo {\r | |
275 | /// The physical base address for the counter control frame\r | |
276 | UINT64 CounterControlBaseAddress;\r | |
277 | \r | |
278 | /// The physical base address for the counter read frame\r | |
279 | UINT64 CounterReadBaseAddress;\r | |
280 | \r | |
281 | /// The secure PL1 timer interrupt\r | |
282 | UINT32 SecurePL1TimerGSIV;\r | |
283 | \r | |
284 | /// The secure PL1 timer flags\r | |
285 | UINT32 SecurePL1TimerFlags;\r | |
286 | \r | |
287 | /// The non-secure PL1 timer interrupt\r | |
288 | UINT32 NonSecurePL1TimerGSIV;\r | |
289 | \r | |
290 | /// The non-secure PL1 timer flags\r | |
291 | UINT32 NonSecurePL1TimerFlags;\r | |
292 | \r | |
293 | /// The virtual timer interrupt\r | |
294 | UINT32 VirtualTimerGSIV;\r | |
295 | \r | |
296 | /// The virtual timer flags\r | |
297 | UINT32 VirtualTimerFlags;\r | |
298 | \r | |
299 | /// The non-secure PL2 timer interrupt\r | |
300 | UINT32 NonSecurePL2TimerGSIV;\r | |
301 | \r | |
302 | /// The non-secure PL2 timer flags\r | |
303 | UINT32 NonSecurePL2TimerFlags;\r | |
e8015f2f PG |
304 | \r |
305 | /// GSIV for the virtual EL2 timer\r | |
306 | UINT32 VirtualPL2TimerGSIV;\r | |
307 | \r | |
308 | /// Flags for the virtual EL2 timer\r | |
309 | UINT32 VirtualPL2TimerFlags;\r | |
26147c77 SM |
310 | } CM_ARM_GENERIC_TIMER_INFO;\r |
311 | \r | |
312 | /** A structure that describes the\r | |
313 | Platform Generic Block Timer Frame information for the Platform.\r | |
c606f472 SM |
314 | \r |
315 | ID: EArmObjGTBlockTimerFrameInfo\r | |
26147c77 SM |
316 | */\r |
317 | typedef struct CmArmGTBlockTimerFrameInfo {\r | |
318 | /// The Generic Timer frame number\r | |
319 | UINT8 FrameNumber;\r | |
320 | \r | |
321 | /// The physical base address for the CntBase block\r | |
322 | UINT64 PhysicalAddressCntBase;\r | |
323 | \r | |
324 | /// The physical base address for the CntEL0Base block\r | |
325 | UINT64 PhysicalAddressCntEL0Base;\r | |
326 | \r | |
327 | /// The physical timer interrupt\r | |
328 | UINT32 PhysicalTimerGSIV;\r | |
329 | \r | |
330 | /** The physical timer flags as described by the GT Block\r | |
331 | Timer frame Structure in the ACPI Specification.\r | |
332 | */\r | |
333 | UINT32 PhysicalTimerFlags;\r | |
334 | \r | |
335 | /// The virtual timer interrupt\r | |
336 | UINT32 VirtualTimerGSIV;\r | |
337 | \r | |
338 | /** The virtual timer flags as described by the GT Block\r | |
339 | Timer frame Structure in the ACPI Specification.\r | |
340 | */\r | |
341 | UINT32 VirtualTimerFlags;\r | |
342 | \r | |
343 | /** The common timer flags as described by the GT Block\r | |
344 | Timer frame Structure in the ACPI Specification.\r | |
345 | */\r | |
346 | UINT32 CommonFlags;\r | |
347 | } CM_ARM_GTBLOCK_TIMER_FRAME_INFO;\r | |
348 | \r | |
349 | /** A structure that describes the\r | |
350 | Platform Generic Block Timer information for the Platform.\r | |
c606f472 SM |
351 | \r |
352 | ID: EArmObjPlatformGTBlockInfo\r | |
26147c77 SM |
353 | */\r |
354 | typedef struct CmArmGTBlockInfo {\r | |
355 | /// The physical base address for the GT Block Timer structure\r | |
356 | UINT64 GTBlockPhysicalAddress;\r | |
357 | \r | |
358 | /// The number of timer frames implemented in the GT Block\r | |
359 | UINT32 GTBlockTimerFrameCount;\r | |
360 | \r | |
361 | /// Reference token for the GT Block timer frame list\r | |
362 | CM_OBJECT_TOKEN GTBlockTimerFrameToken;\r | |
363 | } CM_ARM_GTBLOCK_INFO;\r | |
364 | \r | |
365 | /** A structure that describes the\r | |
366 | SBSA Generic Watchdog information for the Platform.\r | |
c606f472 SM |
367 | \r |
368 | ID: EArmObjPlatformGenericWatchdogInfo\r | |
26147c77 SM |
369 | */\r |
370 | typedef struct CmArmGenericWatchdogInfo {\r | |
371 | /// The physical base address of the SBSA Watchdog control frame\r | |
372 | UINT64 ControlFrameAddress;\r | |
373 | \r | |
374 | /// The physical base address of the SBSA Watchdog refresh frame\r | |
375 | UINT64 RefreshFrameAddress;\r | |
376 | \r | |
377 | /// The watchdog interrupt\r | |
378 | UINT32 TimerGSIV;\r | |
379 | \r | |
380 | /** The flags for the watchdog as described by the SBSA watchdog\r | |
381 | structure in the ACPI specification.\r | |
382 | */\r | |
383 | UINT32 Flags;\r | |
384 | } CM_ARM_GENERIC_WATCHDOG_INFO;\r | |
385 | \r | |
386 | /** A structure that describes the\r | |
387 | PCI Configuration Space information for the Platform.\r | |
c606f472 SM |
388 | \r |
389 | ID: EArmObjPciConfigSpaceInfo\r | |
26147c77 SM |
390 | */\r |
391 | typedef struct CmArmPciConfigSpaceInfo {\r | |
392 | /// The physical base address for the PCI segment\r | |
393 | UINT64 BaseAddress;\r | |
394 | \r | |
395 | /// The PCI segment group number\r | |
396 | UINT16 PciSegmentGroupNumber;\r | |
397 | \r | |
398 | /// The start bus number\r | |
399 | UINT8 StartBusNumber;\r | |
400 | \r | |
401 | /// The end bus number\r | |
402 | UINT8 EndBusNumber;\r | |
403 | } CM_ARM_PCI_CONFIG_SPACE_INFO;\r | |
404 | \r | |
405 | /** A structure that describes the\r | |
406 | Hypervisor Vendor ID information for the Platform.\r | |
c606f472 SM |
407 | \r |
408 | ID: EArmObjHypervisorVendorIdentity\r | |
26147c77 SM |
409 | */\r |
410 | typedef struct CmArmHypervisorVendorId {\r | |
411 | /// The hypervisor Vendor ID\r | |
412 | UINT64 HypervisorVendorId;\r | |
413 | } CM_ARM_HYPERVISOR_VENDOR_ID;\r | |
414 | \r | |
415 | /** A structure that describes the\r | |
416 | Fixed feature flags for the Platform.\r | |
c606f472 SM |
417 | \r |
418 | ID: EArmObjFixedFeatureFlags\r | |
26147c77 SM |
419 | */\r |
420 | typedef struct CmArmFixedFeatureFlags {\r | |
421 | /// The Fixed feature flags\r | |
422 | UINT32 Flags;\r | |
423 | } CM_ARM_FIXED_FEATURE_FLAGS;\r | |
424 | \r | |
425 | /** A structure that describes the\r | |
426 | ITS Group node for the Platform.\r | |
c606f472 SM |
427 | \r |
428 | ID: EArmObjItsGroup\r | |
26147c77 SM |
429 | */\r |
430 | typedef struct CmArmItsGroupNode {\r | |
c606f472 | 431 | /// An unique token used to identify this object\r |
26147c77 SM |
432 | CM_OBJECT_TOKEN Token;\r |
433 | /// The number of ITS identifiers in the ITS node\r | |
434 | UINT32 ItsIdCount;\r | |
435 | /// Reference token for the ITS identifier array\r | |
436 | CM_OBJECT_TOKEN ItsIdToken;\r | |
437 | } CM_ARM_ITS_GROUP_NODE;\r | |
438 | \r | |
439 | /** A structure that describes the\r | |
440 | GIC ITS Identifiers for an ITS Group node.\r | |
c606f472 SM |
441 | \r |
442 | ID: EArmObjGicItsIdentifierArray\r | |
26147c77 SM |
443 | */\r |
444 | typedef struct CmArmGicItsIdentifier {\r | |
445 | /// The ITS Identifier\r | |
446 | UINT32 ItsId;\r | |
447 | } CM_ARM_ITS_IDENTIFIER;\r | |
448 | \r | |
449 | /** A structure that describes the\r | |
450 | Named component node for the Platform.\r | |
c606f472 SM |
451 | \r |
452 | ID: EArmObjNamedComponent\r | |
26147c77 SM |
453 | */\r |
454 | typedef struct CmArmNamedComponentNode {\r | |
c606f472 | 455 | /// An unique token used to identify this object\r |
26147c77 SM |
456 | CM_OBJECT_TOKEN Token;\r |
457 | /// Number of ID mappings\r | |
458 | UINT32 IdMappingCount;\r | |
459 | /// Reference token for the ID mapping array\r | |
460 | CM_OBJECT_TOKEN IdMappingToken;\r | |
461 | \r | |
462 | /// Flags for the named component\r | |
463 | UINT32 Flags;\r | |
464 | \r | |
465 | /// Memory access properties : Cache coherent attributes\r | |
466 | UINT32 CacheCoherent;\r | |
467 | /// Memory access properties : Allocation hints\r | |
468 | UINT8 AllocationHints;\r | |
469 | /// Memory access properties : Memory access flags\r | |
470 | UINT8 MemoryAccessFlags;\r | |
471 | \r | |
472 | /// Memory access properties : Address size limit\r | |
473 | UINT8 AddressSizeLimit;\r | |
474 | /** ASCII Null terminated string with the full path to\r | |
475 | the entry in the namespace for this object.\r | |
476 | */\r | |
477 | CHAR8* ObjectName;\r | |
478 | } CM_ARM_NAMED_COMPONENT_NODE;\r | |
479 | \r | |
480 | /** A structure that describes the\r | |
481 | Root complex node for the Platform.\r | |
c606f472 SM |
482 | \r |
483 | ID: EArmObjRootComplex\r | |
26147c77 SM |
484 | */\r |
485 | typedef struct CmArmRootComplexNode {\r | |
c606f472 | 486 | /// An unique token used to identify this object\r |
26147c77 SM |
487 | CM_OBJECT_TOKEN Token;\r |
488 | /// Number of ID mappings\r | |
489 | UINT32 IdMappingCount;\r | |
490 | /// Reference token for the ID mapping array\r | |
491 | CM_OBJECT_TOKEN IdMappingToken;\r | |
492 | \r | |
493 | /// Memory access properties : Cache coherent attributes\r | |
494 | UINT32 CacheCoherent;\r | |
495 | /// Memory access properties : Allocation hints\r | |
496 | UINT8 AllocationHints;\r | |
497 | /// Memory access properties : Memory access flags\r | |
498 | UINT8 MemoryAccessFlags;\r | |
499 | \r | |
500 | /// ATS attributes\r | |
501 | UINT32 AtsAttribute;\r | |
502 | /// PCI segment number\r | |
503 | UINT32 PciSegmentNumber;\r | |
504 | /// Memory address size limit\r | |
505 | UINT8 MemoryAddressSize;\r | |
506 | } CM_ARM_ROOT_COMPLEX_NODE;\r | |
507 | \r | |
508 | /** A structure that describes the\r | |
509 | SMMUv1 or SMMUv2 node for the Platform.\r | |
c606f472 SM |
510 | \r |
511 | ID: EArmObjSmmuV1SmmuV2\r | |
26147c77 SM |
512 | */\r |
513 | typedef struct CmArmSmmuV1SmmuV2Node {\r | |
c606f472 | 514 | /// An unique token used to identify this object\r |
26147c77 SM |
515 | CM_OBJECT_TOKEN Token;\r |
516 | /// Number of ID mappings\r | |
517 | UINT32 IdMappingCount;\r | |
518 | /// Reference token for the ID mapping array\r | |
519 | CM_OBJECT_TOKEN IdMappingToken;\r | |
520 | \r | |
521 | /// SMMU Base Address\r | |
522 | UINT64 BaseAddress;\r | |
523 | /// Length of the memory range covered by the SMMU\r | |
524 | UINT64 Span;\r | |
525 | /// SMMU Model\r | |
526 | UINT32 Model;\r | |
527 | /// SMMU flags\r | |
528 | UINT32 Flags;\r | |
529 | \r | |
530 | /// Number of context interrupts\r | |
531 | UINT32 ContextInterruptCount;\r | |
532 | /// Reference token for the context interrupt array\r | |
533 | CM_OBJECT_TOKEN ContextInterruptToken;\r | |
534 | \r | |
535 | /// Number of PMU interrupts\r | |
536 | UINT32 PmuInterruptCount;\r | |
537 | /// Reference token for the PMU interrupt array\r | |
538 | CM_OBJECT_TOKEN PmuInterruptToken;\r | |
539 | \r | |
540 | /// GSIV of the SMMU_NSgIrpt interrupt\r | |
541 | UINT32 SMMU_NSgIrpt;\r | |
542 | /// SMMU_NSgIrpt interrupt flags\r | |
543 | UINT32 SMMU_NSgIrptFlags;\r | |
544 | /// GSIV of the SMMU_NSgCfgIrpt interrupt\r | |
545 | UINT32 SMMU_NSgCfgIrpt;\r | |
546 | /// SMMU_NSgCfgIrpt interrupt flags\r | |
547 | UINT32 SMMU_NSgCfgIrptFlags;\r | |
548 | } CM_ARM_SMMUV1_SMMUV2_NODE;\r | |
549 | \r | |
550 | /** A structure that describes the\r | |
551 | SMMUv3 node for the Platform.\r | |
c606f472 SM |
552 | \r |
553 | ID: EArmObjSmmuV3\r | |
26147c77 SM |
554 | */\r |
555 | typedef struct CmArmSmmuV3Node {\r | |
c606f472 | 556 | /// An unique token used to identify this object\r |
26147c77 SM |
557 | CM_OBJECT_TOKEN Token;\r |
558 | /// Number of ID mappings\r | |
559 | UINT32 IdMappingCount;\r | |
560 | /// Reference token for the ID mapping array\r | |
561 | CM_OBJECT_TOKEN IdMappingToken;\r | |
562 | \r | |
563 | /// SMMU Base Address\r | |
564 | UINT64 BaseAddress;\r | |
565 | /// SMMU flags\r | |
566 | UINT32 Flags;\r | |
567 | /// VATOS address\r | |
568 | UINT64 VatosAddress;\r | |
569 | /// Model\r | |
570 | UINT32 Model;\r | |
571 | /// GSIV of the Event interrupt if SPI based\r | |
572 | UINT32 EventInterrupt;\r | |
573 | /// PRI Interrupt if SPI based\r | |
574 | UINT32 PriInterrupt;\r | |
575 | /// GERR interrupt if GSIV based\r | |
576 | UINT32 GerrInterrupt;\r | |
577 | /// Sync interrupt if GSIV based\r | |
578 | UINT32 SyncInterrupt;\r | |
579 | \r | |
580 | /// Proximity domain flag\r | |
581 | UINT32 ProximityDomain;\r | |
582 | /// Index into the array of ID mapping\r | |
583 | UINT32 DeviceIdMappingIndex;\r | |
584 | } CM_ARM_SMMUV3_NODE;\r | |
585 | \r | |
586 | /** A structure that describes the\r | |
587 | PMCG node for the Platform.\r | |
c606f472 SM |
588 | \r |
589 | ID: EArmObjPmcg\r | |
26147c77 SM |
590 | */\r |
591 | typedef struct CmArmPmcgNode {\r | |
c606f472 | 592 | /// An unique token used to identify this object\r |
26147c77 SM |
593 | CM_OBJECT_TOKEN Token;\r |
594 | /// Number of ID mappings\r | |
595 | UINT32 IdMappingCount;\r | |
596 | /// Reference token for the ID mapping array\r | |
597 | CM_OBJECT_TOKEN IdMappingToken;\r | |
598 | \r | |
599 | /// Base Address for performance monitor counter group\r | |
600 | UINT64 BaseAddress;\r | |
601 | /// GSIV for the Overflow interrupt\r | |
602 | UINT32 OverflowInterrupt;\r | |
603 | /// Page 1 Base address\r | |
604 | UINT64 Page1BaseAddress;\r | |
605 | \r | |
606 | /// Reference token for the IORT node associated with this node\r | |
607 | CM_OBJECT_TOKEN ReferenceToken;\r | |
608 | } CM_ARM_PMCG_NODE;\r | |
609 | \r | |
610 | /** A structure that describes the\r | |
611 | ID Mappings for the Platform.\r | |
c606f472 SM |
612 | \r |
613 | ID: EArmObjIdMappingArray\r | |
26147c77 SM |
614 | */\r |
615 | typedef struct CmArmIdMapping {\r | |
616 | /// Input base\r | |
617 | UINT32 InputBase;\r | |
618 | /// Number of input IDs\r | |
619 | UINT32 NumIds;\r | |
620 | /// Output Base\r | |
621 | UINT32 OutputBase;\r | |
622 | /// Reference token for the output node\r | |
623 | CM_OBJECT_TOKEN OutputReferenceToken;\r | |
624 | /// Flags\r | |
625 | UINT32 Flags;\r | |
626 | } CM_ARM_ID_MAPPING;\r | |
627 | \r | |
628 | /** A structure that describes the\r | |
629 | SMMU interrupts for the Platform.\r | |
c606f472 SM |
630 | \r |
631 | ID: EArmObjSmmuInterruptArray\r | |
26147c77 SM |
632 | */\r |
633 | typedef struct CmArmSmmuInterrupt {\r | |
634 | /// Interrupt number\r | |
635 | UINT32 Interrupt;\r | |
636 | \r | |
637 | /// Flags\r | |
638 | UINT32 Flags;\r | |
639 | } CM_ARM_SMMU_INTERRUPT;\r | |
640 | \r | |
77db1156 KK |
641 | /** A structure that describes the Processor Hierarchy Node (Type 0) in PPTT\r |
642 | \r | |
643 | ID: EArmObjProcHierarchyInfo\r | |
644 | */\r | |
645 | typedef struct CmArmProcHierarchyInfo {\r | |
646 | /// A unique token used to identify this object\r | |
647 | CM_OBJECT_TOKEN Token;\r | |
648 | /// Processor structure flags (ACPI 6.3 - January 2019, PPTT, Table 5-155)\r | |
649 | UINT32 Flags;\r | |
650 | /// Token for the parent CM_ARM_PROC_HIERARCHY_INFO object in the processor\r | |
651 | /// topology. A value of CM_NULL_TOKEN means this node has no parent.\r | |
652 | CM_OBJECT_TOKEN ParentToken;\r | |
653 | /// Token of the associated CM_ARM_GICC_INFO object which has the\r | |
654 | /// corresponding ACPI Processor ID. A value of CM_NULL_TOKEN means this\r | |
655 | /// node represents a group of associated processors and it does not have an\r | |
656 | /// associated GIC CPU interface.\r | |
657 | CM_OBJECT_TOKEN GicCToken;\r | |
658 | /// Number of resources private to this Node\r | |
659 | UINT32 NoOfPrivateResources;\r | |
660 | /// Token of the array which contains references to the resources private to\r | |
661 | /// this CM_ARM_PROC_HIERARCHY_INFO instance. This field is ignored if\r | |
662 | /// the NoOfPrivateResources is 0, in which case it is recomended to set\r | |
663 | /// this field to CM_NULL_TOKEN.\r | |
664 | CM_OBJECT_TOKEN PrivateResourcesArrayToken;\r | |
665 | } CM_ARM_PROC_HIERARCHY_INFO;\r | |
666 | \r | |
667 | /** A structure that describes the Cache Type Structure (Type 1) in PPTT\r | |
668 | \r | |
669 | ID: EArmObjCacheInfo\r | |
670 | */\r | |
671 | typedef struct CmArmCacheInfo {\r | |
672 | /// A unique token used to identify this object\r | |
673 | CM_OBJECT_TOKEN Token;\r | |
674 | /// Reference token for the next level of cache that is private to the same\r | |
675 | /// CM_ARM_PROC_HIERARCHY_INFO instance. A value of CM_NULL_TOKEN means this\r | |
676 | /// entry represents the last cache level appropriate to the processor\r | |
677 | /// hierarchy node structures using this entry.\r | |
678 | CM_OBJECT_TOKEN NextLevelOfCacheToken;\r | |
679 | /// Size of the cache in bytes\r | |
680 | UINT32 Size;\r | |
681 | /// Number of sets in the cache\r | |
682 | UINT32 NumberOfSets;\r | |
683 | /// Integer number of ways. The maximum associativity supported by\r | |
684 | /// ACPI Cache type structure is limited to MAX_UINT8. However,\r | |
685 | /// the maximum number of ways supported by the architecture is\r | |
686 | /// PPTT_ARM_CCIDX_CACHE_ASSOCIATIVITY_MAX. Therfore this field\r | |
687 | /// is 32-bit wide.\r | |
688 | UINT32 Associativity;\r | |
689 | /// Cache attributes (ACPI 6.3 - January 2019, PPTT, Table 5-156)\r | |
690 | UINT8 Attributes;\r | |
691 | /// Line size in bytes\r | |
692 | UINT16 LineSize;\r | |
693 | } CM_ARM_CACHE_INFO;\r | |
694 | \r | |
695 | /** A structure that describes the ID Structure (Type 2) in PPTT\r | |
696 | \r | |
697 | ID: EArmObjProcNodeIdInfo\r | |
698 | */\r | |
699 | typedef struct CmArmProcNodeIdInfo {\r | |
700 | /// A unique token used to identify this object\r | |
701 | CM_OBJECT_TOKEN Token;\r | |
702 | // Vendor ID (as described in ACPI ID registry)\r | |
703 | UINT32 VendorId;\r | |
704 | /// First level unique node ID\r | |
705 | UINT64 Level1Id;\r | |
706 | /// Second level unique node ID\r | |
707 | UINT64 Level2Id;\r | |
708 | /// Major revision of the node\r | |
709 | UINT16 MajorRev;\r | |
710 | /// Minor revision of the node\r | |
711 | UINT16 MinorRev;\r | |
712 | /// Spin revision of the node\r | |
713 | UINT16 SpinRev;\r | |
714 | } CM_ARM_PROC_NODE_ID_INFO;\r | |
715 | \r | |
716 | /** A structure that describes a reference to another Configuration Manager\r | |
717 | object.\r | |
718 | \r | |
719 | This is useful for creating an array of reference tokens. The framework\r | |
720 | can then query the configuration manager for these arrays using the\r | |
721 | object ID EArmObjCmRef.\r | |
722 | \r | |
723 | This can be used is to represent one-to-many relationships between objects.\r | |
724 | \r | |
725 | ID: EArmObjCmRef\r | |
726 | */\r | |
727 | typedef struct CmArmObjRef {\r | |
728 | /// Token of the CM object being referenced\r | |
729 | CM_OBJECT_TOKEN ReferenceToken;\r | |
730 | } CM_ARM_OBJ_REF;\r | |
731 | \r | |
26147c77 SM |
732 | #pragma pack()\r |
733 | \r | |
734 | #endif // ARM_NAMESPACE_OBJECTS_H_\r |