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26147c77 SM |
1 | /** @file\r |
2 | \r | |
bade7f42 | 3 | Copyright (c) 2017 - 2020, Arm Limited. All rights reserved.<BR>\r |
26147c77 | 4 | \r |
9cd9bdc6 | 5 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
26147c77 SM |
6 | \r |
7 | @par Glossary:\r | |
8 | - Cm or CM - Configuration Manager\r | |
9 | - Obj or OBJ - Object\r | |
10 | - Std or STD - Standard\r | |
11 | **/\r | |
12 | \r | |
13 | #ifndef ARM_NAMESPACE_OBJECTS_H_\r | |
14 | #define ARM_NAMESPACE_OBJECTS_H_\r | |
15 | \r | |
16 | #include <StandardNameSpaceObjects.h>\r | |
17 | \r | |
18 | #pragma pack(1)\r | |
19 | \r | |
20 | /** The EARM_OBJECT_ID enum describes the Object IDs\r | |
21 | in the ARM Namespace\r | |
22 | */\r | |
23 | typedef enum ArmObjectID {\r | |
f413d9be SM |
24 | EArmObjReserved, ///< 0 - Reserved\r |
25 | EArmObjBootArchInfo, ///< 1 - Boot Architecture Info\r | |
26 | EArmObjCpuInfo, ///< 2 - CPU Info\r | |
27 | EArmObjPowerManagementProfileInfo, ///< 3 - Power Management Profile Info\r | |
28 | EArmObjGicCInfo, ///< 4 - GIC CPU Interface Info\r | |
29 | EArmObjGicDInfo, ///< 5 - GIC Distributor Info\r | |
30 | EArmObjGicMsiFrameInfo, ///< 6 - GIC MSI Frame Info\r | |
31 | EArmObjGicRedistributorInfo, ///< 7 - GIC Redistributor Info\r | |
32 | EArmObjGicItsInfo, ///< 8 - GIC ITS Info\r | |
33 | EArmObjSerialConsolePortInfo, ///< 9 - Serial Console Port Info\r | |
34 | EArmObjSerialDebugPortInfo, ///< 10 - Serial Debug Port Info\r | |
35 | EArmObjGenericTimerInfo, ///< 11 - Generic Timer Info\r | |
36 | EArmObjPlatformGTBlockInfo, ///< 12 - Platform GT Block Info\r | |
37 | EArmObjGTBlockTimerFrameInfo, ///< 13 - Generic Timer Block Frame Info\r | |
38 | EArmObjPlatformGenericWatchdogInfo, ///< 14 - Platform Generic Watchdog\r | |
39 | EArmObjPciConfigSpaceInfo, ///< 15 - PCI Configuration Space Info\r | |
40 | EArmObjHypervisorVendorIdentity, ///< 16 - Hypervisor Vendor Id\r | |
41 | EArmObjFixedFeatureFlags, ///< 17 - Fixed feature flags for FADT\r | |
42 | EArmObjItsGroup, ///< 18 - ITS Group\r | |
43 | EArmObjNamedComponent, ///< 19 - Named Component\r | |
44 | EArmObjRootComplex, ///< 20 - Root Complex\r | |
45 | EArmObjSmmuV1SmmuV2, ///< 21 - SMMUv1 or SMMUv2\r | |
46 | EArmObjSmmuV3, ///< 22 - SMMUv3\r | |
47 | EArmObjPmcg, ///< 23 - PMCG\r | |
48 | EArmObjGicItsIdentifierArray, ///< 24 - GIC ITS Identifier Array\r | |
49 | EArmObjIdMappingArray, ///< 25 - ID Mapping Array\r | |
50 | EArmObjSmmuInterruptArray, ///< 26 - SMMU Interrupt Array\r | |
51 | EArmObjProcHierarchyInfo, ///< 27 - Processor Hierarchy Info\r | |
52 | EArmObjCacheInfo, ///< 28 - Cache Info\r | |
53 | EArmObjProcNodeIdInfo, ///< 29 - Processor Node ID Info\r | |
54 | EArmObjCmRef, ///< 30 - CM Object Reference\r | |
55 | EArmObjMemoryAffinityInfo, ///< 31 - Memory Affinity Info\r | |
56 | EArmObjDeviceHandleAcpi, ///< 32 - Device Handle Acpi\r | |
57 | EArmObjDeviceHandlePci, ///< 33 - Device Handle Pci\r | |
58 | EArmObjGenericInitiatorAffinityInfo, ///< 34 - Generic Initiator Affinity\r | |
bade7f42 | 59 | EArmObjSerialPortInfo, ///< 35 - Generic Serial Port Info\r |
37568365 | 60 | EArmObjCmn600Info, ///< 36 - CMN-600 Info\r |
26147c77 SM |
61 | EArmObjMax\r |
62 | } EARM_OBJECT_ID;\r | |
63 | \r | |
64 | /** A structure that describes the\r | |
65 | ARM Boot Architecture flags.\r | |
c606f472 SM |
66 | \r |
67 | ID: EArmObjBootArchInfo\r | |
26147c77 SM |
68 | */\r |
69 | typedef struct CmArmBootArchInfo {\r | |
70 | /** This is the ARM_BOOT_ARCH flags field of the FADT Table\r | |
71 | described in the ACPI Table Specification.\r | |
72 | */\r | |
aa9aff2d | 73 | UINT16 BootArchFlags;\r |
26147c77 SM |
74 | } CM_ARM_BOOT_ARCH_INFO;\r |
75 | \r | |
26147c77 SM |
76 | /** A structure that describes the\r |
77 | Power Management Profile Information for the Platform.\r | |
c606f472 SM |
78 | \r |
79 | ID: EArmObjPowerManagementProfileInfo\r | |
26147c77 SM |
80 | */\r |
81 | typedef struct CmArmPowerManagementProfileInfo {\r | |
82 | /** This is the Preferred_PM_Profile field of the FADT Table\r | |
83 | described in the ACPI Specification\r | |
84 | */\r | |
85 | UINT8 PowerManagementProfile;\r | |
86 | } CM_ARM_POWER_MANAGEMENT_PROFILE_INFO;\r | |
87 | \r | |
88 | /** A structure that describes the\r | |
89 | GIC CPU Interface for the Platform.\r | |
c606f472 SM |
90 | \r |
91 | ID: EArmObjGicCInfo\r | |
26147c77 SM |
92 | */\r |
93 | typedef struct CmArmGicCInfo {\r | |
94 | /// The GIC CPU Interface number.\r | |
95 | UINT32 CPUInterfaceNumber;\r | |
96 | \r | |
97 | /** The ACPI Processor UID. This must match the\r | |
98 | _UID of the CPU Device object information described\r | |
99 | in the DSDT/SSDT for the CPU.\r | |
100 | */\r | |
101 | UINT32 AcpiProcessorUid;\r | |
102 | \r | |
103 | /** The flags field as described by the GICC structure\r | |
104 | in the ACPI Specification.\r | |
105 | */\r | |
106 | UINT32 Flags;\r | |
107 | \r | |
108 | /** The parking protocol version field as described by\r | |
109 | the GICC structure in the ACPI Specification.\r | |
110 | */\r | |
111 | UINT32 ParkingProtocolVersion;\r | |
112 | \r | |
113 | /** The Performance Interrupt field as described by\r | |
114 | the GICC structure in the ACPI Specification.\r | |
115 | */\r | |
116 | UINT32 PerformanceInterruptGsiv;\r | |
117 | \r | |
118 | /** The CPU Parked address field as described by\r | |
119 | the GICC structure in the ACPI Specification.\r | |
120 | */\r | |
121 | UINT64 ParkedAddress;\r | |
122 | \r | |
123 | /** The base address for the GIC CPU Interface\r | |
124 | as described by the GICC structure in the\r | |
125 | ACPI Specification.\r | |
126 | */\r | |
127 | UINT64 PhysicalBaseAddress;\r | |
128 | \r | |
129 | /** The base address for GICV interface\r | |
130 | as described by the GICC structure in the\r | |
131 | ACPI Specification.\r | |
132 | */\r | |
133 | UINT64 GICV;\r | |
134 | \r | |
135 | /** The base address for GICH interface\r | |
136 | as described by the GICC structure in the\r | |
137 | ACPI Specification.\r | |
138 | */\r | |
139 | UINT64 GICH;\r | |
140 | \r | |
141 | /** The GICV maintenance interrupt\r | |
142 | as described by the GICC structure in the\r | |
143 | ACPI Specification.\r | |
144 | */\r | |
145 | UINT32 VGICMaintenanceInterrupt;\r | |
146 | \r | |
147 | /** The base address for GICR interface\r | |
148 | as described by the GICC structure in the\r | |
149 | ACPI Specification.\r | |
150 | */\r | |
151 | UINT64 GICRBaseAddress;\r | |
152 | \r | |
153 | /** The MPIDR for the CPU\r | |
154 | as described by the GICC structure in the\r | |
155 | ACPI Specification.\r | |
156 | */\r | |
157 | UINT64 MPIDR;\r | |
158 | \r | |
159 | /** The Processor Power Efficiency class\r | |
160 | as described by the GICC structure in the\r | |
161 | ACPI Specification.\r | |
162 | */\r | |
163 | UINT8 ProcessorPowerEfficiencyClass;\r | |
5506701f KK |
164 | \r |
165 | /** Statistical Profiling Extension buffer overflow GSIV. Zero if\r | |
166 | unsupported by this processor. This field was introduced in\r | |
167 | ACPI 6.3 (MADT revision 5) and is therefore ignored when\r | |
168 | generating MADT revision 4 or lower.\r | |
169 | */\r | |
170 | UINT16 SpeOverflowInterrupt;\r | |
f413d9be SM |
171 | \r |
172 | /** The proximity domain to which the logical processor belongs.\r | |
173 | This field is used to populate the GICC affinity structure\r | |
174 | in the SRAT table.\r | |
175 | */\r | |
176 | UINT32 ProximityDomain;\r | |
177 | \r | |
178 | /** The clock domain to which the logical processor belongs.\r | |
179 | This field is used to populate the GICC affinity structure\r | |
180 | in the SRAT table.\r | |
181 | */\r | |
182 | UINT32 ClockDomain;\r | |
183 | \r | |
184 | /** The GICC Affinity flags field as described by the GICC Affinity structure\r | |
185 | in the SRAT table.\r | |
186 | */\r | |
187 | UINT32 AffinityFlags;\r | |
26147c77 SM |
188 | } CM_ARM_GICC_INFO;\r |
189 | \r | |
190 | /** A structure that describes the\r | |
191 | GIC Distributor information for the Platform.\r | |
c606f472 SM |
192 | \r |
193 | ID: EArmObjGicDInfo\r | |
26147c77 SM |
194 | */\r |
195 | typedef struct CmArmGicDInfo {\r | |
26147c77 SM |
196 | /// The Physical Base address for the GIC Distributor.\r |
197 | UINT64 PhysicalBaseAddress;\r | |
198 | \r | |
199 | /** The global system interrupt\r | |
200 | number where this GIC Distributor's\r | |
201 | interrupt inputs start.\r | |
202 | */\r | |
203 | UINT32 SystemVectorBase;\r | |
204 | \r | |
205 | /** The GIC version as described\r | |
206 | by the GICD structure in the\r | |
207 | ACPI Specification.\r | |
208 | */\r | |
209 | UINT8 GicVersion;\r | |
210 | } CM_ARM_GICD_INFO;\r | |
211 | \r | |
212 | /** A structure that describes the\r | |
213 | GIC MSI Frame information for the Platform.\r | |
c606f472 SM |
214 | \r |
215 | ID: EArmObjGicMsiFrameInfo\r | |
26147c77 SM |
216 | */\r |
217 | typedef struct CmArmGicMsiFrameInfo {\r | |
218 | /// The GIC MSI Frame ID\r | |
219 | UINT32 GicMsiFrameId;\r | |
220 | \r | |
221 | /// The Physical base address for the MSI Frame\r | |
222 | UINT64 PhysicalBaseAddress;\r | |
223 | \r | |
224 | /** The GIC MSI Frame flags\r | |
225 | as described by the GIC MSI frame\r | |
226 | structure in the ACPI Specification.\r | |
227 | */\r | |
228 | UINT32 Flags;\r | |
229 | \r | |
230 | /// SPI Count used by this frame\r | |
231 | UINT16 SPICount;\r | |
232 | \r | |
233 | /// SPI Base used by this frame\r | |
234 | UINT16 SPIBase;\r | |
235 | } CM_ARM_GIC_MSI_FRAME_INFO;\r | |
236 | \r | |
237 | /** A structure that describes the\r | |
238 | GIC Redistributor information for the Platform.\r | |
c606f472 SM |
239 | \r |
240 | ID: EArmObjGicRedistributorInfo\r | |
26147c77 SM |
241 | */\r |
242 | typedef struct CmArmGicRedistInfo {\r | |
243 | /** The physical address of a page range\r | |
244 | containing all GIC Redistributors.\r | |
245 | */\r | |
246 | UINT64 DiscoveryRangeBaseAddress;\r | |
247 | \r | |
248 | /// Length of the GIC Redistributor Discovery page range\r | |
249 | UINT32 DiscoveryRangeLength;\r | |
250 | } CM_ARM_GIC_REDIST_INFO;\r | |
251 | \r | |
252 | /** A structure that describes the\r | |
253 | GIC Interrupt Translation Service information for the Platform.\r | |
c606f472 SM |
254 | \r |
255 | ID: EArmObjGicItsInfo\r | |
26147c77 SM |
256 | */\r |
257 | typedef struct CmArmGicItsInfo {\r | |
258 | /// The GIC ITS ID\r | |
259 | UINT32 GicItsId;\r | |
260 | \r | |
261 | /// The physical address for the Interrupt Translation Service\r | |
262 | UINT64 PhysicalBaseAddress;\r | |
f413d9be SM |
263 | \r |
264 | /** The proximity domain to which the logical processor belongs.\r | |
265 | This field is used to populate the GIC ITS affinity structure\r | |
266 | in the SRAT table.\r | |
267 | */\r | |
268 | UINT32 ProximityDomain;\r | |
26147c77 SM |
269 | } CM_ARM_GIC_ITS_INFO;\r |
270 | \r | |
271 | /** A structure that describes the\r | |
272 | Serial Port information for the Platform.\r | |
c606f472 SM |
273 | \r |
274 | ID: EArmObjSerialConsolePortInfo or\r | |
bade7f42 PG |
275 | EArmObjSerialDebugPortInfo or\r |
276 | EArmObjSerialPortInfo\r | |
26147c77 SM |
277 | */\r |
278 | typedef struct CmArmSerialPortInfo {\r | |
279 | /// The physical base address for the serial port\r | |
280 | UINT64 BaseAddress;\r | |
281 | \r | |
282 | /// The serial port interrupt\r | |
283 | UINT32 Interrupt;\r | |
284 | \r | |
285 | /// The serial port baud rate\r | |
286 | UINT64 BaudRate;\r | |
287 | \r | |
288 | /// The serial port clock\r | |
289 | UINT32 Clock;\r | |
290 | \r | |
291 | /// Serial Port subtype\r | |
292 | UINT16 PortSubtype;\r | |
bade7f42 PG |
293 | \r |
294 | /// The Base address length\r | |
295 | UINT64 BaseAddressLength;\r | |
26147c77 SM |
296 | } CM_ARM_SERIAL_PORT_INFO;\r |
297 | \r | |
298 | /** A structure that describes the\r | |
299 | Generic Timer information for the Platform.\r | |
c606f472 SM |
300 | \r |
301 | ID: EArmObjGenericTimerInfo\r | |
26147c77 SM |
302 | */\r |
303 | typedef struct CmArmGenericTimerInfo {\r | |
304 | /// The physical base address for the counter control frame\r | |
305 | UINT64 CounterControlBaseAddress;\r | |
306 | \r | |
307 | /// The physical base address for the counter read frame\r | |
308 | UINT64 CounterReadBaseAddress;\r | |
309 | \r | |
310 | /// The secure PL1 timer interrupt\r | |
311 | UINT32 SecurePL1TimerGSIV;\r | |
312 | \r | |
313 | /// The secure PL1 timer flags\r | |
314 | UINT32 SecurePL1TimerFlags;\r | |
315 | \r | |
316 | /// The non-secure PL1 timer interrupt\r | |
317 | UINT32 NonSecurePL1TimerGSIV;\r | |
318 | \r | |
319 | /// The non-secure PL1 timer flags\r | |
320 | UINT32 NonSecurePL1TimerFlags;\r | |
321 | \r | |
322 | /// The virtual timer interrupt\r | |
323 | UINT32 VirtualTimerGSIV;\r | |
324 | \r | |
325 | /// The virtual timer flags\r | |
326 | UINT32 VirtualTimerFlags;\r | |
327 | \r | |
328 | /// The non-secure PL2 timer interrupt\r | |
329 | UINT32 NonSecurePL2TimerGSIV;\r | |
330 | \r | |
331 | /// The non-secure PL2 timer flags\r | |
332 | UINT32 NonSecurePL2TimerFlags;\r | |
e8015f2f PG |
333 | \r |
334 | /// GSIV for the virtual EL2 timer\r | |
335 | UINT32 VirtualPL2TimerGSIV;\r | |
336 | \r | |
337 | /// Flags for the virtual EL2 timer\r | |
338 | UINT32 VirtualPL2TimerFlags;\r | |
26147c77 SM |
339 | } CM_ARM_GENERIC_TIMER_INFO;\r |
340 | \r | |
341 | /** A structure that describes the\r | |
342 | Platform Generic Block Timer Frame information for the Platform.\r | |
c606f472 SM |
343 | \r |
344 | ID: EArmObjGTBlockTimerFrameInfo\r | |
26147c77 SM |
345 | */\r |
346 | typedef struct CmArmGTBlockTimerFrameInfo {\r | |
347 | /// The Generic Timer frame number\r | |
348 | UINT8 FrameNumber;\r | |
349 | \r | |
350 | /// The physical base address for the CntBase block\r | |
351 | UINT64 PhysicalAddressCntBase;\r | |
352 | \r | |
353 | /// The physical base address for the CntEL0Base block\r | |
354 | UINT64 PhysicalAddressCntEL0Base;\r | |
355 | \r | |
356 | /// The physical timer interrupt\r | |
357 | UINT32 PhysicalTimerGSIV;\r | |
358 | \r | |
359 | /** The physical timer flags as described by the GT Block\r | |
360 | Timer frame Structure in the ACPI Specification.\r | |
361 | */\r | |
362 | UINT32 PhysicalTimerFlags;\r | |
363 | \r | |
364 | /// The virtual timer interrupt\r | |
365 | UINT32 VirtualTimerGSIV;\r | |
366 | \r | |
367 | /** The virtual timer flags as described by the GT Block\r | |
368 | Timer frame Structure in the ACPI Specification.\r | |
369 | */\r | |
370 | UINT32 VirtualTimerFlags;\r | |
371 | \r | |
372 | /** The common timer flags as described by the GT Block\r | |
373 | Timer frame Structure in the ACPI Specification.\r | |
374 | */\r | |
375 | UINT32 CommonFlags;\r | |
376 | } CM_ARM_GTBLOCK_TIMER_FRAME_INFO;\r | |
377 | \r | |
378 | /** A structure that describes the\r | |
379 | Platform Generic Block Timer information for the Platform.\r | |
c606f472 SM |
380 | \r |
381 | ID: EArmObjPlatformGTBlockInfo\r | |
26147c77 SM |
382 | */\r |
383 | typedef struct CmArmGTBlockInfo {\r | |
384 | /// The physical base address for the GT Block Timer structure\r | |
385 | UINT64 GTBlockPhysicalAddress;\r | |
386 | \r | |
387 | /// The number of timer frames implemented in the GT Block\r | |
388 | UINT32 GTBlockTimerFrameCount;\r | |
389 | \r | |
390 | /// Reference token for the GT Block timer frame list\r | |
391 | CM_OBJECT_TOKEN GTBlockTimerFrameToken;\r | |
392 | } CM_ARM_GTBLOCK_INFO;\r | |
393 | \r | |
394 | /** A structure that describes the\r | |
395 | SBSA Generic Watchdog information for the Platform.\r | |
c606f472 SM |
396 | \r |
397 | ID: EArmObjPlatformGenericWatchdogInfo\r | |
26147c77 SM |
398 | */\r |
399 | typedef struct CmArmGenericWatchdogInfo {\r | |
400 | /// The physical base address of the SBSA Watchdog control frame\r | |
401 | UINT64 ControlFrameAddress;\r | |
402 | \r | |
403 | /// The physical base address of the SBSA Watchdog refresh frame\r | |
404 | UINT64 RefreshFrameAddress;\r | |
405 | \r | |
406 | /// The watchdog interrupt\r | |
407 | UINT32 TimerGSIV;\r | |
408 | \r | |
409 | /** The flags for the watchdog as described by the SBSA watchdog\r | |
410 | structure in the ACPI specification.\r | |
411 | */\r | |
412 | UINT32 Flags;\r | |
413 | } CM_ARM_GENERIC_WATCHDOG_INFO;\r | |
414 | \r | |
415 | /** A structure that describes the\r | |
416 | PCI Configuration Space information for the Platform.\r | |
c606f472 SM |
417 | \r |
418 | ID: EArmObjPciConfigSpaceInfo\r | |
26147c77 SM |
419 | */\r |
420 | typedef struct CmArmPciConfigSpaceInfo {\r | |
421 | /// The physical base address for the PCI segment\r | |
422 | UINT64 BaseAddress;\r | |
423 | \r | |
424 | /// The PCI segment group number\r | |
425 | UINT16 PciSegmentGroupNumber;\r | |
426 | \r | |
427 | /// The start bus number\r | |
428 | UINT8 StartBusNumber;\r | |
429 | \r | |
430 | /// The end bus number\r | |
431 | UINT8 EndBusNumber;\r | |
432 | } CM_ARM_PCI_CONFIG_SPACE_INFO;\r | |
433 | \r | |
434 | /** A structure that describes the\r | |
435 | Hypervisor Vendor ID information for the Platform.\r | |
c606f472 SM |
436 | \r |
437 | ID: EArmObjHypervisorVendorIdentity\r | |
26147c77 SM |
438 | */\r |
439 | typedef struct CmArmHypervisorVendorId {\r | |
440 | /// The hypervisor Vendor ID\r | |
441 | UINT64 HypervisorVendorId;\r | |
442 | } CM_ARM_HYPERVISOR_VENDOR_ID;\r | |
443 | \r | |
444 | /** A structure that describes the\r | |
445 | Fixed feature flags for the Platform.\r | |
c606f472 SM |
446 | \r |
447 | ID: EArmObjFixedFeatureFlags\r | |
26147c77 SM |
448 | */\r |
449 | typedef struct CmArmFixedFeatureFlags {\r | |
450 | /// The Fixed feature flags\r | |
451 | UINT32 Flags;\r | |
452 | } CM_ARM_FIXED_FEATURE_FLAGS;\r | |
453 | \r | |
454 | /** A structure that describes the\r | |
455 | ITS Group node for the Platform.\r | |
c606f472 SM |
456 | \r |
457 | ID: EArmObjItsGroup\r | |
26147c77 SM |
458 | */\r |
459 | typedef struct CmArmItsGroupNode {\r | |
c606f472 | 460 | /// An unique token used to identify this object\r |
26147c77 SM |
461 | CM_OBJECT_TOKEN Token;\r |
462 | /// The number of ITS identifiers in the ITS node\r | |
463 | UINT32 ItsIdCount;\r | |
464 | /// Reference token for the ITS identifier array\r | |
465 | CM_OBJECT_TOKEN ItsIdToken;\r | |
466 | } CM_ARM_ITS_GROUP_NODE;\r | |
467 | \r | |
468 | /** A structure that describes the\r | |
469 | GIC ITS Identifiers for an ITS Group node.\r | |
c606f472 SM |
470 | \r |
471 | ID: EArmObjGicItsIdentifierArray\r | |
26147c77 SM |
472 | */\r |
473 | typedef struct CmArmGicItsIdentifier {\r | |
474 | /// The ITS Identifier\r | |
475 | UINT32 ItsId;\r | |
476 | } CM_ARM_ITS_IDENTIFIER;\r | |
477 | \r | |
478 | /** A structure that describes the\r | |
479 | Named component node for the Platform.\r | |
c606f472 SM |
480 | \r |
481 | ID: EArmObjNamedComponent\r | |
26147c77 SM |
482 | */\r |
483 | typedef struct CmArmNamedComponentNode {\r | |
c606f472 | 484 | /// An unique token used to identify this object\r |
26147c77 SM |
485 | CM_OBJECT_TOKEN Token;\r |
486 | /// Number of ID mappings\r | |
487 | UINT32 IdMappingCount;\r | |
488 | /// Reference token for the ID mapping array\r | |
489 | CM_OBJECT_TOKEN IdMappingToken;\r | |
490 | \r | |
491 | /// Flags for the named component\r | |
492 | UINT32 Flags;\r | |
493 | \r | |
494 | /// Memory access properties : Cache coherent attributes\r | |
495 | UINT32 CacheCoherent;\r | |
496 | /// Memory access properties : Allocation hints\r | |
497 | UINT8 AllocationHints;\r | |
498 | /// Memory access properties : Memory access flags\r | |
499 | UINT8 MemoryAccessFlags;\r | |
500 | \r | |
501 | /// Memory access properties : Address size limit\r | |
502 | UINT8 AddressSizeLimit;\r | |
503 | /** ASCII Null terminated string with the full path to\r | |
504 | the entry in the namespace for this object.\r | |
505 | */\r | |
506 | CHAR8* ObjectName;\r | |
507 | } CM_ARM_NAMED_COMPONENT_NODE;\r | |
508 | \r | |
509 | /** A structure that describes the\r | |
510 | Root complex node for the Platform.\r | |
c606f472 SM |
511 | \r |
512 | ID: EArmObjRootComplex\r | |
26147c77 SM |
513 | */\r |
514 | typedef struct CmArmRootComplexNode {\r | |
c606f472 | 515 | /// An unique token used to identify this object\r |
26147c77 SM |
516 | CM_OBJECT_TOKEN Token;\r |
517 | /// Number of ID mappings\r | |
518 | UINT32 IdMappingCount;\r | |
519 | /// Reference token for the ID mapping array\r | |
520 | CM_OBJECT_TOKEN IdMappingToken;\r | |
521 | \r | |
522 | /// Memory access properties : Cache coherent attributes\r | |
523 | UINT32 CacheCoherent;\r | |
524 | /// Memory access properties : Allocation hints\r | |
525 | UINT8 AllocationHints;\r | |
526 | /// Memory access properties : Memory access flags\r | |
527 | UINT8 MemoryAccessFlags;\r | |
528 | \r | |
529 | /// ATS attributes\r | |
530 | UINT32 AtsAttribute;\r | |
531 | /// PCI segment number\r | |
532 | UINT32 PciSegmentNumber;\r | |
533 | /// Memory address size limit\r | |
534 | UINT8 MemoryAddressSize;\r | |
535 | } CM_ARM_ROOT_COMPLEX_NODE;\r | |
536 | \r | |
537 | /** A structure that describes the\r | |
538 | SMMUv1 or SMMUv2 node for the Platform.\r | |
c606f472 SM |
539 | \r |
540 | ID: EArmObjSmmuV1SmmuV2\r | |
26147c77 SM |
541 | */\r |
542 | typedef struct CmArmSmmuV1SmmuV2Node {\r | |
c606f472 | 543 | /// An unique token used to identify this object\r |
26147c77 SM |
544 | CM_OBJECT_TOKEN Token;\r |
545 | /// Number of ID mappings\r | |
546 | UINT32 IdMappingCount;\r | |
547 | /// Reference token for the ID mapping array\r | |
548 | CM_OBJECT_TOKEN IdMappingToken;\r | |
549 | \r | |
550 | /// SMMU Base Address\r | |
551 | UINT64 BaseAddress;\r | |
552 | /// Length of the memory range covered by the SMMU\r | |
553 | UINT64 Span;\r | |
554 | /// SMMU Model\r | |
555 | UINT32 Model;\r | |
556 | /// SMMU flags\r | |
557 | UINT32 Flags;\r | |
558 | \r | |
559 | /// Number of context interrupts\r | |
560 | UINT32 ContextInterruptCount;\r | |
561 | /// Reference token for the context interrupt array\r | |
562 | CM_OBJECT_TOKEN ContextInterruptToken;\r | |
563 | \r | |
564 | /// Number of PMU interrupts\r | |
565 | UINT32 PmuInterruptCount;\r | |
566 | /// Reference token for the PMU interrupt array\r | |
567 | CM_OBJECT_TOKEN PmuInterruptToken;\r | |
568 | \r | |
569 | /// GSIV of the SMMU_NSgIrpt interrupt\r | |
570 | UINT32 SMMU_NSgIrpt;\r | |
571 | /// SMMU_NSgIrpt interrupt flags\r | |
572 | UINT32 SMMU_NSgIrptFlags;\r | |
573 | /// GSIV of the SMMU_NSgCfgIrpt interrupt\r | |
574 | UINT32 SMMU_NSgCfgIrpt;\r | |
575 | /// SMMU_NSgCfgIrpt interrupt flags\r | |
576 | UINT32 SMMU_NSgCfgIrptFlags;\r | |
577 | } CM_ARM_SMMUV1_SMMUV2_NODE;\r | |
578 | \r | |
579 | /** A structure that describes the\r | |
580 | SMMUv3 node for the Platform.\r | |
c606f472 SM |
581 | \r |
582 | ID: EArmObjSmmuV3\r | |
26147c77 SM |
583 | */\r |
584 | typedef struct CmArmSmmuV3Node {\r | |
c606f472 | 585 | /// An unique token used to identify this object\r |
26147c77 SM |
586 | CM_OBJECT_TOKEN Token;\r |
587 | /// Number of ID mappings\r | |
588 | UINT32 IdMappingCount;\r | |
589 | /// Reference token for the ID mapping array\r | |
590 | CM_OBJECT_TOKEN IdMappingToken;\r | |
591 | \r | |
592 | /// SMMU Base Address\r | |
593 | UINT64 BaseAddress;\r | |
594 | /// SMMU flags\r | |
595 | UINT32 Flags;\r | |
596 | /// VATOS address\r | |
597 | UINT64 VatosAddress;\r | |
598 | /// Model\r | |
599 | UINT32 Model;\r | |
600 | /// GSIV of the Event interrupt if SPI based\r | |
601 | UINT32 EventInterrupt;\r | |
602 | /// PRI Interrupt if SPI based\r | |
603 | UINT32 PriInterrupt;\r | |
604 | /// GERR interrupt if GSIV based\r | |
605 | UINT32 GerrInterrupt;\r | |
606 | /// Sync interrupt if GSIV based\r | |
607 | UINT32 SyncInterrupt;\r | |
608 | \r | |
609 | /// Proximity domain flag\r | |
610 | UINT32 ProximityDomain;\r | |
611 | /// Index into the array of ID mapping\r | |
612 | UINT32 DeviceIdMappingIndex;\r | |
613 | } CM_ARM_SMMUV3_NODE;\r | |
614 | \r | |
615 | /** A structure that describes the\r | |
616 | PMCG node for the Platform.\r | |
c606f472 SM |
617 | \r |
618 | ID: EArmObjPmcg\r | |
26147c77 SM |
619 | */\r |
620 | typedef struct CmArmPmcgNode {\r | |
c606f472 | 621 | /// An unique token used to identify this object\r |
26147c77 SM |
622 | CM_OBJECT_TOKEN Token;\r |
623 | /// Number of ID mappings\r | |
624 | UINT32 IdMappingCount;\r | |
625 | /// Reference token for the ID mapping array\r | |
626 | CM_OBJECT_TOKEN IdMappingToken;\r | |
627 | \r | |
628 | /// Base Address for performance monitor counter group\r | |
629 | UINT64 BaseAddress;\r | |
630 | /// GSIV for the Overflow interrupt\r | |
631 | UINT32 OverflowInterrupt;\r | |
632 | /// Page 1 Base address\r | |
633 | UINT64 Page1BaseAddress;\r | |
634 | \r | |
635 | /// Reference token for the IORT node associated with this node\r | |
636 | CM_OBJECT_TOKEN ReferenceToken;\r | |
637 | } CM_ARM_PMCG_NODE;\r | |
638 | \r | |
639 | /** A structure that describes the\r | |
640 | ID Mappings for the Platform.\r | |
c606f472 SM |
641 | \r |
642 | ID: EArmObjIdMappingArray\r | |
26147c77 SM |
643 | */\r |
644 | typedef struct CmArmIdMapping {\r | |
645 | /// Input base\r | |
646 | UINT32 InputBase;\r | |
647 | /// Number of input IDs\r | |
648 | UINT32 NumIds;\r | |
649 | /// Output Base\r | |
650 | UINT32 OutputBase;\r | |
651 | /// Reference token for the output node\r | |
652 | CM_OBJECT_TOKEN OutputReferenceToken;\r | |
653 | /// Flags\r | |
654 | UINT32 Flags;\r | |
655 | } CM_ARM_ID_MAPPING;\r | |
656 | \r | |
37568365 PG |
657 | /** A structure that describes the Arm\r |
658 | Generic Interrupts.\r | |
26147c77 | 659 | */\r |
37568365 | 660 | typedef struct CmArmGenericInterrupt {\r |
26147c77 SM |
661 | /// Interrupt number\r |
662 | UINT32 Interrupt;\r | |
663 | \r | |
664 | /// Flags\r | |
665 | UINT32 Flags;\r | |
37568365 PG |
666 | } CM_ARM_GENERIC_INTERRUPT;\r |
667 | \r | |
668 | /** A structure that describes the SMMU interrupts for the Platform.\r | |
669 | \r | |
670 | Interrupt Interrupt number.\r | |
671 | Flags Interrupt flags as defined for SMMU node.\r | |
672 | \r | |
673 | ID: EArmObjSmmuInterruptArray\r | |
674 | */\r | |
675 | typedef CM_ARM_GENERIC_INTERRUPT CM_ARM_SMMU_INTERRUPT;\r | |
676 | \r | |
677 | /** A structure that describes the AML Extended Interrupts.\r | |
678 | \r | |
679 | Interrupt Interrupt number.\r | |
680 | Flags Interrupt flags as defined by the Interrupt\r | |
681 | Vector Flags (Byte 3) of the Extended Interrupt\r | |
682 | resource descriptor.\r | |
683 | See EFI_ACPI_EXTENDED_INTERRUPT_FLAG_xxx in Acpi10.h\r | |
684 | \r | |
685 | ID: EArmObjExtendedInterruptInfo\r | |
686 | */\r | |
687 | typedef CM_ARM_GENERIC_INTERRUPT CM_ARM_EXTENDED_INTERRUPT;\r | |
26147c77 | 688 | \r |
77db1156 KK |
689 | /** A structure that describes the Processor Hierarchy Node (Type 0) in PPTT\r |
690 | \r | |
691 | ID: EArmObjProcHierarchyInfo\r | |
692 | */\r | |
693 | typedef struct CmArmProcHierarchyInfo {\r | |
694 | /// A unique token used to identify this object\r | |
695 | CM_OBJECT_TOKEN Token;\r | |
696 | /// Processor structure flags (ACPI 6.3 - January 2019, PPTT, Table 5-155)\r | |
697 | UINT32 Flags;\r | |
698 | /// Token for the parent CM_ARM_PROC_HIERARCHY_INFO object in the processor\r | |
699 | /// topology. A value of CM_NULL_TOKEN means this node has no parent.\r | |
700 | CM_OBJECT_TOKEN ParentToken;\r | |
701 | /// Token of the associated CM_ARM_GICC_INFO object which has the\r | |
702 | /// corresponding ACPI Processor ID. A value of CM_NULL_TOKEN means this\r | |
703 | /// node represents a group of associated processors and it does not have an\r | |
704 | /// associated GIC CPU interface.\r | |
705 | CM_OBJECT_TOKEN GicCToken;\r | |
706 | /// Number of resources private to this Node\r | |
707 | UINT32 NoOfPrivateResources;\r | |
708 | /// Token of the array which contains references to the resources private to\r | |
709 | /// this CM_ARM_PROC_HIERARCHY_INFO instance. This field is ignored if\r | |
e3f8605a | 710 | /// the NoOfPrivateResources is 0, in which case it is recommended to set\r |
77db1156 KK |
711 | /// this field to CM_NULL_TOKEN.\r |
712 | CM_OBJECT_TOKEN PrivateResourcesArrayToken;\r | |
713 | } CM_ARM_PROC_HIERARCHY_INFO;\r | |
714 | \r | |
715 | /** A structure that describes the Cache Type Structure (Type 1) in PPTT\r | |
716 | \r | |
717 | ID: EArmObjCacheInfo\r | |
718 | */\r | |
719 | typedef struct CmArmCacheInfo {\r | |
720 | /// A unique token used to identify this object\r | |
721 | CM_OBJECT_TOKEN Token;\r | |
722 | /// Reference token for the next level of cache that is private to the same\r | |
723 | /// CM_ARM_PROC_HIERARCHY_INFO instance. A value of CM_NULL_TOKEN means this\r | |
724 | /// entry represents the last cache level appropriate to the processor\r | |
725 | /// hierarchy node structures using this entry.\r | |
726 | CM_OBJECT_TOKEN NextLevelOfCacheToken;\r | |
727 | /// Size of the cache in bytes\r | |
728 | UINT32 Size;\r | |
729 | /// Number of sets in the cache\r | |
730 | UINT32 NumberOfSets;\r | |
731 | /// Integer number of ways. The maximum associativity supported by\r | |
732 | /// ACPI Cache type structure is limited to MAX_UINT8. However,\r | |
733 | /// the maximum number of ways supported by the architecture is\r | |
734 | /// PPTT_ARM_CCIDX_CACHE_ASSOCIATIVITY_MAX. Therfore this field\r | |
735 | /// is 32-bit wide.\r | |
736 | UINT32 Associativity;\r | |
737 | /// Cache attributes (ACPI 6.3 - January 2019, PPTT, Table 5-156)\r | |
738 | UINT8 Attributes;\r | |
739 | /// Line size in bytes\r | |
740 | UINT16 LineSize;\r | |
741 | } CM_ARM_CACHE_INFO;\r | |
742 | \r | |
743 | /** A structure that describes the ID Structure (Type 2) in PPTT\r | |
744 | \r | |
745 | ID: EArmObjProcNodeIdInfo\r | |
746 | */\r | |
747 | typedef struct CmArmProcNodeIdInfo {\r | |
748 | /// A unique token used to identify this object\r | |
749 | CM_OBJECT_TOKEN Token;\r | |
750 | // Vendor ID (as described in ACPI ID registry)\r | |
751 | UINT32 VendorId;\r | |
752 | /// First level unique node ID\r | |
753 | UINT64 Level1Id;\r | |
754 | /// Second level unique node ID\r | |
755 | UINT64 Level2Id;\r | |
756 | /// Major revision of the node\r | |
757 | UINT16 MajorRev;\r | |
758 | /// Minor revision of the node\r | |
759 | UINT16 MinorRev;\r | |
760 | /// Spin revision of the node\r | |
761 | UINT16 SpinRev;\r | |
762 | } CM_ARM_PROC_NODE_ID_INFO;\r | |
763 | \r | |
764 | /** A structure that describes a reference to another Configuration Manager\r | |
765 | object.\r | |
766 | \r | |
767 | This is useful for creating an array of reference tokens. The framework\r | |
768 | can then query the configuration manager for these arrays using the\r | |
769 | object ID EArmObjCmRef.\r | |
770 | \r | |
771 | This can be used is to represent one-to-many relationships between objects.\r | |
772 | \r | |
773 | ID: EArmObjCmRef\r | |
774 | */\r | |
775 | typedef struct CmArmObjRef {\r | |
776 | /// Token of the CM object being referenced\r | |
777 | CM_OBJECT_TOKEN ReferenceToken;\r | |
778 | } CM_ARM_OBJ_REF;\r | |
779 | \r | |
f413d9be SM |
780 | /** A structure that describes the Memory Affinity Structure (Type 1) in SRAT\r |
781 | \r | |
782 | ID: EArmObjMemoryAffinityInfo\r | |
783 | */\r | |
784 | typedef struct CmArmMemoryAffinityInfo {\r | |
785 | /// The proximity domain to which the "range of memory" belongs.\r | |
786 | UINT32 ProximityDomain;\r | |
787 | \r | |
788 | /// Base Address\r | |
789 | UINT64 BaseAddress;\r | |
790 | \r | |
791 | /// Length\r | |
792 | UINT64 Length;\r | |
793 | \r | |
794 | /// Flags\r | |
795 | UINT32 Flags;\r | |
796 | } CM_ARM_MEMORY_AFFINITY_INFO;\r | |
797 | \r | |
798 | /** A structure that describes the ACPI Device Handle (Type 0) in the\r | |
799 | Generic Initiator Affinity structure in SRAT\r | |
800 | \r | |
801 | ID: EArmObjDeviceHandleAcpi\r | |
802 | */\r | |
803 | typedef struct CmArmDeviceHandleAcpi {\r | |
804 | /// Hardware ID\r | |
805 | UINT64 Hid;\r | |
806 | \r | |
807 | /// Unique Id\r | |
808 | UINT32 Uid;\r | |
809 | } CM_ARM_DEVICE_HANDLE_ACPI;\r | |
810 | \r | |
811 | /** A structure that describes the PCI Device Handle (Type 1) in the\r | |
812 | Generic Initiator Affinity structure in SRAT\r | |
813 | \r | |
814 | ID: EArmObjDeviceHandlePci\r | |
815 | */\r | |
816 | typedef struct CmArmDeviceHandlePci {\r | |
817 | /// PCI Segment Number\r | |
818 | UINT16 SegmentNumber;\r | |
819 | \r | |
820 | /// PCI Bus Number - Max 256 busses (Bits 15:8 of BDF)\r | |
821 | UINT8 BusNumber;\r | |
822 | \r | |
e3f8605a | 823 | /// PCI Device Number - Max 32 devices (Bits 7:3 of BDF)\r |
f413d9be SM |
824 | UINT8 DeviceNumber;\r |
825 | \r | |
826 | /// PCI Function Number - Max 8 functions (Bits 2:0 of BDF)\r | |
827 | UINT8 FunctionNumber;\r | |
828 | } CM_ARM_DEVICE_HANDLE_PCI;\r | |
829 | \r | |
830 | /** A structure that describes the Generic Initiator Affinity structure in SRAT\r | |
831 | \r | |
832 | ID: EArmObjGenericInitiatorAffinityInfo\r | |
833 | */\r | |
834 | typedef struct CmArmGenericInitiatorAffinityInfo {\r | |
835 | /// The proximity domain to which the generic initiator belongs.\r | |
836 | UINT32 ProximityDomain;\r | |
837 | \r | |
838 | /// Flags\r | |
839 | UINT32 Flags;\r | |
840 | \r | |
841 | /// Device Handle Type\r | |
842 | UINT8 DeviceHandleType;\r | |
843 | \r | |
844 | /// Reference Token for the Device Handle\r | |
845 | CM_OBJECT_TOKEN DeviceHandleToken;\r | |
846 | } CM_ARM_GENERIC_INITIATOR_AFFINITY_INFO;\r | |
847 | \r | |
37568365 PG |
848 | /** A structure that describes the CMN-600 hardware.\r |
849 | \r | |
850 | ID: EArmObjCmn600Info\r | |
851 | */\r | |
852 | typedef struct CmArmCmn600Info {\r | |
853 | /// The PERIPHBASE address.\r | |
854 | /// Corresponds to the Configuration Node Region (CFGR) base address.\r | |
855 | UINT64 PeriphBaseAddress;\r | |
856 | \r | |
857 | /// The PERIPHBASE address length.\r | |
858 | /// Corresponds to the CFGR base address length.\r | |
859 | UINT64 PeriphBaseAddressLength;\r | |
860 | \r | |
861 | /// The ROOTNODEBASE address.\r | |
862 | /// Corresponds to the Root node (ROOT) base address.\r | |
863 | UINT64 RootNodeBaseAddress;\r | |
864 | \r | |
865 | /// The Debug and Trace Logic Controller (DTC) count.\r | |
866 | /// CMN-600 can have maximum 4 DTCs.\r | |
867 | UINT8 DtcCount;\r | |
868 | \r | |
869 | /// DTC Interrupt list.\r | |
870 | /// The first interrupt resource descriptor pertains to\r | |
871 | /// DTC[0], the second to DTC[1] and so on.\r | |
872 | /// DtcCount determines the number of DTC Interrupts that\r | |
873 | /// are populated. If DTC count is 2 then DtcInterrupt[2]\r | |
874 | /// and DtcInterrupt[3] are ignored.\r | |
875 | /// Note: The size of CM_ARM_CMN_600_INFO structure remains\r | |
876 | /// constant and does not vary with the DTC count.\r | |
877 | CM_ARM_EXTENDED_INTERRUPT DtcInterrupt[4];\r | |
878 | } CM_ARM_CMN_600_INFO;\r | |
879 | \r | |
26147c77 SM |
880 | #pragma pack()\r |
881 | \r | |
882 | #endif // ARM_NAMESPACE_OBJECTS_H_\r |