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26147c77 SM |
1 | /** @file\r |
2 | \r | |
cc00dbcb | 3 | Copyright (c) 2017 - 2021, Arm Limited. All rights reserved.<BR>\r |
26147c77 | 4 | \r |
9cd9bdc6 | 5 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
26147c77 SM |
6 | \r |
7 | @par Glossary:\r | |
8 | - Cm or CM - Configuration Manager\r | |
9 | - Obj or OBJ - Object\r | |
10 | - Std or STD - Standard\r | |
11 | **/\r | |
12 | \r | |
13 | #ifndef ARM_NAMESPACE_OBJECTS_H_\r | |
14 | #define ARM_NAMESPACE_OBJECTS_H_\r | |
15 | \r | |
16 | #include <StandardNameSpaceObjects.h>\r | |
17 | \r | |
18 | #pragma pack(1)\r | |
19 | \r | |
20 | /** The EARM_OBJECT_ID enum describes the Object IDs\r | |
21 | in the ARM Namespace\r | |
22 | */\r | |
23 | typedef enum ArmObjectID {\r | |
f413d9be SM |
24 | EArmObjReserved, ///< 0 - Reserved\r |
25 | EArmObjBootArchInfo, ///< 1 - Boot Architecture Info\r | |
26 | EArmObjCpuInfo, ///< 2 - CPU Info\r | |
27 | EArmObjPowerManagementProfileInfo, ///< 3 - Power Management Profile Info\r | |
28 | EArmObjGicCInfo, ///< 4 - GIC CPU Interface Info\r | |
29 | EArmObjGicDInfo, ///< 5 - GIC Distributor Info\r | |
30 | EArmObjGicMsiFrameInfo, ///< 6 - GIC MSI Frame Info\r | |
31 | EArmObjGicRedistributorInfo, ///< 7 - GIC Redistributor Info\r | |
32 | EArmObjGicItsInfo, ///< 8 - GIC ITS Info\r | |
33 | EArmObjSerialConsolePortInfo, ///< 9 - Serial Console Port Info\r | |
34 | EArmObjSerialDebugPortInfo, ///< 10 - Serial Debug Port Info\r | |
35 | EArmObjGenericTimerInfo, ///< 11 - Generic Timer Info\r | |
36 | EArmObjPlatformGTBlockInfo, ///< 12 - Platform GT Block Info\r | |
37 | EArmObjGTBlockTimerFrameInfo, ///< 13 - Generic Timer Block Frame Info\r | |
38 | EArmObjPlatformGenericWatchdogInfo, ///< 14 - Platform Generic Watchdog\r | |
39 | EArmObjPciConfigSpaceInfo, ///< 15 - PCI Configuration Space Info\r | |
40 | EArmObjHypervisorVendorIdentity, ///< 16 - Hypervisor Vendor Id\r | |
41 | EArmObjFixedFeatureFlags, ///< 17 - Fixed feature flags for FADT\r | |
42 | EArmObjItsGroup, ///< 18 - ITS Group\r | |
43 | EArmObjNamedComponent, ///< 19 - Named Component\r | |
44 | EArmObjRootComplex, ///< 20 - Root Complex\r | |
45 | EArmObjSmmuV1SmmuV2, ///< 21 - SMMUv1 or SMMUv2\r | |
46 | EArmObjSmmuV3, ///< 22 - SMMUv3\r | |
47 | EArmObjPmcg, ///< 23 - PMCG\r | |
48 | EArmObjGicItsIdentifierArray, ///< 24 - GIC ITS Identifier Array\r | |
49 | EArmObjIdMappingArray, ///< 25 - ID Mapping Array\r | |
50 | EArmObjSmmuInterruptArray, ///< 26 - SMMU Interrupt Array\r | |
51 | EArmObjProcHierarchyInfo, ///< 27 - Processor Hierarchy Info\r | |
52 | EArmObjCacheInfo, ///< 28 - Cache Info\r | |
b2bbe3df | 53 | EArmObjReserved29, ///< 29 - Reserved\r |
f413d9be SM |
54 | EArmObjCmRef, ///< 30 - CM Object Reference\r |
55 | EArmObjMemoryAffinityInfo, ///< 31 - Memory Affinity Info\r | |
56 | EArmObjDeviceHandleAcpi, ///< 32 - Device Handle Acpi\r | |
57 | EArmObjDeviceHandlePci, ///< 33 - Device Handle Pci\r | |
58 | EArmObjGenericInitiatorAffinityInfo, ///< 34 - Generic Initiator Affinity\r | |
bade7f42 | 59 | EArmObjSerialPortInfo, ///< 35 - Generic Serial Port Info\r |
37568365 | 60 | EArmObjCmn600Info, ///< 36 - CMN-600 Info\r |
f17ef10e | 61 | EArmObjLpiInfo, ///< 37 - Lpi Info\r |
26147c77 SM |
62 | EArmObjMax\r |
63 | } EARM_OBJECT_ID;\r | |
64 | \r | |
65 | /** A structure that describes the\r | |
66 | ARM Boot Architecture flags.\r | |
c606f472 SM |
67 | \r |
68 | ID: EArmObjBootArchInfo\r | |
26147c77 SM |
69 | */\r |
70 | typedef struct CmArmBootArchInfo {\r | |
71 | /** This is the ARM_BOOT_ARCH flags field of the FADT Table\r | |
72 | described in the ACPI Table Specification.\r | |
73 | */\r | |
731c67e1 | 74 | UINT16 BootArchFlags;\r |
26147c77 SM |
75 | } CM_ARM_BOOT_ARCH_INFO;\r |
76 | \r | |
26147c77 SM |
77 | /** A structure that describes the\r |
78 | Power Management Profile Information for the Platform.\r | |
c606f472 SM |
79 | \r |
80 | ID: EArmObjPowerManagementProfileInfo\r | |
26147c77 SM |
81 | */\r |
82 | typedef struct CmArmPowerManagementProfileInfo {\r | |
83 | /** This is the Preferred_PM_Profile field of the FADT Table\r | |
84 | described in the ACPI Specification\r | |
85 | */\r | |
731c67e1 | 86 | UINT8 PowerManagementProfile;\r |
26147c77 SM |
87 | } CM_ARM_POWER_MANAGEMENT_PROFILE_INFO;\r |
88 | \r | |
89 | /** A structure that describes the\r | |
90 | GIC CPU Interface for the Platform.\r | |
c606f472 SM |
91 | \r |
92 | ID: EArmObjGicCInfo\r | |
26147c77 SM |
93 | */\r |
94 | typedef struct CmArmGicCInfo {\r | |
95 | /// The GIC CPU Interface number.\r | |
731c67e1 | 96 | UINT32 CPUInterfaceNumber;\r |
26147c77 SM |
97 | \r |
98 | /** The ACPI Processor UID. This must match the\r | |
99 | _UID of the CPU Device object information described\r | |
100 | in the DSDT/SSDT for the CPU.\r | |
101 | */\r | |
731c67e1 | 102 | UINT32 AcpiProcessorUid;\r |
26147c77 SM |
103 | \r |
104 | /** The flags field as described by the GICC structure\r | |
105 | in the ACPI Specification.\r | |
106 | */\r | |
731c67e1 | 107 | UINT32 Flags;\r |
26147c77 SM |
108 | \r |
109 | /** The parking protocol version field as described by\r | |
110 | the GICC structure in the ACPI Specification.\r | |
111 | */\r | |
731c67e1 | 112 | UINT32 ParkingProtocolVersion;\r |
26147c77 SM |
113 | \r |
114 | /** The Performance Interrupt field as described by\r | |
115 | the GICC structure in the ACPI Specification.\r | |
116 | */\r | |
731c67e1 | 117 | UINT32 PerformanceInterruptGsiv;\r |
26147c77 SM |
118 | \r |
119 | /** The CPU Parked address field as described by\r | |
120 | the GICC structure in the ACPI Specification.\r | |
121 | */\r | |
731c67e1 | 122 | UINT64 ParkedAddress;\r |
26147c77 SM |
123 | \r |
124 | /** The base address for the GIC CPU Interface\r | |
125 | as described by the GICC structure in the\r | |
126 | ACPI Specification.\r | |
127 | */\r | |
731c67e1 | 128 | UINT64 PhysicalBaseAddress;\r |
26147c77 SM |
129 | \r |
130 | /** The base address for GICV interface\r | |
131 | as described by the GICC structure in the\r | |
132 | ACPI Specification.\r | |
133 | */\r | |
731c67e1 | 134 | UINT64 GICV;\r |
26147c77 SM |
135 | \r |
136 | /** The base address for GICH interface\r | |
137 | as described by the GICC structure in the\r | |
138 | ACPI Specification.\r | |
139 | */\r | |
731c67e1 | 140 | UINT64 GICH;\r |
26147c77 SM |
141 | \r |
142 | /** The GICV maintenance interrupt\r | |
143 | as described by the GICC structure in the\r | |
144 | ACPI Specification.\r | |
145 | */\r | |
731c67e1 | 146 | UINT32 VGICMaintenanceInterrupt;\r |
26147c77 SM |
147 | \r |
148 | /** The base address for GICR interface\r | |
149 | as described by the GICC structure in the\r | |
150 | ACPI Specification.\r | |
151 | */\r | |
731c67e1 | 152 | UINT64 GICRBaseAddress;\r |
26147c77 SM |
153 | \r |
154 | /** The MPIDR for the CPU\r | |
155 | as described by the GICC structure in the\r | |
156 | ACPI Specification.\r | |
157 | */\r | |
731c67e1 | 158 | UINT64 MPIDR;\r |
26147c77 SM |
159 | \r |
160 | /** The Processor Power Efficiency class\r | |
161 | as described by the GICC structure in the\r | |
162 | ACPI Specification.\r | |
163 | */\r | |
731c67e1 | 164 | UINT8 ProcessorPowerEfficiencyClass;\r |
5506701f KK |
165 | \r |
166 | /** Statistical Profiling Extension buffer overflow GSIV. Zero if\r | |
167 | unsupported by this processor. This field was introduced in\r | |
168 | ACPI 6.3 (MADT revision 5) and is therefore ignored when\r | |
169 | generating MADT revision 4 or lower.\r | |
170 | */\r | |
731c67e1 | 171 | UINT16 SpeOverflowInterrupt;\r |
f413d9be SM |
172 | \r |
173 | /** The proximity domain to which the logical processor belongs.\r | |
174 | This field is used to populate the GICC affinity structure\r | |
175 | in the SRAT table.\r | |
176 | */\r | |
731c67e1 | 177 | UINT32 ProximityDomain;\r |
f413d9be SM |
178 | \r |
179 | /** The clock domain to which the logical processor belongs.\r | |
180 | This field is used to populate the GICC affinity structure\r | |
181 | in the SRAT table.\r | |
182 | */\r | |
731c67e1 | 183 | UINT32 ClockDomain;\r |
f413d9be SM |
184 | \r |
185 | /** The GICC Affinity flags field as described by the GICC Affinity structure\r | |
186 | in the SRAT table.\r | |
187 | */\r | |
731c67e1 | 188 | UINT32 AffinityFlags;\r |
26147c77 SM |
189 | } CM_ARM_GICC_INFO;\r |
190 | \r | |
191 | /** A structure that describes the\r | |
192 | GIC Distributor information for the Platform.\r | |
c606f472 SM |
193 | \r |
194 | ID: EArmObjGicDInfo\r | |
26147c77 SM |
195 | */\r |
196 | typedef struct CmArmGicDInfo {\r | |
26147c77 | 197 | /// The Physical Base address for the GIC Distributor.\r |
731c67e1 | 198 | UINT64 PhysicalBaseAddress;\r |
26147c77 SM |
199 | \r |
200 | /** The global system interrupt\r | |
201 | number where this GIC Distributor's\r | |
202 | interrupt inputs start.\r | |
203 | */\r | |
731c67e1 | 204 | UINT32 SystemVectorBase;\r |
26147c77 SM |
205 | \r |
206 | /** The GIC version as described\r | |
207 | by the GICD structure in the\r | |
208 | ACPI Specification.\r | |
209 | */\r | |
731c67e1 | 210 | UINT8 GicVersion;\r |
26147c77 SM |
211 | } CM_ARM_GICD_INFO;\r |
212 | \r | |
213 | /** A structure that describes the\r | |
214 | GIC MSI Frame information for the Platform.\r | |
c606f472 SM |
215 | \r |
216 | ID: EArmObjGicMsiFrameInfo\r | |
26147c77 SM |
217 | */\r |
218 | typedef struct CmArmGicMsiFrameInfo {\r | |
219 | /// The GIC MSI Frame ID\r | |
731c67e1 | 220 | UINT32 GicMsiFrameId;\r |
26147c77 SM |
221 | \r |
222 | /// The Physical base address for the MSI Frame\r | |
731c67e1 | 223 | UINT64 PhysicalBaseAddress;\r |
26147c77 SM |
224 | \r |
225 | /** The GIC MSI Frame flags\r | |
226 | as described by the GIC MSI frame\r | |
227 | structure in the ACPI Specification.\r | |
228 | */\r | |
731c67e1 | 229 | UINT32 Flags;\r |
26147c77 SM |
230 | \r |
231 | /// SPI Count used by this frame\r | |
731c67e1 | 232 | UINT16 SPICount;\r |
26147c77 SM |
233 | \r |
234 | /// SPI Base used by this frame\r | |
731c67e1 | 235 | UINT16 SPIBase;\r |
26147c77 SM |
236 | } CM_ARM_GIC_MSI_FRAME_INFO;\r |
237 | \r | |
238 | /** A structure that describes the\r | |
239 | GIC Redistributor information for the Platform.\r | |
c606f472 SM |
240 | \r |
241 | ID: EArmObjGicRedistributorInfo\r | |
26147c77 SM |
242 | */\r |
243 | typedef struct CmArmGicRedistInfo {\r | |
244 | /** The physical address of a page range\r | |
245 | containing all GIC Redistributors.\r | |
246 | */\r | |
731c67e1 | 247 | UINT64 DiscoveryRangeBaseAddress;\r |
26147c77 SM |
248 | \r |
249 | /// Length of the GIC Redistributor Discovery page range\r | |
731c67e1 | 250 | UINT32 DiscoveryRangeLength;\r |
26147c77 SM |
251 | } CM_ARM_GIC_REDIST_INFO;\r |
252 | \r | |
253 | /** A structure that describes the\r | |
254 | GIC Interrupt Translation Service information for the Platform.\r | |
c606f472 SM |
255 | \r |
256 | ID: EArmObjGicItsInfo\r | |
26147c77 SM |
257 | */\r |
258 | typedef struct CmArmGicItsInfo {\r | |
259 | /// The GIC ITS ID\r | |
731c67e1 | 260 | UINT32 GicItsId;\r |
26147c77 SM |
261 | \r |
262 | /// The physical address for the Interrupt Translation Service\r | |
731c67e1 | 263 | UINT64 PhysicalBaseAddress;\r |
f413d9be SM |
264 | \r |
265 | /** The proximity domain to which the logical processor belongs.\r | |
266 | This field is used to populate the GIC ITS affinity structure\r | |
267 | in the SRAT table.\r | |
268 | */\r | |
731c67e1 | 269 | UINT32 ProximityDomain;\r |
26147c77 SM |
270 | } CM_ARM_GIC_ITS_INFO;\r |
271 | \r | |
272 | /** A structure that describes the\r | |
273 | Serial Port information for the Platform.\r | |
c606f472 SM |
274 | \r |
275 | ID: EArmObjSerialConsolePortInfo or\r | |
bade7f42 PG |
276 | EArmObjSerialDebugPortInfo or\r |
277 | EArmObjSerialPortInfo\r | |
26147c77 SM |
278 | */\r |
279 | typedef struct CmArmSerialPortInfo {\r | |
280 | /// The physical base address for the serial port\r | |
731c67e1 | 281 | UINT64 BaseAddress;\r |
26147c77 SM |
282 | \r |
283 | /// The serial port interrupt\r | |
731c67e1 | 284 | UINT32 Interrupt;\r |
26147c77 SM |
285 | \r |
286 | /// The serial port baud rate\r | |
731c67e1 | 287 | UINT64 BaudRate;\r |
26147c77 SM |
288 | \r |
289 | /// The serial port clock\r | |
731c67e1 | 290 | UINT32 Clock;\r |
26147c77 SM |
291 | \r |
292 | /// Serial Port subtype\r | |
731c67e1 | 293 | UINT16 PortSubtype;\r |
bade7f42 PG |
294 | \r |
295 | /// The Base address length\r | |
731c67e1 | 296 | UINT64 BaseAddressLength;\r |
c8cf71ec JG |
297 | \r |
298 | /// The access size\r | |
731c67e1 | 299 | UINT8 AccessSize;\r |
26147c77 SM |
300 | } CM_ARM_SERIAL_PORT_INFO;\r |
301 | \r | |
302 | /** A structure that describes the\r | |
303 | Generic Timer information for the Platform.\r | |
c606f472 SM |
304 | \r |
305 | ID: EArmObjGenericTimerInfo\r | |
26147c77 SM |
306 | */\r |
307 | typedef struct CmArmGenericTimerInfo {\r | |
308 | /// The physical base address for the counter control frame\r | |
731c67e1 | 309 | UINT64 CounterControlBaseAddress;\r |
26147c77 SM |
310 | \r |
311 | /// The physical base address for the counter read frame\r | |
731c67e1 | 312 | UINT64 CounterReadBaseAddress;\r |
26147c77 SM |
313 | \r |
314 | /// The secure PL1 timer interrupt\r | |
731c67e1 | 315 | UINT32 SecurePL1TimerGSIV;\r |
26147c77 SM |
316 | \r |
317 | /// The secure PL1 timer flags\r | |
731c67e1 | 318 | UINT32 SecurePL1TimerFlags;\r |
26147c77 SM |
319 | \r |
320 | /// The non-secure PL1 timer interrupt\r | |
731c67e1 | 321 | UINT32 NonSecurePL1TimerGSIV;\r |
26147c77 SM |
322 | \r |
323 | /// The non-secure PL1 timer flags\r | |
731c67e1 | 324 | UINT32 NonSecurePL1TimerFlags;\r |
26147c77 SM |
325 | \r |
326 | /// The virtual timer interrupt\r | |
731c67e1 | 327 | UINT32 VirtualTimerGSIV;\r |
26147c77 SM |
328 | \r |
329 | /// The virtual timer flags\r | |
731c67e1 | 330 | UINT32 VirtualTimerFlags;\r |
26147c77 SM |
331 | \r |
332 | /// The non-secure PL2 timer interrupt\r | |
731c67e1 | 333 | UINT32 NonSecurePL2TimerGSIV;\r |
26147c77 SM |
334 | \r |
335 | /// The non-secure PL2 timer flags\r | |
731c67e1 | 336 | UINT32 NonSecurePL2TimerFlags;\r |
e8015f2f PG |
337 | \r |
338 | /// GSIV for the virtual EL2 timer\r | |
731c67e1 | 339 | UINT32 VirtualPL2TimerGSIV;\r |
e8015f2f PG |
340 | \r |
341 | /// Flags for the virtual EL2 timer\r | |
731c67e1 | 342 | UINT32 VirtualPL2TimerFlags;\r |
26147c77 SM |
343 | } CM_ARM_GENERIC_TIMER_INFO;\r |
344 | \r | |
345 | /** A structure that describes the\r | |
346 | Platform Generic Block Timer Frame information for the Platform.\r | |
c606f472 SM |
347 | \r |
348 | ID: EArmObjGTBlockTimerFrameInfo\r | |
26147c77 SM |
349 | */\r |
350 | typedef struct CmArmGTBlockTimerFrameInfo {\r | |
351 | /// The Generic Timer frame number\r | |
731c67e1 | 352 | UINT8 FrameNumber;\r |
26147c77 SM |
353 | \r |
354 | /// The physical base address for the CntBase block\r | |
731c67e1 | 355 | UINT64 PhysicalAddressCntBase;\r |
26147c77 SM |
356 | \r |
357 | /// The physical base address for the CntEL0Base block\r | |
731c67e1 | 358 | UINT64 PhysicalAddressCntEL0Base;\r |
26147c77 SM |
359 | \r |
360 | /// The physical timer interrupt\r | |
731c67e1 | 361 | UINT32 PhysicalTimerGSIV;\r |
26147c77 SM |
362 | \r |
363 | /** The physical timer flags as described by the GT Block\r | |
364 | Timer frame Structure in the ACPI Specification.\r | |
365 | */\r | |
731c67e1 | 366 | UINT32 PhysicalTimerFlags;\r |
26147c77 SM |
367 | \r |
368 | /// The virtual timer interrupt\r | |
731c67e1 | 369 | UINT32 VirtualTimerGSIV;\r |
26147c77 SM |
370 | \r |
371 | /** The virtual timer flags as described by the GT Block\r | |
372 | Timer frame Structure in the ACPI Specification.\r | |
373 | */\r | |
731c67e1 | 374 | UINT32 VirtualTimerFlags;\r |
26147c77 SM |
375 | \r |
376 | /** The common timer flags as described by the GT Block\r | |
377 | Timer frame Structure in the ACPI Specification.\r | |
378 | */\r | |
731c67e1 | 379 | UINT32 CommonFlags;\r |
26147c77 SM |
380 | } CM_ARM_GTBLOCK_TIMER_FRAME_INFO;\r |
381 | \r | |
382 | /** A structure that describes the\r | |
383 | Platform Generic Block Timer information for the Platform.\r | |
c606f472 SM |
384 | \r |
385 | ID: EArmObjPlatformGTBlockInfo\r | |
26147c77 SM |
386 | */\r |
387 | typedef struct CmArmGTBlockInfo {\r | |
388 | /// The physical base address for the GT Block Timer structure\r | |
731c67e1 | 389 | UINT64 GTBlockPhysicalAddress;\r |
26147c77 SM |
390 | \r |
391 | /// The number of timer frames implemented in the GT Block\r | |
731c67e1 | 392 | UINT32 GTBlockTimerFrameCount;\r |
26147c77 SM |
393 | \r |
394 | /// Reference token for the GT Block timer frame list\r | |
731c67e1 | 395 | CM_OBJECT_TOKEN GTBlockTimerFrameToken;\r |
26147c77 SM |
396 | } CM_ARM_GTBLOCK_INFO;\r |
397 | \r | |
398 | /** A structure that describes the\r | |
f09dbf20 | 399 | Arm Generic Watchdog information for the Platform.\r |
c606f472 SM |
400 | \r |
401 | ID: EArmObjPlatformGenericWatchdogInfo\r | |
26147c77 SM |
402 | */\r |
403 | typedef struct CmArmGenericWatchdogInfo {\r | |
f09dbf20 | 404 | /// The physical base address of the Arm Watchdog control frame\r |
731c67e1 | 405 | UINT64 ControlFrameAddress;\r |
26147c77 | 406 | \r |
f09dbf20 | 407 | /// The physical base address of the Arm Watchdog refresh frame\r |
731c67e1 | 408 | UINT64 RefreshFrameAddress;\r |
26147c77 SM |
409 | \r |
410 | /// The watchdog interrupt\r | |
731c67e1 | 411 | UINT32 TimerGSIV;\r |
26147c77 | 412 | \r |
f09dbf20 | 413 | /** The flags for the watchdog as described by the Arm watchdog\r |
26147c77 SM |
414 | structure in the ACPI specification.\r |
415 | */\r | |
731c67e1 | 416 | UINT32 Flags;\r |
26147c77 SM |
417 | } CM_ARM_GENERIC_WATCHDOG_INFO;\r |
418 | \r | |
419 | /** A structure that describes the\r | |
420 | PCI Configuration Space information for the Platform.\r | |
c606f472 SM |
421 | \r |
422 | ID: EArmObjPciConfigSpaceInfo\r | |
26147c77 SM |
423 | */\r |
424 | typedef struct CmArmPciConfigSpaceInfo {\r | |
425 | /// The physical base address for the PCI segment\r | |
731c67e1 | 426 | UINT64 BaseAddress;\r |
26147c77 SM |
427 | \r |
428 | /// The PCI segment group number\r | |
731c67e1 | 429 | UINT16 PciSegmentGroupNumber;\r |
26147c77 SM |
430 | \r |
431 | /// The start bus number\r | |
731c67e1 | 432 | UINT8 StartBusNumber;\r |
26147c77 SM |
433 | \r |
434 | /// The end bus number\r | |
731c67e1 | 435 | UINT8 EndBusNumber;\r |
26147c77 SM |
436 | } CM_ARM_PCI_CONFIG_SPACE_INFO;\r |
437 | \r | |
438 | /** A structure that describes the\r | |
439 | Hypervisor Vendor ID information for the Platform.\r | |
c606f472 SM |
440 | \r |
441 | ID: EArmObjHypervisorVendorIdentity\r | |
26147c77 SM |
442 | */\r |
443 | typedef struct CmArmHypervisorVendorId {\r | |
444 | /// The hypervisor Vendor ID\r | |
731c67e1 | 445 | UINT64 HypervisorVendorId;\r |
26147c77 SM |
446 | } CM_ARM_HYPERVISOR_VENDOR_ID;\r |
447 | \r | |
448 | /** A structure that describes the\r | |
449 | Fixed feature flags for the Platform.\r | |
c606f472 SM |
450 | \r |
451 | ID: EArmObjFixedFeatureFlags\r | |
26147c77 SM |
452 | */\r |
453 | typedef struct CmArmFixedFeatureFlags {\r | |
454 | /// The Fixed feature flags\r | |
731c67e1 | 455 | UINT32 Flags;\r |
26147c77 SM |
456 | } CM_ARM_FIXED_FEATURE_FLAGS;\r |
457 | \r | |
458 | /** A structure that describes the\r | |
459 | ITS Group node for the Platform.\r | |
c606f472 SM |
460 | \r |
461 | ID: EArmObjItsGroup\r | |
26147c77 SM |
462 | */\r |
463 | typedef struct CmArmItsGroupNode {\r | |
c606f472 | 464 | /// An unique token used to identify this object\r |
731c67e1 | 465 | CM_OBJECT_TOKEN Token;\r |
26147c77 | 466 | /// The number of ITS identifiers in the ITS node\r |
731c67e1 | 467 | UINT32 ItsIdCount;\r |
26147c77 | 468 | /// Reference token for the ITS identifier array\r |
731c67e1 | 469 | CM_OBJECT_TOKEN ItsIdToken;\r |
26147c77 SM |
470 | } CM_ARM_ITS_GROUP_NODE;\r |
471 | \r | |
26147c77 SM |
472 | /** A structure that describes the\r |
473 | Named component node for the Platform.\r | |
c606f472 SM |
474 | \r |
475 | ID: EArmObjNamedComponent\r | |
26147c77 SM |
476 | */\r |
477 | typedef struct CmArmNamedComponentNode {\r | |
c606f472 | 478 | /// An unique token used to identify this object\r |
731c67e1 | 479 | CM_OBJECT_TOKEN Token;\r |
26147c77 | 480 | /// Number of ID mappings\r |
731c67e1 | 481 | UINT32 IdMappingCount;\r |
26147c77 | 482 | /// Reference token for the ID mapping array\r |
731c67e1 | 483 | CM_OBJECT_TOKEN IdMappingToken;\r |
26147c77 SM |
484 | \r |
485 | /// Flags for the named component\r | |
731c67e1 | 486 | UINT32 Flags;\r |
26147c77 SM |
487 | \r |
488 | /// Memory access properties : Cache coherent attributes\r | |
731c67e1 | 489 | UINT32 CacheCoherent;\r |
26147c77 | 490 | /// Memory access properties : Allocation hints\r |
731c67e1 | 491 | UINT8 AllocationHints;\r |
26147c77 | 492 | /// Memory access properties : Memory access flags\r |
731c67e1 | 493 | UINT8 MemoryAccessFlags;\r |
26147c77 SM |
494 | \r |
495 | /// Memory access properties : Address size limit\r | |
731c67e1 MK |
496 | UINT8 AddressSizeLimit;\r |
497 | \r | |
26147c77 SM |
498 | /** ASCII Null terminated string with the full path to\r |
499 | the entry in the namespace for this object.\r | |
500 | */\r | |
731c67e1 | 501 | CHAR8 *ObjectName;\r |
26147c77 SM |
502 | } CM_ARM_NAMED_COMPONENT_NODE;\r |
503 | \r | |
504 | /** A structure that describes the\r | |
505 | Root complex node for the Platform.\r | |
c606f472 SM |
506 | \r |
507 | ID: EArmObjRootComplex\r | |
26147c77 SM |
508 | */\r |
509 | typedef struct CmArmRootComplexNode {\r | |
c606f472 | 510 | /// An unique token used to identify this object\r |
731c67e1 | 511 | CM_OBJECT_TOKEN Token;\r |
26147c77 | 512 | /// Number of ID mappings\r |
731c67e1 | 513 | UINT32 IdMappingCount;\r |
26147c77 | 514 | /// Reference token for the ID mapping array\r |
731c67e1 | 515 | CM_OBJECT_TOKEN IdMappingToken;\r |
26147c77 SM |
516 | \r |
517 | /// Memory access properties : Cache coherent attributes\r | |
731c67e1 | 518 | UINT32 CacheCoherent;\r |
26147c77 | 519 | /// Memory access properties : Allocation hints\r |
731c67e1 | 520 | UINT8 AllocationHints;\r |
26147c77 | 521 | /// Memory access properties : Memory access flags\r |
731c67e1 | 522 | UINT8 MemoryAccessFlags;\r |
26147c77 SM |
523 | \r |
524 | /// ATS attributes\r | |
731c67e1 | 525 | UINT32 AtsAttribute;\r |
26147c77 | 526 | /// PCI segment number\r |
731c67e1 | 527 | UINT32 PciSegmentNumber;\r |
26147c77 | 528 | /// Memory address size limit\r |
731c67e1 | 529 | UINT8 MemoryAddressSize;\r |
26147c77 SM |
530 | } CM_ARM_ROOT_COMPLEX_NODE;\r |
531 | \r | |
532 | /** A structure that describes the\r | |
533 | SMMUv1 or SMMUv2 node for the Platform.\r | |
c606f472 SM |
534 | \r |
535 | ID: EArmObjSmmuV1SmmuV2\r | |
26147c77 SM |
536 | */\r |
537 | typedef struct CmArmSmmuV1SmmuV2Node {\r | |
c606f472 | 538 | /// An unique token used to identify this object\r |
731c67e1 | 539 | CM_OBJECT_TOKEN Token;\r |
26147c77 | 540 | /// Number of ID mappings\r |
731c67e1 | 541 | UINT32 IdMappingCount;\r |
26147c77 | 542 | /// Reference token for the ID mapping array\r |
731c67e1 | 543 | CM_OBJECT_TOKEN IdMappingToken;\r |
26147c77 SM |
544 | \r |
545 | /// SMMU Base Address\r | |
731c67e1 | 546 | UINT64 BaseAddress;\r |
26147c77 | 547 | /// Length of the memory range covered by the SMMU\r |
731c67e1 | 548 | UINT64 Span;\r |
26147c77 | 549 | /// SMMU Model\r |
731c67e1 | 550 | UINT32 Model;\r |
26147c77 | 551 | /// SMMU flags\r |
731c67e1 | 552 | UINT32 Flags;\r |
26147c77 SM |
553 | \r |
554 | /// Number of context interrupts\r | |
731c67e1 | 555 | UINT32 ContextInterruptCount;\r |
26147c77 | 556 | /// Reference token for the context interrupt array\r |
731c67e1 | 557 | CM_OBJECT_TOKEN ContextInterruptToken;\r |
26147c77 SM |
558 | \r |
559 | /// Number of PMU interrupts\r | |
731c67e1 | 560 | UINT32 PmuInterruptCount;\r |
26147c77 | 561 | /// Reference token for the PMU interrupt array\r |
731c67e1 | 562 | CM_OBJECT_TOKEN PmuInterruptToken;\r |
26147c77 SM |
563 | \r |
564 | /// GSIV of the SMMU_NSgIrpt interrupt\r | |
731c67e1 | 565 | UINT32 SMMU_NSgIrpt;\r |
26147c77 | 566 | /// SMMU_NSgIrpt interrupt flags\r |
731c67e1 | 567 | UINT32 SMMU_NSgIrptFlags;\r |
26147c77 | 568 | /// GSIV of the SMMU_NSgCfgIrpt interrupt\r |
731c67e1 | 569 | UINT32 SMMU_NSgCfgIrpt;\r |
26147c77 | 570 | /// SMMU_NSgCfgIrpt interrupt flags\r |
731c67e1 | 571 | UINT32 SMMU_NSgCfgIrptFlags;\r |
26147c77 SM |
572 | } CM_ARM_SMMUV1_SMMUV2_NODE;\r |
573 | \r | |
574 | /** A structure that describes the\r | |
575 | SMMUv3 node for the Platform.\r | |
c606f472 SM |
576 | \r |
577 | ID: EArmObjSmmuV3\r | |
26147c77 SM |
578 | */\r |
579 | typedef struct CmArmSmmuV3Node {\r | |
c606f472 | 580 | /// An unique token used to identify this object\r |
731c67e1 | 581 | CM_OBJECT_TOKEN Token;\r |
26147c77 | 582 | /// Number of ID mappings\r |
731c67e1 | 583 | UINT32 IdMappingCount;\r |
26147c77 | 584 | /// Reference token for the ID mapping array\r |
731c67e1 | 585 | CM_OBJECT_TOKEN IdMappingToken;\r |
26147c77 SM |
586 | \r |
587 | /// SMMU Base Address\r | |
731c67e1 | 588 | UINT64 BaseAddress;\r |
26147c77 | 589 | /// SMMU flags\r |
731c67e1 | 590 | UINT32 Flags;\r |
26147c77 | 591 | /// VATOS address\r |
731c67e1 | 592 | UINT64 VatosAddress;\r |
26147c77 | 593 | /// Model\r |
731c67e1 | 594 | UINT32 Model;\r |
26147c77 | 595 | /// GSIV of the Event interrupt if SPI based\r |
731c67e1 | 596 | UINT32 EventInterrupt;\r |
26147c77 | 597 | /// PRI Interrupt if SPI based\r |
731c67e1 | 598 | UINT32 PriInterrupt;\r |
26147c77 | 599 | /// GERR interrupt if GSIV based\r |
731c67e1 | 600 | UINT32 GerrInterrupt;\r |
26147c77 | 601 | /// Sync interrupt if GSIV based\r |
731c67e1 | 602 | UINT32 SyncInterrupt;\r |
26147c77 SM |
603 | \r |
604 | /// Proximity domain flag\r | |
731c67e1 | 605 | UINT32 ProximityDomain;\r |
26147c77 | 606 | /// Index into the array of ID mapping\r |
731c67e1 | 607 | UINT32 DeviceIdMappingIndex;\r |
26147c77 SM |
608 | } CM_ARM_SMMUV3_NODE;\r |
609 | \r | |
610 | /** A structure that describes the\r | |
611 | PMCG node for the Platform.\r | |
c606f472 SM |
612 | \r |
613 | ID: EArmObjPmcg\r | |
26147c77 SM |
614 | */\r |
615 | typedef struct CmArmPmcgNode {\r | |
c606f472 | 616 | /// An unique token used to identify this object\r |
731c67e1 | 617 | CM_OBJECT_TOKEN Token;\r |
26147c77 | 618 | /// Number of ID mappings\r |
731c67e1 | 619 | UINT32 IdMappingCount;\r |
26147c77 | 620 | /// Reference token for the ID mapping array\r |
731c67e1 | 621 | CM_OBJECT_TOKEN IdMappingToken;\r |
26147c77 SM |
622 | \r |
623 | /// Base Address for performance monitor counter group\r | |
731c67e1 | 624 | UINT64 BaseAddress;\r |
26147c77 | 625 | /// GSIV for the Overflow interrupt\r |
731c67e1 | 626 | UINT32 OverflowInterrupt;\r |
26147c77 | 627 | /// Page 1 Base address\r |
731c67e1 | 628 | UINT64 Page1BaseAddress;\r |
26147c77 SM |
629 | \r |
630 | /// Reference token for the IORT node associated with this node\r | |
731c67e1 | 631 | CM_OBJECT_TOKEN ReferenceToken;\r |
26147c77 SM |
632 | } CM_ARM_PMCG_NODE;\r |
633 | \r | |
cc00dbcb PG |
634 | /** A structure that describes the\r |
635 | GIC ITS Identifiers for an ITS Group node.\r | |
636 | \r | |
637 | ID: EArmObjGicItsIdentifierArray\r | |
638 | */\r | |
639 | typedef struct CmArmGicItsIdentifier {\r | |
640 | /// The ITS Identifier\r | |
731c67e1 | 641 | UINT32 ItsId;\r |
cc00dbcb PG |
642 | } CM_ARM_ITS_IDENTIFIER;\r |
643 | \r | |
26147c77 SM |
644 | /** A structure that describes the\r |
645 | ID Mappings for the Platform.\r | |
c606f472 SM |
646 | \r |
647 | ID: EArmObjIdMappingArray\r | |
26147c77 SM |
648 | */\r |
649 | typedef struct CmArmIdMapping {\r | |
650 | /// Input base\r | |
731c67e1 | 651 | UINT32 InputBase;\r |
26147c77 | 652 | /// Number of input IDs\r |
731c67e1 | 653 | UINT32 NumIds;\r |
26147c77 | 654 | /// Output Base\r |
731c67e1 | 655 | UINT32 OutputBase;\r |
26147c77 | 656 | /// Reference token for the output node\r |
731c67e1 | 657 | CM_OBJECT_TOKEN OutputReferenceToken;\r |
26147c77 | 658 | /// Flags\r |
731c67e1 | 659 | UINT32 Flags;\r |
26147c77 SM |
660 | } CM_ARM_ID_MAPPING;\r |
661 | \r | |
37568365 PG |
662 | /** A structure that describes the Arm\r |
663 | Generic Interrupts.\r | |
26147c77 | 664 | */\r |
37568365 | 665 | typedef struct CmArmGenericInterrupt {\r |
26147c77 SM |
666 | /// Interrupt number\r |
667 | UINT32 Interrupt;\r | |
668 | \r | |
669 | /// Flags\r | |
670 | UINT32 Flags;\r | |
37568365 PG |
671 | } CM_ARM_GENERIC_INTERRUPT;\r |
672 | \r | |
673 | /** A structure that describes the SMMU interrupts for the Platform.\r | |
674 | \r | |
675 | Interrupt Interrupt number.\r | |
676 | Flags Interrupt flags as defined for SMMU node.\r | |
677 | \r | |
678 | ID: EArmObjSmmuInterruptArray\r | |
679 | */\r | |
680 | typedef CM_ARM_GENERIC_INTERRUPT CM_ARM_SMMU_INTERRUPT;\r | |
681 | \r | |
682 | /** A structure that describes the AML Extended Interrupts.\r | |
683 | \r | |
684 | Interrupt Interrupt number.\r | |
685 | Flags Interrupt flags as defined by the Interrupt\r | |
686 | Vector Flags (Byte 3) of the Extended Interrupt\r | |
687 | resource descriptor.\r | |
688 | See EFI_ACPI_EXTENDED_INTERRUPT_FLAG_xxx in Acpi10.h\r | |
37568365 PG |
689 | */\r |
690 | typedef CM_ARM_GENERIC_INTERRUPT CM_ARM_EXTENDED_INTERRUPT;\r | |
26147c77 | 691 | \r |
77db1156 KK |
692 | /** A structure that describes the Processor Hierarchy Node (Type 0) in PPTT\r |
693 | \r | |
694 | ID: EArmObjProcHierarchyInfo\r | |
695 | */\r | |
696 | typedef struct CmArmProcHierarchyInfo {\r | |
697 | /// A unique token used to identify this object\r | |
731c67e1 | 698 | CM_OBJECT_TOKEN Token;\r |
77db1156 | 699 | /// Processor structure flags (ACPI 6.3 - January 2019, PPTT, Table 5-155)\r |
731c67e1 | 700 | UINT32 Flags;\r |
77db1156 KK |
701 | /// Token for the parent CM_ARM_PROC_HIERARCHY_INFO object in the processor\r |
702 | /// topology. A value of CM_NULL_TOKEN means this node has no parent.\r | |
731c67e1 | 703 | CM_OBJECT_TOKEN ParentToken;\r |
77db1156 KK |
704 | /// Token of the associated CM_ARM_GICC_INFO object which has the\r |
705 | /// corresponding ACPI Processor ID. A value of CM_NULL_TOKEN means this\r | |
706 | /// node represents a group of associated processors and it does not have an\r | |
707 | /// associated GIC CPU interface.\r | |
731c67e1 | 708 | CM_OBJECT_TOKEN GicCToken;\r |
77db1156 | 709 | /// Number of resources private to this Node\r |
731c67e1 | 710 | UINT32 NoOfPrivateResources;\r |
77db1156 KK |
711 | /// Token of the array which contains references to the resources private to\r |
712 | /// this CM_ARM_PROC_HIERARCHY_INFO instance. This field is ignored if\r | |
e3f8605a | 713 | /// the NoOfPrivateResources is 0, in which case it is recommended to set\r |
77db1156 | 714 | /// this field to CM_NULL_TOKEN.\r |
731c67e1 | 715 | CM_OBJECT_TOKEN PrivateResourcesArrayToken;\r |
f17ef10e PG |
716 | /// Optional field: Reference Token for the Lpi state of this processor.\r |
717 | /// Token identifying a CM_ARM_OBJ_REF structure, itself referencing\r | |
718 | /// CM_ARM_LPI_INFO objects.\r | |
731c67e1 | 719 | CM_OBJECT_TOKEN LpiToken;\r |
77db1156 KK |
720 | } CM_ARM_PROC_HIERARCHY_INFO;\r |
721 | \r | |
722 | /** A structure that describes the Cache Type Structure (Type 1) in PPTT\r | |
723 | \r | |
724 | ID: EArmObjCacheInfo\r | |
725 | */\r | |
726 | typedef struct CmArmCacheInfo {\r | |
727 | /// A unique token used to identify this object\r | |
731c67e1 | 728 | CM_OBJECT_TOKEN Token;\r |
77db1156 KK |
729 | /// Reference token for the next level of cache that is private to the same\r |
730 | /// CM_ARM_PROC_HIERARCHY_INFO instance. A value of CM_NULL_TOKEN means this\r | |
731 | /// entry represents the last cache level appropriate to the processor\r | |
732 | /// hierarchy node structures using this entry.\r | |
731c67e1 | 733 | CM_OBJECT_TOKEN NextLevelOfCacheToken;\r |
77db1156 | 734 | /// Size of the cache in bytes\r |
731c67e1 | 735 | UINT32 Size;\r |
77db1156 | 736 | /// Number of sets in the cache\r |
731c67e1 | 737 | UINT32 NumberOfSets;\r |
77db1156 KK |
738 | /// Integer number of ways. The maximum associativity supported by\r |
739 | /// ACPI Cache type structure is limited to MAX_UINT8. However,\r | |
740 | /// the maximum number of ways supported by the architecture is\r | |
741 | /// PPTT_ARM_CCIDX_CACHE_ASSOCIATIVITY_MAX. Therfore this field\r | |
742 | /// is 32-bit wide.\r | |
731c67e1 | 743 | UINT32 Associativity;\r |
77db1156 | 744 | /// Cache attributes (ACPI 6.3 - January 2019, PPTT, Table 5-156)\r |
731c67e1 | 745 | UINT8 Attributes;\r |
77db1156 | 746 | /// Line size in bytes\r |
731c67e1 | 747 | UINT16 LineSize;\r |
77db1156 KK |
748 | } CM_ARM_CACHE_INFO;\r |
749 | \r | |
77db1156 KK |
750 | /** A structure that describes a reference to another Configuration Manager\r |
751 | object.\r | |
752 | \r | |
753 | This is useful for creating an array of reference tokens. The framework\r | |
754 | can then query the configuration manager for these arrays using the\r | |
755 | object ID EArmObjCmRef.\r | |
756 | \r | |
757 | This can be used is to represent one-to-many relationships between objects.\r | |
758 | \r | |
759 | ID: EArmObjCmRef\r | |
760 | */\r | |
761 | typedef struct CmArmObjRef {\r | |
762 | /// Token of the CM object being referenced\r | |
731c67e1 | 763 | CM_OBJECT_TOKEN ReferenceToken;\r |
77db1156 KK |
764 | } CM_ARM_OBJ_REF;\r |
765 | \r | |
f413d9be SM |
766 | /** A structure that describes the Memory Affinity Structure (Type 1) in SRAT\r |
767 | \r | |
768 | ID: EArmObjMemoryAffinityInfo\r | |
769 | */\r | |
770 | typedef struct CmArmMemoryAffinityInfo {\r | |
771 | /// The proximity domain to which the "range of memory" belongs.\r | |
731c67e1 | 772 | UINT32 ProximityDomain;\r |
f413d9be SM |
773 | \r |
774 | /// Base Address\r | |
731c67e1 | 775 | UINT64 BaseAddress;\r |
f413d9be SM |
776 | \r |
777 | /// Length\r | |
731c67e1 | 778 | UINT64 Length;\r |
f413d9be SM |
779 | \r |
780 | /// Flags\r | |
731c67e1 | 781 | UINT32 Flags;\r |
f413d9be SM |
782 | } CM_ARM_MEMORY_AFFINITY_INFO;\r |
783 | \r | |
784 | /** A structure that describes the ACPI Device Handle (Type 0) in the\r | |
785 | Generic Initiator Affinity structure in SRAT\r | |
786 | \r | |
787 | ID: EArmObjDeviceHandleAcpi\r | |
788 | */\r | |
789 | typedef struct CmArmDeviceHandleAcpi {\r | |
790 | /// Hardware ID\r | |
731c67e1 | 791 | UINT64 Hid;\r |
f413d9be SM |
792 | \r |
793 | /// Unique Id\r | |
731c67e1 | 794 | UINT32 Uid;\r |
f413d9be SM |
795 | } CM_ARM_DEVICE_HANDLE_ACPI;\r |
796 | \r | |
797 | /** A structure that describes the PCI Device Handle (Type 1) in the\r | |
798 | Generic Initiator Affinity structure in SRAT\r | |
799 | \r | |
800 | ID: EArmObjDeviceHandlePci\r | |
801 | */\r | |
802 | typedef struct CmArmDeviceHandlePci {\r | |
803 | /// PCI Segment Number\r | |
731c67e1 | 804 | UINT16 SegmentNumber;\r |
f413d9be SM |
805 | \r |
806 | /// PCI Bus Number - Max 256 busses (Bits 15:8 of BDF)\r | |
731c67e1 | 807 | UINT8 BusNumber;\r |
f413d9be | 808 | \r |
e3f8605a | 809 | /// PCI Device Number - Max 32 devices (Bits 7:3 of BDF)\r |
731c67e1 | 810 | UINT8 DeviceNumber;\r |
f413d9be SM |
811 | \r |
812 | /// PCI Function Number - Max 8 functions (Bits 2:0 of BDF)\r | |
731c67e1 | 813 | UINT8 FunctionNumber;\r |
f413d9be SM |
814 | } CM_ARM_DEVICE_HANDLE_PCI;\r |
815 | \r | |
816 | /** A structure that describes the Generic Initiator Affinity structure in SRAT\r | |
817 | \r | |
818 | ID: EArmObjGenericInitiatorAffinityInfo\r | |
819 | */\r | |
820 | typedef struct CmArmGenericInitiatorAffinityInfo {\r | |
821 | /// The proximity domain to which the generic initiator belongs.\r | |
731c67e1 | 822 | UINT32 ProximityDomain;\r |
f413d9be SM |
823 | \r |
824 | /// Flags\r | |
731c67e1 | 825 | UINT32 Flags;\r |
f413d9be SM |
826 | \r |
827 | /// Device Handle Type\r | |
731c67e1 | 828 | UINT8 DeviceHandleType;\r |
f413d9be SM |
829 | \r |
830 | /// Reference Token for the Device Handle\r | |
731c67e1 | 831 | CM_OBJECT_TOKEN DeviceHandleToken;\r |
f413d9be SM |
832 | } CM_ARM_GENERIC_INITIATOR_AFFINITY_INFO;\r |
833 | \r | |
37568365 PG |
834 | /** A structure that describes the CMN-600 hardware.\r |
835 | \r | |
836 | ID: EArmObjCmn600Info\r | |
837 | */\r | |
838 | typedef struct CmArmCmn600Info {\r | |
839 | /// The PERIPHBASE address.\r | |
840 | /// Corresponds to the Configuration Node Region (CFGR) base address.\r | |
731c67e1 | 841 | UINT64 PeriphBaseAddress;\r |
37568365 PG |
842 | \r |
843 | /// The PERIPHBASE address length.\r | |
844 | /// Corresponds to the CFGR base address length.\r | |
731c67e1 | 845 | UINT64 PeriphBaseAddressLength;\r |
37568365 PG |
846 | \r |
847 | /// The ROOTNODEBASE address.\r | |
848 | /// Corresponds to the Root node (ROOT) base address.\r | |
731c67e1 | 849 | UINT64 RootNodeBaseAddress;\r |
37568365 PG |
850 | \r |
851 | /// The Debug and Trace Logic Controller (DTC) count.\r | |
852 | /// CMN-600 can have maximum 4 DTCs.\r | |
731c67e1 | 853 | UINT8 DtcCount;\r |
37568365 PG |
854 | \r |
855 | /// DTC Interrupt list.\r | |
856 | /// The first interrupt resource descriptor pertains to\r | |
857 | /// DTC[0], the second to DTC[1] and so on.\r | |
858 | /// DtcCount determines the number of DTC Interrupts that\r | |
859 | /// are populated. If DTC count is 2 then DtcInterrupt[2]\r | |
860 | /// and DtcInterrupt[3] are ignored.\r | |
861 | /// Note: The size of CM_ARM_CMN_600_INFO structure remains\r | |
862 | /// constant and does not vary with the DTC count.\r | |
731c67e1 | 863 | CM_ARM_EXTENDED_INTERRUPT DtcInterrupt[4];\r |
37568365 PG |
864 | } CM_ARM_CMN_600_INFO;\r |
865 | \r | |
f17ef10e PG |
866 | /** A structure that describes the Lpi information.\r |
867 | \r | |
868 | The Low Power Idle states are described in DSDT/SSDT and associated\r | |
869 | to cpus/clusters in the cpu topology.\r | |
870 | \r | |
871 | ID: EArmObjLpiInfo\r | |
872 | */\r | |
873 | typedef struct CmArmLpiInfo {\r | |
874 | /** Minimum Residency. Time in microseconds after which a\r | |
875 | state becomes more energy efficient than any shallower state.\r | |
876 | */\r | |
731c67e1 | 877 | UINT32 MinResidency;\r |
f17ef10e PG |
878 | \r |
879 | /** Worst case time in microseconds from a wake interrupt\r | |
880 | being asserted to the return to a running state\r | |
881 | */\r | |
731c67e1 | 882 | UINT32 WorstCaseWakeLatency;\r |
f17ef10e PG |
883 | \r |
884 | /** Flags.\r | |
885 | */\r | |
731c67e1 | 886 | UINT32 Flags;\r |
f17ef10e PG |
887 | \r |
888 | /** Architecture specific context loss flags.\r | |
889 | */\r | |
731c67e1 | 890 | UINT32 ArchFlags;\r |
f17ef10e PG |
891 | \r |
892 | /** Residency counter frequency in cycles-per-second (Hz).\r | |
893 | */\r | |
731c67e1 | 894 | UINT32 ResCntFreq;\r |
f17ef10e PG |
895 | \r |
896 | /** Every shallower power state in the parent is also enabled.\r | |
897 | */\r | |
731c67e1 | 898 | UINT32 EnableParentState;\r |
f17ef10e PG |
899 | \r |
900 | /** The EntryMethod _LPI field can be described as an integer\r | |
901 | or in a Register resource data descriptor.\r | |
902 | \r | |
903 | If IsInteger is TRUE, the IntegerEntryMethod field is used.\r | |
904 | If IsInteger is FALSE, the RegisterEntryMethod field is used.\r | |
905 | */\r | |
731c67e1 | 906 | BOOLEAN IsInteger;\r |
f17ef10e PG |
907 | \r |
908 | /** EntryMethod described as an Integer.\r | |
909 | */\r | |
731c67e1 | 910 | UINT64 IntegerEntryMethod;\r |
f17ef10e PG |
911 | \r |
912 | /** EntryMethod described as a EFI_ACPI_GENERIC_REGISTER_DESCRIPTOR.\r | |
913 | */\r | |
731c67e1 | 914 | EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE RegisterEntryMethod;\r |
f17ef10e PG |
915 | \r |
916 | /** Residency counter register.\r | |
917 | */\r | |
731c67e1 | 918 | EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE ResidencyCounterRegister;\r |
f17ef10e PG |
919 | \r |
920 | /** Usage counter register.\r | |
921 | */\r | |
731c67e1 | 922 | EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE UsageCounterRegister;\r |
f17ef10e PG |
923 | \r |
924 | /** String representing the Lpi state\r | |
925 | */\r | |
731c67e1 | 926 | CHAR8 StateName[16];\r |
f17ef10e PG |
927 | } CM_ARM_LPI_INFO;\r |
928 | \r | |
26147c77 SM |
929 | #pragma pack()\r |
930 | \r | |
931 | #endif // ARM_NAMESPACE_OBJECTS_H_\r |