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3eb9473e | 1 | /*++\r |
2 | \r | |
3 | Copyright (c) 2004 - 2006, Intel Corporation \r | |
4 | All rights reserved. This program and the accompanying materials \r | |
5 | are licensed and made available under the terms and conditions of the BSD License \r | |
6 | which accompanies this distribution. The full text of the license may be found at \r | |
7 | http://opensource.org/licenses/bsd-license.php \r | |
8 | \r | |
9 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r | |
10 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r | |
11 | \r | |
12 | Module name:\r | |
13 | \r | |
14 | EfiPxe.h\r | |
15 | \r | |
16 | 32/64-bit PXE specification:\r | |
17 | \r | |
18 | alpha-4, 99-Dec-17\r | |
19 | \r | |
20 | Abstract:\r | |
21 | \r | |
22 | This header file contains all of the PXE type definitions,\r | |
23 | structure prototypes, global variables and constants that\r | |
24 | are needed for porting PXE to EFI.\r | |
25 | --*/\r | |
26 | \r | |
27 | #ifndef _EFIPXE_H\r | |
28 | #define _EFIPXE_H\r | |
29 | \r | |
30 | #pragma pack(1)\r | |
31 | \r | |
32 | #define PXE_INTEL_ORDER 1 // Intel order\r | |
33 | // #define PXE_NETWORK_ORDER 1 // network order\r | |
34 | //\r | |
35 | #define PXE_UINT64_SUPPORT 1 // UINT64 supported\r | |
4cb43192 | 36 | #if PXE_UINT64_SUPPORT == 0\r |
37 | #define PXE_NO_UINT64_SUPPORT 1\r | |
38 | #else\r | |
39 | #define PXE_NO_UINT64_SUPPORT 0\r | |
40 | #endif\r | |
3eb9473e | 41 | //\r |
42 | #define PXE_BUSTYPE(a, b, c, d) \\r | |
43 | ( \\r | |
44 | (((UINT32) (d) & 0xFF) << 24) | (((UINT32) (c) & 0xFF) << 16) | (((UINT32) (b) & 0xFF) << 8) | \\r | |
45 | ((UINT32) (a) & 0xFF) \\r | |
46 | )\r | |
47 | \r | |
48 | //\r | |
49 | // UNDI ROM ID and devive ID signature\r | |
50 | //\r | |
51 | #define PXE_BUSTYPE_PXE PXE_BUSTYPE ('!', 'P', 'X', 'E')\r | |
52 | \r | |
53 | //\r | |
54 | // BUS ROM ID signatures\r | |
55 | //\r | |
56 | #define PXE_BUSTYPE_PCI PXE_BUSTYPE ('P', 'C', 'I', 'R')\r | |
57 | #define PXE_BUSTYPE_PC_CARD PXE_BUSTYPE ('P', 'C', 'C', 'R')\r | |
58 | #define PXE_BUSTYPE_USB PXE_BUSTYPE ('U', 'S', 'B', 'R')\r | |
59 | #define PXE_BUSTYPE_1394 PXE_BUSTYPE ('1', '3', '9', '4')\r | |
60 | \r | |
61 | #define PXE_SWAP_UINT16(n) ((((UINT16) (n) & 0x00FF) << 8) | (((UINT16) (n) & 0xFF00) >> 8))\r | |
62 | \r | |
63 | #define PXE_SWAP_UINT32(n) \\r | |
64 | ((((UINT32)(n) & 0x000000FF) << 24) | \\r | |
65 | (((UINT32)(n) & 0x0000FF00) << 8) | \\r | |
66 | (((UINT32)(n) & 0x00FF0000) >> 8) | \\r | |
67 | (((UINT32)(n) & 0xFF000000) >> 24))\r | |
68 | \r | |
69 | #if PXE_UINT64_SUPPORT != 0\r | |
70 | #define PXE_SWAP_UINT64(n) \\r | |
71 | ((((UINT64)(n) & 0x00000000000000FF) << 56) | \\r | |
72 | (((UINT64)(n) & 0x000000000000FF00) << 40) | \\r | |
73 | (((UINT64)(n) & 0x0000000000FF0000) << 24) | \\r | |
74 | (((UINT64)(n) & 0x00000000FF000000) << 8) | \\r | |
75 | (((UINT64)(n) & 0x000000FF00000000) >> 8) | \\r | |
76 | (((UINT64)(n) & 0x0000FF0000000000) >> 24) | \\r | |
77 | (((UINT64)(n) & 0x00FF000000000000) >> 40) | \\r | |
78 | (((UINT64)(n) & 0xFF00000000000000) >> 56))\r | |
79 | #endif // PXE_UINT64_SUPPORT\r | |
80 | #if PXE_NO_UINT64_SUPPORT != 0\r | |
81 | #define PXE_SWAP_UINT64(n) { \\r | |
82 | UINT32 tmp; \\r | |
83 | tmp = (PXE_UINT64) (n)[1]; \\r | |
84 | (UINT64) (n)[1] = PXE_SWAP_UINT32 ((UINT64) (n)[0]); \\r | |
85 | (UINT64) (n)[0] = tmp; \\r | |
86 | }\r | |
87 | #endif // PXE_NO_UINT64_SUPPORT\r | |
88 | #define PXE_CPBSIZE_NOT_USED 0 // zero\r | |
89 | #define PXE_DBSIZE_NOT_USED 0 // zero\r | |
90 | #define PXE_CPBADDR_NOT_USED (PXE_UINT64) 0 // zero\r | |
91 | #define PXE_DBADDR_NOT_USED (PXE_UINT64) 0 // zero\r | |
92 | #define PXE_CONST const\r | |
93 | \r | |
94 | #define PXE_VOLATILE volatile\r | |
95 | \r | |
96 | #if PXE_UINT64_SUPPORT != 0\r | |
97 | //\r | |
98 | // typedef unsigned long PXE_UINT64;\r | |
99 | //\r | |
100 | typedef UINT64 PXE_UINT64;\r | |
101 | #endif // PXE_UINT64_SUPPORT\r | |
102 | #if PXE_NO_UINT64_SUPPORT != 0\r | |
103 | typedef PXE_UINT32 PXE_UINT64[2];\r | |
104 | #endif // PXE_NO_UINT64_SUPPORT\r | |
105 | #define PXE_FALSE 0 // zero\r | |
106 | #define PXE_TRUE (!PXE_FALSE)\r | |
107 | \r | |
108 | typedef UINT16 PXE_OPCODE;\r | |
109 | \r | |
110 | //\r | |
111 | // Return UNDI operational state.\r | |
112 | //\r | |
113 | #define PXE_OPCODE_GET_STATE 0x0000\r | |
114 | \r | |
115 | //\r | |
116 | // Change UNDI operational state from Stopped to Started.\r | |
117 | //\r | |
118 | #define PXE_OPCODE_START 0x0001\r | |
119 | \r | |
120 | //\r | |
121 | // Change UNDI operational state from Started to Stopped.\r | |
122 | //\r | |
123 | #define PXE_OPCODE_STOP 0x0002\r | |
124 | \r | |
125 | //\r | |
126 | // Get UNDI initialization information.\r | |
127 | //\r | |
128 | #define PXE_OPCODE_GET_INIT_INFO 0x0003\r | |
129 | \r | |
130 | //\r | |
131 | // Get NIC configuration information.\r | |
132 | //\r | |
133 | #define PXE_OPCODE_GET_CONFIG_INFO 0x0004\r | |
134 | \r | |
135 | //\r | |
136 | // Changed UNDI operational state from Started to Initialized.\r | |
137 | //\r | |
138 | #define PXE_OPCODE_INITIALIZE 0x0005\r | |
139 | \r | |
140 | //\r | |
141 | // Re-initialize the NIC H/W.\r | |
142 | //\r | |
143 | #define PXE_OPCODE_RESET 0x0006\r | |
144 | \r | |
145 | //\r | |
146 | // Change the UNDI operational state from Initialized to Started.\r | |
147 | //\r | |
148 | #define PXE_OPCODE_SHUTDOWN 0x0007\r | |
149 | \r | |
150 | //\r | |
151 | // Read & change state of external interrupt enables.\r | |
152 | //\r | |
153 | #define PXE_OPCODE_INTERRUPT_ENABLES 0x0008\r | |
154 | \r | |
155 | //\r | |
156 | // Read & change state of packet receive filters.\r | |
157 | //\r | |
158 | #define PXE_OPCODE_RECEIVE_FILTERS 0x0009\r | |
159 | \r | |
160 | //\r | |
161 | // Read & change station MAC address.\r | |
162 | //\r | |
163 | #define PXE_OPCODE_STATION_ADDRESS 0x000A\r | |
164 | \r | |
165 | //\r | |
166 | // Read traffic statistics.\r | |
167 | //\r | |
168 | #define PXE_OPCODE_STATISTICS 0x000B\r | |
169 | \r | |
170 | //\r | |
171 | // Convert multicast IP address to multicast MAC address.\r | |
172 | //\r | |
173 | #define PXE_OPCODE_MCAST_IP_TO_MAC 0x000C\r | |
174 | \r | |
175 | //\r | |
176 | // Read or change non-volatile storage on the NIC.\r | |
177 | //\r | |
178 | #define PXE_OPCODE_NVDATA 0x000D\r | |
179 | \r | |
180 | //\r | |
181 | // Get & clear interrupt status.\r | |
182 | //\r | |
183 | #define PXE_OPCODE_GET_STATUS 0x000E\r | |
184 | \r | |
185 | //\r | |
186 | // Fill media header in packet for transmit.\r | |
187 | //\r | |
188 | #define PXE_OPCODE_FILL_HEADER 0x000F\r | |
189 | \r | |
190 | //\r | |
191 | // Transmit packet(s).\r | |
192 | //\r | |
193 | #define PXE_OPCODE_TRANSMIT 0x0010\r | |
194 | \r | |
195 | //\r | |
196 | // Receive packet.\r | |
197 | //\r | |
198 | #define PXE_OPCODE_RECEIVE 0x0011\r | |
199 | \r | |
200 | //\r | |
201 | // last valid opcode:\r | |
202 | //\r | |
203 | #define PXE_OPCODE_VALID_MAX 0x0011\r | |
204 | \r | |
205 | //\r | |
206 | // Last valid PXE UNDI OpCode number.\r | |
207 | //\r | |
208 | #define PXE_OPCODE_LAST_VALID 0x0011\r | |
209 | \r | |
210 | typedef UINT16 PXE_OPFLAGS;\r | |
211 | \r | |
212 | #define PXE_OPFLAGS_NOT_USED 0x0000\r | |
213 | \r | |
214 | //\r | |
215 | // //////////////////////////////////////\r | |
216 | // UNDI Get State\r | |
217 | //\r | |
218 | // No OpFlags\r | |
219 | \r | |
220 | ////////////////////////////////////////\r | |
221 | // UNDI Start\r | |
222 | //\r | |
223 | // No OpFlags\r | |
224 | \r | |
225 | ////////////////////////////////////////\r | |
226 | // UNDI Stop\r | |
227 | //\r | |
228 | // No OpFlags\r | |
229 | \r | |
230 | ////////////////////////////////////////\r | |
231 | // UNDI Get Init Info\r | |
232 | //\r | |
233 | // No Opflags\r | |
234 | \r | |
235 | ////////////////////////////////////////\r | |
236 | // UNDI Get Config Info\r | |
237 | //\r | |
238 | // No Opflags\r | |
239 | \r | |
240 | ////////////////////////////////////////\r | |
241 | // UNDI Initialize\r | |
242 | //\r | |
243 | #define PXE_OPFLAGS_INITIALIZE_CABLE_DETECT_MASK 0x0001\r | |
244 | #define PXE_OPFLAGS_INITIALIZE_DETECT_CABLE 0x0000\r | |
245 | #define PXE_OPFLAGS_INITIALIZE_DO_NOT_DETECT_CABLE 0x0001\r | |
246 | \r | |
247 | //\r | |
248 | // //////////////////////////////////////\r | |
249 | // UNDI Reset\r | |
250 | //\r | |
251 | #define PXE_OPFLAGS_RESET_DISABLE_INTERRUPTS 0x0001\r | |
252 | #define PXE_OPFLAGS_RESET_DISABLE_FILTERS 0x0002\r | |
253 | \r | |
254 | //\r | |
255 | // //////////////////////////////////////\r | |
256 | // UNDI Shutdown\r | |
257 | //\r | |
258 | // No OpFlags\r | |
259 | \r | |
260 | ////////////////////////////////////////\r | |
261 | // UNDI Interrupt Enables\r | |
262 | //\r | |
263 | //\r | |
264 | // Select whether to enable or disable external interrupt signals.\r | |
265 | // Setting both enable and disable will return PXE_STATCODE_INVALID_OPFLAGS.\r | |
266 | //\r | |
267 | #define PXE_OPFLAGS_INTERRUPT_OPMASK 0xC000\r | |
268 | #define PXE_OPFLAGS_INTERRUPT_ENABLE 0x8000\r | |
269 | #define PXE_OPFLAGS_INTERRUPT_DISABLE 0x4000\r | |
270 | #define PXE_OPFLAGS_INTERRUPT_READ 0x0000\r | |
271 | \r | |
272 | //\r | |
273 | // Enable receive interrupts. An external interrupt will be generated\r | |
274 | // after a complete non-error packet has been received.\r | |
275 | //\r | |
276 | #define PXE_OPFLAGS_INTERRUPT_RECEIVE 0x0001\r | |
277 | \r | |
278 | //\r | |
279 | // Enable transmit interrupts. An external interrupt will be generated\r | |
280 | // after a complete non-error packet has been transmitted.\r | |
281 | //\r | |
282 | #define PXE_OPFLAGS_INTERRUPT_TRANSMIT 0x0002\r | |
283 | \r | |
284 | //\r | |
285 | // Enable command interrupts. An external interrupt will be generated\r | |
286 | // when command execution stops.\r | |
287 | //\r | |
288 | #define PXE_OPFLAGS_INTERRUPT_COMMAND 0x0004\r | |
289 | \r | |
290 | //\r | |
291 | // Generate software interrupt. Setting this bit generates an external\r | |
292 | // interrupt, if it is supported by the hardware.\r | |
293 | //\r | |
294 | #define PXE_OPFLAGS_INTERRUPT_SOFTWARE 0x0008\r | |
295 | \r | |
296 | //\r | |
297 | // //////////////////////////////////////\r | |
298 | // UNDI Receive Filters\r | |
299 | //\r | |
300 | //\r | |
301 | // Select whether to enable or disable receive filters.\r | |
302 | // Setting both enable and disable will return PXE_STATCODE_INVALID_OPCODE.\r | |
303 | //\r | |
304 | #define PXE_OPFLAGS_RECEIVE_FILTER_OPMASK 0xC000\r | |
305 | #define PXE_OPFLAGS_RECEIVE_FILTER_ENABLE 0x8000\r | |
306 | #define PXE_OPFLAGS_RECEIVE_FILTER_DISABLE 0x4000\r | |
307 | #define PXE_OPFLAGS_RECEIVE_FILTER_READ 0x0000\r | |
308 | \r | |
309 | //\r | |
310 | // To reset the contents of the multicast MAC address filter list,\r | |
311 | // set this OpFlag:\r | |
312 | //\r | |
313 | #define PXE_OPFLAGS_RECEIVE_FILTER_RESET_MCAST_LIST 0x2000\r | |
314 | \r | |
315 | //\r | |
316 | // Enable unicast packet receiving. Packets sent to the current station\r | |
317 | // MAC address will be received.\r | |
318 | //\r | |
319 | #define PXE_OPFLAGS_RECEIVE_FILTER_UNICAST 0x0001\r | |
320 | \r | |
321 | //\r | |
322 | // Enable broadcast packet receiving. Packets sent to the broadcast\r | |
323 | // MAC address will be received.\r | |
324 | //\r | |
325 | #define PXE_OPFLAGS_RECEIVE_FILTER_BROADCAST 0x0002\r | |
326 | \r | |
327 | //\r | |
328 | // Enable filtered multicast packet receiving. Packets sent to any\r | |
329 | // of the multicast MAC addresses in the multicast MAC address filter\r | |
330 | // list will be received. If the filter list is empty, no multicast\r | |
331 | //\r | |
332 | #define PXE_OPFLAGS_RECEIVE_FILTER_FILTERED_MULTICAST 0x0004\r | |
333 | \r | |
334 | //\r | |
335 | // Enable promiscuous packet receiving. All packets will be received.\r | |
336 | //\r | |
337 | #define PXE_OPFLAGS_RECEIVE_FILTER_PROMISCUOUS 0x0008\r | |
338 | \r | |
339 | //\r | |
340 | // Enable promiscuous multicast packet receiving. All multicast\r | |
341 | // packets will be received.\r | |
342 | //\r | |
343 | #define PXE_OPFLAGS_RECEIVE_FILTER_ALL_MULTICAST 0x0010\r | |
344 | \r | |
345 | //\r | |
346 | // //////////////////////////////////////\r | |
347 | // UNDI Station Address\r | |
348 | //\r | |
349 | #define PXE_OPFLAGS_STATION_ADDRESS_READ 0x0000\r | |
350 | #define PXE_OPFLAGS_STATION_ADDRESS_WRITE 0x0000\r | |
351 | #define PXE_OPFLAGS_STATION_ADDRESS_RESET 0x0001\r | |
352 | \r | |
353 | //\r | |
354 | // //////////////////////////////////////\r | |
355 | // UNDI Statistics\r | |
356 | //\r | |
357 | #define PXE_OPFLAGS_STATISTICS_READ 0x0000\r | |
358 | #define PXE_OPFLAGS_STATISTICS_RESET 0x0001\r | |
359 | \r | |
360 | //\r | |
361 | // //////////////////////////////////////\r | |
362 | // UNDI MCast IP to MAC\r | |
363 | //\r | |
364 | //\r | |
365 | // Identify the type of IP address in the CPB.\r | |
366 | //\r | |
367 | #define PXE_OPFLAGS_MCAST_IP_TO_MAC_OPMASK 0x0003\r | |
368 | #define PXE_OPFLAGS_MCAST_IPV4_TO_MAC 0x0000\r | |
369 | #define PXE_OPFLAGS_MCAST_IPV6_TO_MAC 0x0001\r | |
370 | \r | |
371 | //\r | |
372 | // //////////////////////////////////////\r | |
373 | // UNDI NvData\r | |
374 | //\r | |
375 | //\r | |
376 | // Select the type of non-volatile data operation.\r | |
377 | //\r | |
378 | #define PXE_OPFLAGS_NVDATA_OPMASK 0x0001\r | |
379 | #define PXE_OPFLAGS_NVDATA_READ 0x0000\r | |
380 | #define PXE_OPFLAGS_NVDATA_WRITE 0x0001\r | |
381 | \r | |
382 | //\r | |
383 | // //////////////////////////////////////\r | |
384 | // UNDI Get Status\r | |
385 | //\r | |
386 | //\r | |
387 | // Return current interrupt status. This will also clear any interrupts\r | |
388 | // that are currently set. This can be used in a polling routine. The\r | |
389 | // interrupt flags are still set and cleared even when the interrupts\r | |
390 | // are disabled.\r | |
391 | //\r | |
392 | #define PXE_OPFLAGS_GET_INTERRUPT_STATUS 0x0001\r | |
393 | \r | |
394 | //\r | |
395 | // Return list of transmitted buffers for recycling. Transmit buffers\r | |
396 | // must not be changed or unallocated until they have recycled. After\r | |
397 | // issuing a transmit command, wait for a transmit complete interrupt.\r | |
398 | // When a transmit complete interrupt is received, read the transmitted\r | |
399 | // buffers. Do not plan on getting one buffer per interrupt. Some\r | |
400 | // NICs and UNDIs may transmit multiple buffers per interrupt.\r | |
401 | //\r | |
402 | #define PXE_OPFLAGS_GET_TRANSMITTED_BUFFERS 0x0002\r | |
403 | \r | |
404 | //\r | |
405 | // //////////////////////////////////////\r | |
406 | // UNDI Fill Header\r | |
407 | //\r | |
408 | #define PXE_OPFLAGS_FILL_HEADER_OPMASK 0x0001\r | |
409 | #define PXE_OPFLAGS_FILL_HEADER_FRAGMENTED 0x0001\r | |
410 | #define PXE_OPFLAGS_FILL_HEADER_WHOLE 0x0000\r | |
411 | \r | |
412 | //\r | |
413 | // //////////////////////////////////////\r | |
414 | // UNDI Transmit\r | |
415 | //\r | |
416 | //\r | |
417 | // S/W UNDI only. Return after the packet has been transmitted. A\r | |
418 | // transmit complete interrupt will still be generated and the transmit\r | |
419 | // buffer will have to be recycled.\r | |
420 | //\r | |
421 | #define PXE_OPFLAGS_SWUNDI_TRANSMIT_OPMASK 0x0001\r | |
422 | #define PXE_OPFLAGS_TRANSMIT_BLOCK 0x0001\r | |
423 | #define PXE_OPFLAGS_TRANSMIT_DONT_BLOCK 0x0000\r | |
424 | \r | |
425 | //\r | |
426 | //\r | |
427 | //\r | |
428 | #define PXE_OPFLAGS_TRANSMIT_OPMASK 0x0002\r | |
429 | #define PXE_OPFLAGS_TRANSMIT_FRAGMENTED 0x0002\r | |
430 | #define PXE_OPFLAGS_TRANSMIT_WHOLE 0x0000\r | |
431 | \r | |
432 | //\r | |
433 | // //////////////////////////////////////\r | |
434 | // UNDI Receive\r | |
435 | //\r | |
436 | // No OpFlags\r | |
437 | //\r | |
438 | typedef UINT16 PXE_STATFLAGS;\r | |
439 | \r | |
440 | #define PXE_STATFLAGS_INITIALIZE 0x0000\r | |
441 | \r | |
442 | //\r | |
443 | // //////////////////////////////////////\r | |
444 | // Common StatFlags that can be returned by all commands.\r | |
445 | //\r | |
446 | //\r | |
447 | // The COMMAND_COMPLETE and COMMAND_FAILED status flags must be\r | |
448 | // implemented by all UNDIs. COMMAND_QUEUED is only needed by UNDIs\r | |
449 | // that support command queuing.\r | |
450 | //\r | |
451 | #define PXE_STATFLAGS_STATUS_MASK 0xC000\r | |
452 | #define PXE_STATFLAGS_COMMAND_COMPLETE 0xC000\r | |
453 | #define PXE_STATFLAGS_COMMAND_FAILED 0x8000\r | |
454 | #define PXE_STATFLAGS_COMMAND_QUEUED 0x4000\r | |
455 | //\r | |
456 | // #define PXE_STATFLAGS_INITIALIZE 0x0000\r | |
457 | //\r | |
458 | #define PXE_STATFLAGS_DB_WRITE_TRUNCATED 0x2000\r | |
459 | \r | |
460 | //\r | |
461 | // //////////////////////////////////////\r | |
462 | // UNDI Get State\r | |
463 | //\r | |
464 | #define PXE_STATFLAGS_GET_STATE_MASK 0x0003\r | |
465 | #define PXE_STATFLAGS_GET_STATE_INITIALIZED 0x0002\r | |
466 | #define PXE_STATFLAGS_GET_STATE_STARTED 0x0001\r | |
467 | #define PXE_STATFLAGS_GET_STATE_STOPPED 0x0000\r | |
468 | \r | |
469 | //\r | |
470 | // //////////////////////////////////////\r | |
471 | // UNDI Start\r | |
472 | //\r | |
473 | // No additional StatFlags\r | |
474 | \r | |
475 | ////////////////////////////////////////\r | |
476 | // UNDI Get Init Info\r | |
477 | //\r | |
478 | #define PXE_STATFLAGS_CABLE_DETECT_MASK 0x0001\r | |
479 | #define PXE_STATFLAGS_CABLE_DETECT_NOT_SUPPORTED 0x0000\r | |
480 | #define PXE_STATFLAGS_CABLE_DETECT_SUPPORTED 0x0001\r | |
481 | \r | |
482 | //\r | |
483 | // //////////////////////////////////////\r | |
484 | // UNDI Initialize\r | |
485 | //\r | |
486 | #define PXE_STATFLAGS_INITIALIZED_NO_MEDIA 0x0001\r | |
487 | \r | |
488 | //\r | |
489 | // //////////////////////////////////////\r | |
490 | // UNDI Reset\r | |
491 | //\r | |
492 | #define PXE_STATFLAGS_RESET_NO_MEDIA 0x0001\r | |
493 | \r | |
494 | //\r | |
495 | // //////////////////////////////////////\r | |
496 | // UNDI Shutdown\r | |
497 | //\r | |
498 | // No additional StatFlags\r | |
499 | \r | |
500 | ////////////////////////////////////////\r | |
501 | // UNDI Interrupt Enables\r | |
502 | //\r | |
503 | //\r | |
504 | // If set, receive interrupts are enabled.\r | |
505 | //\r | |
506 | #define PXE_STATFLAGS_INTERRUPT_RECEIVE 0x0001\r | |
507 | \r | |
508 | //\r | |
509 | // If set, transmit interrupts are enabled.\r | |
510 | //\r | |
511 | #define PXE_STATFLAGS_INTERRUPT_TRANSMIT 0x0002\r | |
512 | \r | |
513 | //\r | |
514 | // If set, command interrupts are enabled.\r | |
515 | //\r | |
516 | #define PXE_STATFLAGS_INTERRUPT_COMMAND 0x0004\r | |
517 | \r | |
518 | //\r | |
519 | // //////////////////////////////////////\r | |
520 | // UNDI Receive Filters\r | |
521 | //\r | |
522 | //\r | |
523 | // If set, unicast packets will be received.\r | |
524 | //\r | |
525 | #define PXE_STATFLAGS_RECEIVE_FILTER_UNICAST 0x0001\r | |
526 | \r | |
527 | //\r | |
528 | // If set, broadcast packets will be received.\r | |
529 | //\r | |
530 | #define PXE_STATFLAGS_RECEIVE_FILTER_BROADCAST 0x0002\r | |
531 | \r | |
532 | //\r | |
533 | // If set, multicast packets that match up with the multicast address\r | |
534 | // filter list will be received.\r | |
535 | //\r | |
536 | #define PXE_STATFLAGS_RECEIVE_FILTER_FILTERED_MULTICAST 0x0004\r | |
537 | \r | |
538 | //\r | |
539 | // If set, all packets will be received.\r | |
540 | //\r | |
541 | #define PXE_STATFLAGS_RECEIVE_FILTER_PROMISCUOUS 0x0008\r | |
542 | \r | |
543 | //\r | |
544 | // If set, all multicast packets will be received.\r | |
545 | //\r | |
546 | #define PXE_STATFLAGS_RECEIVE_FILTER_ALL_MULTICAST 0x0010\r | |
547 | \r | |
548 | //\r | |
549 | // //////////////////////////////////////\r | |
550 | // UNDI Station Address\r | |
551 | //\r | |
552 | // No additional StatFlags\r | |
553 | \r | |
554 | ////////////////////////////////////////\r | |
555 | // UNDI Statistics\r | |
556 | //\r | |
557 | // No additional StatFlags\r | |
558 | \r | |
559 | ////////////////////////////////////////\r | |
560 | // UNDI MCast IP to MAC\r | |
561 | //\r | |
562 | // No additional StatFlags\r | |
563 | \r | |
564 | ////////////////////////////////////////\r | |
565 | // UNDI NvData\r | |
566 | //\r | |
567 | // No additional StatFlags\r | |
568 | \r | |
569 | \r | |
570 | ////////////////////////////////////////\r | |
571 | // UNDI Get Status\r | |
572 | //\r | |
573 | //\r | |
574 | // Use to determine if an interrupt has occurred.\r | |
575 | //\r | |
576 | #define PXE_STATFLAGS_GET_STATUS_INTERRUPT_MASK 0x000F\r | |
577 | #define PXE_STATFLAGS_GET_STATUS_NO_INTERRUPTS 0x0000\r | |
578 | \r | |
579 | //\r | |
580 | // If set, at least one receive interrupt occurred.\r | |
581 | //\r | |
582 | #define PXE_STATFLAGS_GET_STATUS_RECEIVE 0x0001\r | |
583 | \r | |
584 | //\r | |
585 | // If set, at least one transmit interrupt occurred.\r | |
586 | //\r | |
587 | #define PXE_STATFLAGS_GET_STATUS_TRANSMIT 0x0002\r | |
588 | \r | |
589 | //\r | |
590 | // If set, at least one command interrupt occurred.\r | |
591 | //\r | |
592 | #define PXE_STATFLAGS_GET_STATUS_COMMAND 0x0004\r | |
593 | \r | |
594 | //\r | |
595 | // If set, at least one software interrupt occurred.\r | |
596 | //\r | |
597 | #define PXE_STATFLAGS_GET_STATUS_SOFTWARE 0x0008\r | |
598 | \r | |
599 | //\r | |
600 | // This flag is set if the transmitted buffer queue is empty. This flag\r | |
601 | // will be set if all transmitted buffer addresses get written into the DB.\r | |
602 | //\r | |
603 | #define PXE_STATFLAGS_GET_STATUS_TXBUF_QUEUE_EMPTY 0x0010\r | |
604 | \r | |
605 | //\r | |
606 | // This flag is set if no transmitted buffer addresses were written\r | |
607 | // into the DB. (This could be because DBsize was too small.)\r | |
608 | //\r | |
609 | #define PXE_STATFLAGS_GET_STATUS_NO_TXBUFS_WRITTEN 0x0020\r | |
610 | \r | |
611 | //\r | |
612 | // //////////////////////////////////////\r | |
613 | // UNDI Fill Header\r | |
614 | //\r | |
615 | // No additional StatFlags\r | |
616 | \r | |
617 | ////////////////////////////////////////\r | |
618 | // UNDI Transmit\r | |
619 | //\r | |
620 | // No additional StatFlags.\r | |
621 | \r | |
622 | ////////////////////////////////////////\r | |
623 | // UNDI Receive\r | |
624 | //\r | |
625 | // No additional StatFlags.\r | |
626 | //\r | |
627 | typedef UINT16 PXE_STATCODE;\r | |
628 | \r | |
629 | #define PXE_STATCODE_INITIALIZE 0x0000\r | |
630 | \r | |
631 | //\r | |
632 | // //////////////////////////////////////\r | |
633 | // Common StatCodes returned by all UNDI commands, UNDI protocol functions\r | |
634 | // and BC protocol functions.\r | |
635 | //\r | |
636 | #define PXE_STATCODE_SUCCESS 0x0000\r | |
637 | \r | |
638 | #define PXE_STATCODE_INVALID_CDB 0x0001\r | |
639 | #define PXE_STATCODE_INVALID_CPB 0x0002\r | |
640 | #define PXE_STATCODE_BUSY 0x0003\r | |
641 | #define PXE_STATCODE_QUEUE_FULL 0x0004\r | |
642 | #define PXE_STATCODE_ALREADY_STARTED 0x0005\r | |
643 | #define PXE_STATCODE_NOT_STARTED 0x0006\r | |
644 | #define PXE_STATCODE_NOT_SHUTDOWN 0x0007\r | |
645 | #define PXE_STATCODE_ALREADY_INITIALIZED 0x0008\r | |
646 | #define PXE_STATCODE_NOT_INITIALIZED 0x0009\r | |
647 | #define PXE_STATCODE_DEVICE_FAILURE 0x000A\r | |
648 | #define PXE_STATCODE_NVDATA_FAILURE 0x000B\r | |
649 | #define PXE_STATCODE_UNSUPPORTED 0x000C\r | |
650 | #define PXE_STATCODE_BUFFER_FULL 0x000D\r | |
651 | #define PXE_STATCODE_INVALID_PARAMETER 0x000E\r | |
652 | #define PXE_STATCODE_INVALID_UNDI 0x000F\r | |
653 | #define PXE_STATCODE_IPV4_NOT_SUPPORTED 0x0010\r | |
654 | #define PXE_STATCODE_IPV6_NOT_SUPPORTED 0x0011\r | |
655 | #define PXE_STATCODE_NOT_ENOUGH_MEMORY 0x0012\r | |
656 | #define PXE_STATCODE_NO_DATA 0x0013\r | |
657 | \r | |
658 | typedef UINT16 PXE_IFNUM;\r | |
659 | \r | |
660 | //\r | |
661 | // This interface number must be passed to the S/W UNDI Start command.\r | |
662 | //\r | |
663 | #define PXE_IFNUM_START 0x0000\r | |
664 | \r | |
665 | //\r | |
666 | // This interface number is returned by the S/W UNDI Get State and\r | |
667 | // Start commands if information in the CDB, CPB or DB is invalid.\r | |
668 | //\r | |
669 | #define PXE_IFNUM_INVALID 0x0000\r | |
670 | \r | |
671 | typedef UINT16 PXE_CONTROL;\r | |
672 | \r | |
673 | //\r | |
674 | // Setting this flag directs the UNDI to queue this command for later\r | |
675 | // execution if the UNDI is busy and it supports command queuing.\r | |
676 | // If queuing is not supported, a PXE_STATCODE_INVALID_CONTROL error\r | |
677 | // is returned. If the queue is full, a PXE_STATCODE_CDB_QUEUE_FULL\r | |
678 | // error is returned.\r | |
679 | //\r | |
680 | #define PXE_CONTROL_QUEUE_IF_BUSY 0x0002\r | |
681 | \r | |
682 | //\r | |
683 | // These two bit values are used to determine if there are more UNDI\r | |
684 | // CDB structures following this one. If the link bit is set, there\r | |
685 | // must be a CDB structure following this one. Execution will start\r | |
686 | // on the next CDB structure as soon as this one completes successfully.\r | |
687 | // If an error is generated by this command, execution will stop.\r | |
688 | //\r | |
689 | #define PXE_CONTROL_LINK 0x0001\r | |
690 | #define PXE_CONTROL_LAST_CDB_IN_LIST 0x0000\r | |
691 | \r | |
692 | typedef UINT8 PXE_FRAME_TYPE;\r | |
693 | \r | |
694 | #define PXE_FRAME_TYPE_NONE 0x00\r | |
695 | #define PXE_FRAME_TYPE_UNICAST 0x01\r | |
696 | #define PXE_FRAME_TYPE_BROADCAST 0x02\r | |
697 | #define PXE_FRAME_TYPE_MULTICAST 0x03\r | |
698 | #define PXE_FRAME_TYPE_PROMISCUOUS 0x04\r | |
699 | \r | |
700 | typedef UINT32 PXE_IPV4;\r | |
701 | \r | |
702 | typedef UINT32 PXE_IPV6[4];\r | |
703 | #define PXE_MAC_LENGTH 32\r | |
704 | \r | |
705 | typedef UINT8 PXE_MAC_ADDR[PXE_MAC_LENGTH];\r | |
706 | \r | |
707 | typedef UINT8 PXE_IFTYPE;\r | |
708 | typedef UINT16 PXE_MEDIA_PROTOCOL;\r | |
709 | \r | |
710 | //\r | |
711 | // This information is from the ARP section of RFC 1700.\r | |
712 | //\r | |
713 | // 1 Ethernet (10Mb) [JBP]\r | |
714 | // 2 Experimental Ethernet (3Mb) [JBP]\r | |
715 | // 3 Amateur Radio AX.25 [PXK]\r | |
716 | // 4 Proteon ProNET Token Ring [JBP]\r | |
717 | // 5 Chaos [GXP]\r | |
718 | // 6 IEEE 802 Networks [JBP]\r | |
719 | // 7 ARCNET [JBP]\r | |
720 | // 8 Hyperchannel [JBP]\r | |
721 | // 9 Lanstar [TU]\r | |
722 | // 10 Autonet Short Address [MXB1]\r | |
723 | // 11 LocalTalk [JKR1]\r | |
724 | // 12 LocalNet (IBM* PCNet or SYTEK* LocalNET) [JXM]\r | |
725 | // 13 Ultra link [RXD2]\r | |
726 | // 14 SMDS [GXC1]\r | |
727 | // 15 Frame Relay [AGM]\r | |
728 | // 16 Asynchronous Transmission Mode (ATM) [JXB2]\r | |
729 | // 17 HDLC [JBP]\r | |
730 | // 18 Fibre Channel [Yakov Rekhter]\r | |
731 | // 19 Asynchronous Transmission Mode (ATM) [Mark Laubach]\r | |
732 | // 20 Serial Line [JBP]\r | |
733 | // 21 Asynchronous Transmission Mode (ATM) [MXB1]\r | |
734 | //\r | |
735 | // * Other names and brands may be claimed as the property of others.\r | |
736 | //\r | |
737 | #define PXE_IFTYPE_ETHERNET 0x01\r | |
738 | #define PXE_IFTYPE_TOKENRING 0x04\r | |
739 | #define PXE_IFTYPE_FIBRE_CHANNEL 0x12\r | |
740 | \r | |
741 | typedef struct s_pxe_hw_undi {\r | |
742 | UINT32 Signature; // PXE_ROMID_SIGNATURE\r | |
743 | UINT8 Len; // sizeof(PXE_HW_UNDI)\r | |
744 | UINT8 Fudge; // makes 8-bit cksum equal zero\r | |
745 | UINT8 Rev; // PXE_ROMID_REV\r | |
746 | UINT8 IFcnt; // physical connector count\r | |
747 | UINT8 MajorVer; // PXE_ROMID_MAJORVER\r | |
748 | UINT8 MinorVer; // PXE_ROMID_MINORVER\r | |
749 | UINT16 reserved; // zero, not used\r | |
750 | UINT32 Implementation; // implementation flags\r | |
751 | // reserved // vendor use\r | |
752 | // UINT32 Status; // status port\r | |
753 | // UINT32 Command; // command port\r | |
754 | // UINT64 CDBaddr; // CDB address port\r | |
755 | //\r | |
756 | } PXE_HW_UNDI;\r | |
757 | \r | |
758 | //\r | |
759 | // Status port bit definitions\r | |
760 | //\r | |
761 | //\r | |
762 | // UNDI operation state\r | |
763 | //\r | |
764 | #define PXE_HWSTAT_STATE_MASK 0xC0000000\r | |
765 | #define PXE_HWSTAT_BUSY 0xC0000000\r | |
766 | #define PXE_HWSTAT_INITIALIZED 0x80000000\r | |
767 | #define PXE_HWSTAT_STARTED 0x40000000\r | |
768 | #define PXE_HWSTAT_STOPPED 0x00000000\r | |
769 | \r | |
770 | //\r | |
771 | // If set, last command failed\r | |
772 | //\r | |
773 | #define PXE_HWSTAT_COMMAND_FAILED 0x20000000\r | |
774 | \r | |
775 | //\r | |
776 | // If set, identifies enabled receive filters\r | |
777 | //\r | |
778 | #define PXE_HWSTAT_PROMISCUOUS_MULTICAST_RX_ENABLED 0x00001000\r | |
779 | #define PXE_HWSTAT_PROMISCUOUS_RX_ENABLED 0x00000800\r | |
780 | #define PXE_HWSTAT_BROADCAST_RX_ENABLED 0x00000400\r | |
781 | #define PXE_HWSTAT_MULTICAST_RX_ENABLED 0x00000200\r | |
782 | #define PXE_HWSTAT_UNICAST_RX_ENABLED 0x00000100\r | |
783 | \r | |
784 | //\r | |
785 | // If set, identifies enabled external interrupts\r | |
786 | //\r | |
787 | #define PXE_HWSTAT_SOFTWARE_INT_ENABLED 0x00000080\r | |
788 | #define PXE_HWSTAT_TX_COMPLETE_INT_ENABLED 0x00000040\r | |
789 | #define PXE_HWSTAT_PACKET_RX_INT_ENABLED 0x00000020\r | |
790 | #define PXE_HWSTAT_CMD_COMPLETE_INT_ENABLED 0x00000010\r | |
791 | \r | |
792 | //\r | |
793 | // If set, identifies pending interrupts\r | |
794 | //\r | |
795 | #define PXE_HWSTAT_SOFTWARE_INT_PENDING 0x00000008\r | |
796 | #define PXE_HWSTAT_TX_COMPLETE_INT_PENDING 0x00000004\r | |
797 | #define PXE_HWSTAT_PACKET_RX_INT_PENDING 0x00000002\r | |
798 | #define PXE_HWSTAT_CMD_COMPLETE_INT_PENDING 0x00000001\r | |
799 | \r | |
800 | //\r | |
801 | // Command port definitions\r | |
802 | //\r | |
803 | //\r | |
804 | // If set, CDB identified in CDBaddr port is given to UNDI.\r | |
805 | // If not set, other bits in this word will be processed.\r | |
806 | //\r | |
807 | #define PXE_HWCMD_ISSUE_COMMAND 0x80000000\r | |
808 | #define PXE_HWCMD_INTS_AND_FILTS 0x00000000\r | |
809 | \r | |
810 | //\r | |
811 | // Use these to enable/disable receive filters.\r | |
812 | //\r | |
813 | #define PXE_HWCMD_PROMISCUOUS_MULTICAST_RX_ENABLE 0x00001000\r | |
814 | #define PXE_HWCMD_PROMISCUOUS_RX_ENABLE 0x00000800\r | |
815 | #define PXE_HWCMD_BROADCAST_RX_ENABLE 0x00000400\r | |
816 | #define PXE_HWCMD_MULTICAST_RX_ENABLE 0x00000200\r | |
817 | #define PXE_HWCMD_UNICAST_RX_ENABLE 0x00000100\r | |
818 | \r | |
819 | //\r | |
820 | // Use these to enable/disable external interrupts\r | |
821 | //\r | |
822 | #define PXE_HWCMD_SOFTWARE_INT_ENABLE 0x00000080\r | |
823 | #define PXE_HWCMD_TX_COMPLETE_INT_ENABLE 0x00000040\r | |
824 | #define PXE_HWCMD_PACKET_RX_INT_ENABLE 0x00000020\r | |
825 | #define PXE_HWCMD_CMD_COMPLETE_INT_ENABLE 0x00000010\r | |
826 | \r | |
827 | //\r | |
828 | // Use these to clear pending external interrupts\r | |
829 | //\r | |
830 | #define PXE_HWCMD_CLEAR_SOFTWARE_INT 0x00000008\r | |
831 | #define PXE_HWCMD_CLEAR_TX_COMPLETE_INT 0x00000004\r | |
832 | #define PXE_HWCMD_CLEAR_PACKET_RX_INT 0x00000002\r | |
833 | #define PXE_HWCMD_CLEAR_CMD_COMPLETE_INT 0x00000001\r | |
834 | \r | |
835 | typedef struct s_pxe_sw_undi {\r | |
836 | UINT32 Signature; // PXE_ROMID_SIGNATURE\r | |
837 | UINT8 Len; // sizeof(PXE_SW_UNDI)\r | |
838 | UINT8 Fudge; // makes 8-bit cksum zero\r | |
839 | UINT8 Rev; // PXE_ROMID_REV\r | |
840 | UINT8 IFcnt; // physical connector count\r | |
841 | UINT8 MajorVer; // PXE_ROMID_MAJORVER\r | |
842 | UINT8 MinorVer; // PXE_ROMID_MINORVER\r | |
843 | UINT16 reserved1; // zero, not used\r | |
844 | UINT32 Implementation; // Implementation flags\r | |
845 | UINT64 EntryPoint; // API entry point\r | |
846 | UINT8 reserved2[3]; // zero, not used\r | |
847 | UINT8 BusCnt; // number of bustypes supported\r | |
848 | UINT32 BusType[1]; // list of supported bustypes\r | |
849 | } PXE_SW_UNDI;\r | |
850 | \r | |
851 | typedef union u_pxe_undi {\r | |
852 | PXE_HW_UNDI hw;\r | |
853 | PXE_SW_UNDI sw;\r | |
854 | } PXE_UNDI;\r | |
855 | \r | |
856 | //\r | |
857 | // Signature of !PXE structure\r | |
858 | //\r | |
859 | #define PXE_ROMID_SIGNATURE PXE_BUSTYPE ('!', 'P', 'X', 'E')\r | |
860 | \r | |
861 | //\r | |
862 | // !PXE structure format revision\r | |
863 | //\r | |
864 | #define PXE_ROMID_REV 0x02\r | |
865 | \r | |
866 | //\r | |
867 | // UNDI command interface revision. These are the values that get sent\r | |
868 | // in option 94 (Client Network Interface Identifier) in the DHCP Discover\r | |
869 | // and PXE Boot Server Request packets.\r | |
870 | //\r | |
871 | #define PXE_ROMID_MAJORVER 0x03\r | |
872 | #define PXE_ROMID_MINORVER 0x00\r | |
873 | #define PXE_ROMID_MINORVER_31 0x10\r | |
874 | \r | |
875 | //\r | |
876 | // Implementation flags\r | |
877 | //\r | |
878 | #define PXE_ROMID_IMP_HW_UNDI 0x80000000\r | |
879 | #define PXE_ROMID_IMP_SW_VIRT_ADDR 0x40000000\r | |
880 | #define PXE_ROMID_IMP_64BIT_DEVICE 0x00010000\r | |
881 | #define PXE_ROMID_IMP_FRAG_SUPPORTED 0x00008000\r | |
882 | #define PXE_ROMID_IMP_CMD_LINK_SUPPORTED 0x00004000\r | |
883 | #define PXE_ROMID_IMP_CMD_QUEUE_SUPPORTED 0x00002000\r | |
884 | #define PXE_ROMID_IMP_MULTI_FRAME_SUPPORTED 0x00001000\r | |
885 | #define PXE_ROMID_IMP_NVDATA_SUPPORT_MASK 0x00000C00\r | |
886 | #define PXE_ROMID_IMP_NVDATA_BULK_WRITABLE 0x00000C00\r | |
887 | #define PXE_ROMID_IMP_NVDATA_SPARSE_WRITABLE 0x00000800\r | |
888 | #define PXE_ROMID_IMP_NVDATA_READ_ONLY 0x00000400\r | |
889 | #define PXE_ROMID_IMP_NVDATA_NOT_AVAILABLE 0x00000000\r | |
890 | #define PXE_ROMID_IMP_STATISTICS_SUPPORTED 0x00000200\r | |
891 | #define PXE_ROMID_IMP_STATION_ADDR_SETTABLE 0x00000100\r | |
892 | #define PXE_ROMID_IMP_PROMISCUOUS_MULTICAST_RX_SUPPORTED 0x00000080\r | |
893 | #define PXE_ROMID_IMP_PROMISCUOUS_RX_SUPPORTED 0x00000040\r | |
894 | #define PXE_ROMID_IMP_BROADCAST_RX_SUPPORTED 0x00000020\r | |
895 | #define PXE_ROMID_IMP_FILTERED_MULTICAST_RX_SUPPORTED 0x00000010\r | |
896 | #define PXE_ROMID_IMP_SOFTWARE_INT_SUPPORTED 0x00000008\r | |
897 | #define PXE_ROMID_IMP_TX_COMPLETE_INT_SUPPORTED 0x00000004\r | |
898 | #define PXE_ROMID_IMP_PACKET_RX_INT_SUPPORTED 0x00000002\r | |
899 | #define PXE_ROMID_IMP_CMD_COMPLETE_INT_SUPPORTED 0x00000001\r | |
900 | \r | |
901 | typedef struct s_pxe_cdb {\r | |
902 | PXE_OPCODE OpCode;\r | |
903 | PXE_OPFLAGS OpFlags;\r | |
904 | UINT16 CPBsize;\r | |
905 | UINT16 DBsize;\r | |
906 | UINT64 CPBaddr;\r | |
907 | UINT64 DBaddr;\r | |
908 | PXE_STATCODE StatCode;\r | |
909 | PXE_STATFLAGS StatFlags;\r | |
910 | UINT16 IFnum;\r | |
911 | PXE_CONTROL Control;\r | |
912 | } PXE_CDB;\r | |
913 | \r | |
914 | typedef union u_pxe_ip_addr {\r | |
915 | PXE_IPV6 IPv6;\r | |
916 | PXE_IPV4 IPv4;\r | |
917 | } PXE_IP_ADDR;\r | |
918 | \r | |
919 | typedef union pxe_device {\r | |
920 | //\r | |
921 | // PCI and PC Card NICs are both identified using bus, device\r | |
922 | // and function numbers. For PC Card, this may require PC\r | |
923 | // Card services to be loaded in the BIOS or preboot\r | |
924 | // environment.\r | |
925 | //\r | |
926 | struct {\r | |
927 | //\r | |
928 | // See S/W UNDI ROMID structure definition for PCI and\r | |
929 | // PCC BusType definitions.\r | |
930 | //\r | |
931 | UINT32 BusType;\r | |
932 | \r | |
933 | //\r | |
934 | // Bus, device & function numbers that locate this device.\r | |
935 | //\r | |
936 | UINT16 Bus;\r | |
937 | UINT8 Device;\r | |
938 | UINT8 Function;\r | |
939 | }\r | |
940 | PCI, PCC;\r | |
941 | \r | |
942 | //\r | |
943 | // %%TBD - More information is needed about enumerating\r | |
944 | // USB and 1394 devices.\r | |
945 | //\r | |
946 | struct {\r | |
947 | UINT32 BusType;\r | |
948 | UINT32 tdb;\r | |
949 | }\r | |
950 | USB, _1394;\r | |
951 | } PXE_DEVICE;\r | |
952 | \r | |
953 | //\r | |
954 | // cpb and db definitions\r | |
955 | //\r | |
956 | #define MAX_PCI_CONFIG_LEN 64 // # of dwords\r | |
957 | #define MAX_EEPROM_LEN 128 // #of dwords\r | |
958 | #define MAX_XMIT_BUFFERS 32 // recycling Q length for xmit_done\r | |
959 | #define MAX_MCAST_ADDRESS_CNT 8\r | |
960 | \r | |
961 | typedef struct s_pxe_cpb_start {\r | |
962 | //\r | |
963 | // PXE_VOID Delay(UINTN microseconds);\r | |
964 | //\r | |
965 | // UNDI will never request a delay smaller than 10 microseconds\r | |
966 | // and will always request delays in increments of 10 microseconds.\r | |
967 | // The Delay() CallBack routine must delay between n and n + 10\r | |
968 | // microseconds before returning control to the UNDI.\r | |
969 | //\r | |
970 | // This field cannot be set to zero.\r | |
971 | //\r | |
972 | UINT64 Delay;\r | |
973 | \r | |
974 | //\r | |
975 | // PXE_VOID Block(UINT32 enable);\r | |
976 | //\r | |
977 | // UNDI may need to block multi-threaded/multi-processor access to\r | |
978 | // critical code sections when programming or accessing the network\r | |
979 | // device. To this end, a blocking service is needed by the UNDI.\r | |
980 | // When UNDI needs a block, it will call Block() passing a non-zero\r | |
981 | // value. When UNDI no longer needs a block, it will call Block()\r | |
982 | // with a zero value. When called, if the Block() is already enabled,\r | |
983 | // do not return control to the UNDI until the previous Block() is\r | |
984 | // disabled.\r | |
985 | //\r | |
986 | // This field cannot be set to zero.\r | |
987 | //\r | |
988 | UINT64 Block;\r | |
989 | \r | |
990 | //\r | |
991 | // PXE_VOID Virt2Phys(UINT64 virtual, UINT64 physical_ptr);\r | |
992 | //\r | |
993 | // UNDI will pass the virtual address of a buffer and the virtual\r | |
994 | // address of a 64-bit physical buffer. Convert the virtual address\r | |
995 | // to a physical address and write the result to the physical address\r | |
996 | // buffer. If virtual and physical addresses are the same, just\r | |
997 | // copy the virtual address to the physical address buffer.\r | |
998 | //\r | |
999 | // This field can be set to zero if virtual and physical addresses\r | |
1000 | // are equal.\r | |
1001 | //\r | |
1002 | UINT64 Virt2Phys;\r | |
1003 | //\r | |
1004 | // PXE_VOID Mem_IO(UINT8 read_write, UINT8 len, UINT64 port,\r | |
1005 | // UINT64 buf_addr);\r | |
1006 | //\r | |
1007 | // UNDI will read or write the device io space using this call back\r | |
1008 | // function. It passes the number of bytes as the len parameter and it\r | |
1009 | // will be either 1,2,4 or 8.\r | |
1010 | //\r | |
1011 | // This field can not be set to zero.\r | |
1012 | //\r | |
1013 | UINT64 Mem_IO;\r | |
1014 | } PXE_CPB_START;\r | |
1015 | \r | |
1016 | typedef struct s_pxe_cpb_start_31 {\r | |
1017 | //\r | |
1018 | // PXE_VOID Delay(UINT64 UnqId, UINTN microseconds);\r | |
1019 | //\r | |
1020 | // UNDI will never request a delay smaller than 10 microseconds\r | |
1021 | // and will always request delays in increments of 10 microseconds.\r | |
1022 | // The Delay() CallBack routine must delay between n and n + 10\r | |
1023 | // microseconds before returning control to the UNDI.\r | |
1024 | //\r | |
1025 | // This field cannot be set to zero.\r | |
1026 | //\r | |
1027 | UINT64 Delay;\r | |
1028 | \r | |
1029 | //\r | |
1030 | // PXE_VOID Block(UINT64 unq_id, UINT32 enable);\r | |
1031 | //\r | |
1032 | // UNDI may need to block multi-threaded/multi-processor access to\r | |
1033 | // critical code sections when programming or accessing the network\r | |
1034 | // device. To this end, a blocking service is needed by the UNDI.\r | |
1035 | // When UNDI needs a block, it will call Block() passing a non-zero\r | |
1036 | // value. When UNDI no longer needs a block, it will call Block()\r | |
1037 | // with a zero value. When called, if the Block() is already enabled,\r | |
1038 | // do not return control to the UNDI until the previous Block() is\r | |
1039 | // disabled.\r | |
1040 | //\r | |
1041 | // This field cannot be set to zero.\r | |
1042 | //\r | |
1043 | UINT64 Block;\r | |
1044 | \r | |
1045 | //\r | |
1046 | // PXE_VOID Virt2Phys(UINT64 UnqId, UINT64 virtual, UINT64 physical_ptr);\r | |
1047 | //\r | |
1048 | // UNDI will pass the virtual address of a buffer and the virtual\r | |
1049 | // address of a 64-bit physical buffer. Convert the virtual address\r | |
1050 | // to a physical address and write the result to the physical address\r | |
1051 | // buffer. If virtual and physical addresses are the same, just\r | |
1052 | // copy the virtual address to the physical address buffer.\r | |
1053 | //\r | |
1054 | // This field can be set to zero if virtual and physical addresses\r | |
1055 | // are equal.\r | |
1056 | //\r | |
1057 | UINT64 Virt2Phys;\r | |
1058 | //\r | |
1059 | // PXE_VOID Mem_IO(UINT64 UnqId, UINT8 read_write, UINT8 len, UINT64 port,\r | |
1060 | // UINT64 buf_addr);\r | |
1061 | //\r | |
1062 | // UNDI will read or write the device io space using this call back\r | |
1063 | // function. It passes the number of bytes as the len parameter and it\r | |
1064 | // will be either 1,2,4 or 8.\r | |
1065 | //\r | |
1066 | // This field can not be set to zero.\r | |
1067 | //\r | |
1068 | UINT64 Mem_IO;\r | |
1069 | //\r | |
1070 | // PXE_VOID Map_Mem(UINT64 unq_id, UINT64 virtual_addr, UINT32 size,\r | |
1071 | // UINT32 Direction, UINT64 mapped_addr);\r | |
1072 | //\r | |
1073 | // UNDI will pass the virtual address of a buffer, direction of the data\r | |
1074 | // flow from/to the mapped buffer (the constants are defined below)\r | |
1075 | // and a place holder (pointer) for the mapped address.\r | |
1076 | // This call will Map the given address to a physical DMA address and write\r | |
1077 | // the result to the mapped_addr pointer. If there is no need to\r | |
1078 | // map the given address to a lower address (i.e. the given address is\r | |
1079 | // associated with a physical address that is already compatible to be\r | |
1080 | // used with the DMA, it converts the given virtual address to it's\r | |
1081 | // physical address and write that in the mapped address pointer.\r | |
1082 | //\r | |
1083 | // This field can be set to zero if there is no mapping service available\r | |
1084 | //\r | |
1085 | UINT64 Map_Mem;\r | |
1086 | \r | |
1087 | //\r | |
1088 | // PXE_VOID UnMap_Mem(UINT64 unq_id, UINT64 virtual_addr, UINT32 size,\r | |
1089 | // UINT32 Direction, UINT64 mapped_addr);\r | |
1090 | //\r | |
1091 | // UNDI will pass the virtual and mapped addresses of a buffer\r | |
1092 | // This call will un map the given address\r | |
1093 | //\r | |
1094 | // This field can be set to zero if there is no unmapping service available\r | |
1095 | //\r | |
1096 | UINT64 UnMap_Mem;\r | |
1097 | \r | |
1098 | //\r | |
1099 | // PXE_VOID Sync_Mem(UINT64 unq_id, UINT64 virtual,\r | |
1100 | // UINT32 size, UINT32 Direction, UINT64 mapped_addr);\r | |
1101 | //\r | |
1102 | // UNDI will pass the virtual and mapped addresses of a buffer\r | |
1103 | // This call will synchronize the contents of both the virtual and mapped\r | |
1104 | // buffers for the given Direction.\r | |
1105 | //\r | |
1106 | // This field can be set to zero if there is no service available\r | |
1107 | //\r | |
1108 | UINT64 Sync_Mem;\r | |
1109 | \r | |
1110 | //\r | |
1111 | // protocol driver can provide anything for this Unique_ID, UNDI remembers\r | |
1112 | // that as just a 64bit value assocaited to the interface specified by\r | |
1113 | // the ifnum and gives it back as a parameter to all the call-back routines\r | |
1114 | // when calling for that interface!\r | |
1115 | //\r | |
1116 | UINT64 Unique_ID;\r | |
1117 | //\r | |
1118 | } PXE_CPB_START_31;\r | |
1119 | \r | |
1120 | #define TO_AND_FROM_DEVICE 0\r | |
1121 | #define FROM_DEVICE 1\r | |
1122 | #define TO_DEVICE 2\r | |
1123 | \r | |
1124 | #define PXE_DELAY_MILLISECOND 1000\r | |
1125 | #define PXE_DELAY_SECOND 1000000\r | |
1126 | #define PXE_IO_READ 0\r | |
1127 | #define PXE_IO_WRITE 1\r | |
1128 | #define PXE_MEM_READ 2\r | |
1129 | #define PXE_MEM_WRITE 4\r | |
1130 | \r | |
1131 | typedef struct s_pxe_db_get_init_info {\r | |
1132 | //\r | |
1133 | // Minimum length of locked memory buffer that must be given to\r | |
1134 | // the Initialize command. Giving UNDI more memory will generally\r | |
1135 | // give better performance.\r | |
1136 | //\r | |
1137 | // If MemoryRequired is zero, the UNDI does not need and will not\r | |
1138 | // use system memory to receive and transmit packets.\r | |
1139 | //\r | |
1140 | UINT32 MemoryRequired;\r | |
1141 | \r | |
1142 | //\r | |
1143 | // Maximum frame data length for Tx/Rx excluding the media header.\r | |
1144 | //\r | |
1145 | UINT32 FrameDataLen;\r | |
1146 | \r | |
1147 | //\r | |
1148 | // Supported link speeds are in units of mega bits. Common ethernet\r | |
1149 | // values are 10, 100 and 1000. Unused LinkSpeeds[] entries are zero\r | |
1150 | // filled.\r | |
1151 | //\r | |
1152 | UINT32 LinkSpeeds[4];\r | |
1153 | \r | |
1154 | //\r | |
1155 | // Number of non-volatile storage items.\r | |
1156 | //\r | |
1157 | UINT32 NvCount;\r | |
1158 | \r | |
1159 | //\r | |
1160 | // Width of non-volatile storage item in bytes. 0, 1, 2 or 4\r | |
1161 | //\r | |
1162 | UINT16 NvWidth;\r | |
1163 | \r | |
1164 | //\r | |
1165 | // Media header length. This is the typical media header length for\r | |
1166 | // this UNDI. This information is needed when allocating receive\r | |
1167 | // and transmit buffers.\r | |
1168 | //\r | |
1169 | UINT16 MediaHeaderLen;\r | |
1170 | \r | |
1171 | //\r | |
1172 | // Number of bytes in the NIC hardware (MAC) address.\r | |
1173 | //\r | |
1174 | UINT16 HWaddrLen;\r | |
1175 | \r | |
1176 | //\r | |
1177 | // Maximum number of multicast MAC addresses in the multicast\r | |
1178 | // MAC address filter list.\r | |
1179 | //\r | |
1180 | UINT16 MCastFilterCnt;\r | |
1181 | \r | |
1182 | //\r | |
1183 | // Default number and size of transmit and receive buffers that will\r | |
1184 | // be allocated by the UNDI. If MemoryRequired is non-zero, this\r | |
1185 | // allocation will come out of the memory buffer given to the Initialize\r | |
1186 | // command. If MemoryRequired is zero, this allocation will come out of\r | |
1187 | // memory on the NIC.\r | |
1188 | //\r | |
1189 | UINT16 TxBufCnt;\r | |
1190 | UINT16 TxBufSize;\r | |
1191 | UINT16 RxBufCnt;\r | |
1192 | UINT16 RxBufSize;\r | |
1193 | \r | |
1194 | //\r | |
1195 | // Hardware interface types defined in the Assigned Numbers RFC\r | |
1196 | // and used in DHCP and ARP packets.\r | |
1197 | // See the PXE_IFTYPE typedef and PXE_IFTYPE_xxx macros.\r | |
1198 | //\r | |
1199 | UINT8 IFtype;\r | |
1200 | \r | |
1201 | //\r | |
1202 | // Supported duplex. See PXE_DUPLEX_xxxxx #defines below.\r | |
1203 | //\r | |
1204 | UINT8 Duplex;\r | |
1205 | \r | |
1206 | //\r | |
1207 | // Supported loopback options. See PXE_LOOPBACK_xxxxx #defines below.\r | |
1208 | //\r | |
1209 | UINT8 LoopBack;\r | |
1210 | } PXE_DB_GET_INIT_INFO;\r | |
1211 | \r | |
1212 | #define PXE_MAX_TXRX_UNIT_ETHER 1500\r | |
1213 | \r | |
1214 | #define PXE_HWADDR_LEN_ETHER 0x0006\r | |
1215 | #define PXE_MAC_HEADER_LEN_ETHER 0x000E\r | |
1216 | \r | |
1217 | #define PXE_DUPLEX_ENABLE_FULL_SUPPORTED 1\r | |
1218 | #define PXE_DUPLEX_FORCE_FULL_SUPPORTED 2\r | |
1219 | \r | |
1220 | #define PXE_LOOPBACK_INTERNAL_SUPPORTED 1\r | |
1221 | #define PXE_LOOPBACK_EXTERNAL_SUPPORTED 2\r | |
1222 | \r | |
1223 | typedef struct s_pxe_pci_config_info {\r | |
1224 | //\r | |
1225 | // This is the flag field for the PXE_DB_GET_CONFIG_INFO union.\r | |
1226 | // For PCI bus devices, this field is set to PXE_BUSTYPE_PCI.\r | |
1227 | //\r | |
1228 | UINT32 BusType;\r | |
1229 | \r | |
1230 | //\r | |
1231 | // This identifies the PCI network device that this UNDI interface\r | |
1232 | // is bound to.\r | |
1233 | //\r | |
1234 | UINT16 Bus;\r | |
1235 | UINT8 Device;\r | |
1236 | UINT8 Function;\r | |
1237 | \r | |
1238 | //\r | |
1239 | // This is a copy of the PCI configuration space for this\r | |
1240 | // network device.\r | |
1241 | //\r | |
1242 | union {\r | |
1243 | UINT8 Byte[256];\r | |
1244 | UINT16 Word[128];\r | |
1245 | UINT32 Dword[64];\r | |
1246 | } Config;\r | |
1247 | } PXE_PCI_CONFIG_INFO;\r | |
1248 | \r | |
1249 | typedef struct s_pxe_pcc_config_info {\r | |
1250 | //\r | |
1251 | // This is the flag field for the PXE_DB_GET_CONFIG_INFO union.\r | |
1252 | // For PCC bus devices, this field is set to PXE_BUSTYPE_PCC.\r | |
1253 | //\r | |
1254 | UINT32 BusType;\r | |
1255 | \r | |
1256 | //\r | |
1257 | // This identifies the PCC network device that this UNDI interface\r | |
1258 | // is bound to.\r | |
1259 | //\r | |
1260 | UINT16 Bus;\r | |
1261 | UINT8 Device;\r | |
1262 | UINT8 Function;\r | |
1263 | \r | |
1264 | //\r | |
1265 | // This is a copy of the PCC configuration space for this\r | |
1266 | // network device.\r | |
1267 | //\r | |
1268 | union {\r | |
1269 | UINT8 Byte[256];\r | |
1270 | UINT16 Word[128];\r | |
1271 | UINT32 Dword[64];\r | |
1272 | } Config;\r | |
1273 | } PXE_PCC_CONFIG_INFO;\r | |
1274 | \r | |
1275 | typedef struct s_pxe_usb_config_info {\r | |
1276 | UINT32 BusType;\r | |
1277 | //\r | |
1278 | // %%TBD What should we return here...\r | |
1279 | //\r | |
1280 | } PXE_USB_CONFIG_INFO;\r | |
1281 | \r | |
1282 | typedef struct s_pxe_1394_config_info {\r | |
1283 | UINT32 BusType;\r | |
1284 | //\r | |
1285 | // %%TBD What should we return here...\r | |
1286 | //\r | |
1287 | } PXE_1394_CONFIG_INFO;\r | |
1288 | \r | |
1289 | typedef union u_pxe_db_get_config_info {\r | |
1290 | PXE_PCI_CONFIG_INFO pci;\r | |
1291 | PXE_PCC_CONFIG_INFO pcc;\r | |
1292 | PXE_USB_CONFIG_INFO usb;\r | |
1293 | PXE_1394_CONFIG_INFO _1394;\r | |
1294 | } PXE_DB_GET_CONFIG_INFO;\r | |
1295 | \r | |
1296 | typedef struct s_pxe_cpb_initialize {\r | |
1297 | //\r | |
1298 | // Address of first (lowest) byte of the memory buffer. This buffer must\r | |
1299 | // be in contiguous physical memory and cannot be swapped out. The UNDI\r | |
1300 | // will be using this for transmit and receive buffering.\r | |
1301 | //\r | |
1302 | UINT64 MemoryAddr;\r | |
1303 | \r | |
1304 | //\r | |
1305 | // MemoryLength must be greater than or equal to MemoryRequired\r | |
1306 | // returned by the Get Init Info command.\r | |
1307 | //\r | |
1308 | UINT32 MemoryLength;\r | |
1309 | \r | |
1310 | //\r | |
1311 | // Desired link speed in Mbit/sec. Common ethernet values are 10, 100\r | |
1312 | // and 1000. Setting a value of zero will auto-detect and/or use the\r | |
1313 | // default link speed (operation depends on UNDI/NIC functionality).\r | |
1314 | //\r | |
1315 | UINT32 LinkSpeed;\r | |
1316 | \r | |
1317 | //\r | |
1318 | // Suggested number and size of receive and transmit buffers to\r | |
1319 | // allocate. If MemoryAddr and MemoryLength are non-zero, this\r | |
1320 | // allocation comes out of the supplied memory buffer. If MemoryAddr\r | |
1321 | // and MemoryLength are zero, this allocation comes out of memory\r | |
1322 | // on the NIC.\r | |
1323 | //\r | |
1324 | // If these fields are set to zero, the UNDI will allocate buffer\r | |
1325 | // counts and sizes as it sees fit.\r | |
1326 | //\r | |
1327 | UINT16 TxBufCnt;\r | |
1328 | UINT16 TxBufSize;\r | |
1329 | UINT16 RxBufCnt;\r | |
1330 | UINT16 RxBufSize;\r | |
1331 | \r | |
1332 | //\r | |
1333 | // The following configuration parameters are optional and must be zero\r | |
1334 | // to use the default values.\r | |
1335 | //\r | |
1336 | UINT8 Duplex;\r | |
1337 | \r | |
1338 | UINT8 LoopBack;\r | |
1339 | } PXE_CPB_INITIALIZE;\r | |
1340 | \r | |
1341 | #define PXE_DUPLEX_DEFAULT 0x00\r | |
1342 | #define PXE_FORCE_FULL_DUPLEX 0x01\r | |
1343 | #define PXE_ENABLE_FULL_DUPLEX 0x02\r | |
1344 | #define PXE_FORCE_HALF_DUPLEX 0x04\r | |
1345 | #define PXE_DISABLE_FULL_DUPLEX 0x08\r | |
1346 | \r | |
1347 | #define LOOPBACK_NORMAL 0\r | |
1348 | #define LOOPBACK_INTERNAL 1\r | |
1349 | #define LOOPBACK_EXTERNAL 2\r | |
1350 | \r | |
1351 | typedef struct s_pxe_db_initialize {\r | |
1352 | //\r | |
1353 | // Actual amount of memory used from the supplied memory buffer. This\r | |
1354 | // may be less that the amount of memory suppllied and may be zero if\r | |
1355 | // the UNDI and network device do not use external memory buffers.\r | |
1356 | //\r | |
1357 | // Memory used by the UNDI and network device is allocated from the\r | |
1358 | // lowest memory buffer address.\r | |
1359 | //\r | |
1360 | UINT32 MemoryUsed;\r | |
1361 | \r | |
1362 | //\r | |
1363 | // Actual number and size of receive and transmit buffers that were\r | |
1364 | // allocated.\r | |
1365 | //\r | |
1366 | UINT16 TxBufCnt;\r | |
1367 | UINT16 TxBufSize;\r | |
1368 | UINT16 RxBufCnt;\r | |
1369 | UINT16 RxBufSize;\r | |
1370 | } PXE_DB_INITIALIZE;\r | |
1371 | \r | |
1372 | typedef struct s_pxe_cpb_receive_filters {\r | |
1373 | //\r | |
1374 | // List of multicast MAC addresses. This list, if present, will\r | |
1375 | // replace the existing multicast MAC address filter list.\r | |
1376 | //\r | |
1377 | PXE_MAC_ADDR MCastList[MAX_MCAST_ADDRESS_CNT];\r | |
1378 | } PXE_CPB_RECEIVE_FILTERS;\r | |
1379 | \r | |
1380 | typedef struct s_pxe_db_receive_filters {\r | |
1381 | //\r | |
1382 | // Filtered multicast MAC address list.\r | |
1383 | //\r | |
1384 | PXE_MAC_ADDR MCastList[MAX_MCAST_ADDRESS_CNT];\r | |
1385 | } PXE_DB_RECEIVE_FILTERS;\r | |
1386 | \r | |
1387 | typedef struct s_pxe_cpb_station_address {\r | |
1388 | //\r | |
1389 | // If supplied and supported, the current station MAC address\r | |
1390 | // will be changed.\r | |
1391 | //\r | |
1392 | PXE_MAC_ADDR StationAddr;\r | |
1393 | } PXE_CPB_STATION_ADDRESS;\r | |
1394 | \r | |
1395 | typedef struct s_pxe_dpb_station_address {\r | |
1396 | //\r | |
1397 | // Current station MAC address.\r | |
1398 | //\r | |
1399 | PXE_MAC_ADDR StationAddr;\r | |
1400 | \r | |
1401 | //\r | |
1402 | // Station broadcast MAC address.\r | |
1403 | //\r | |
1404 | PXE_MAC_ADDR BroadcastAddr;\r | |
1405 | \r | |
1406 | //\r | |
1407 | // Permanent station MAC address.\r | |
1408 | //\r | |
1409 | PXE_MAC_ADDR PermanentAddr;\r | |
1410 | } PXE_DB_STATION_ADDRESS;\r | |
1411 | \r | |
1412 | typedef struct s_pxe_db_statistics {\r | |
1413 | //\r | |
1414 | // Bit field identifying what statistic data is collected by the\r | |
1415 | // UNDI/NIC.\r | |
1416 | // If bit 0x00 is set, Data[0x00] is collected.\r | |
1417 | // If bit 0x01 is set, Data[0x01] is collected.\r | |
1418 | // If bit 0x20 is set, Data[0x20] is collected.\r | |
1419 | // If bit 0x21 is set, Data[0x21] is collected.\r | |
1420 | // Etc.\r | |
1421 | //\r | |
1422 | UINT64 Supported;\r | |
1423 | \r | |
1424 | //\r | |
1425 | // Statistic data.\r | |
1426 | //\r | |
1427 | UINT64 Data[64];\r | |
1428 | } PXE_DB_STATISTICS;\r | |
1429 | \r | |
1430 | //\r | |
1431 | // Total number of frames received. Includes frames with errors and\r | |
1432 | // dropped frames.\r | |
1433 | //\r | |
1434 | #define PXE_STATISTICS_RX_TOTAL_FRAMES 0x00\r | |
1435 | \r | |
1436 | //\r | |
1437 | // Number of valid frames received and copied into receive buffers.\r | |
1438 | //\r | |
1439 | #define PXE_STATISTICS_RX_GOOD_FRAMES 0x01\r | |
1440 | \r | |
1441 | //\r | |
1442 | // Number of frames below the minimum length for the media.\r | |
1443 | // This would be <64 for ethernet.\r | |
1444 | //\r | |
1445 | #define PXE_STATISTICS_RX_UNDERSIZE_FRAMES 0x02\r | |
1446 | \r | |
1447 | //\r | |
1448 | // Number of frames longer than the maxminum length for the\r | |
1449 | // media. This would be >1500 for ethernet.\r | |
1450 | //\r | |
1451 | #define PXE_STATISTICS_RX_OVERSIZE_FRAMES 0x03\r | |
1452 | \r | |
1453 | //\r | |
1454 | // Valid frames that were dropped because receive buffers were full.\r | |
1455 | //\r | |
1456 | #define PXE_STATISTICS_RX_DROPPED_FRAMES 0x04\r | |
1457 | \r | |
1458 | //\r | |
1459 | // Number of valid unicast frames received and not dropped.\r | |
1460 | //\r | |
1461 | #define PXE_STATISTICS_RX_UNICAST_FRAMES 0x05\r | |
1462 | \r | |
1463 | //\r | |
1464 | // Number of valid broadcast frames received and not dropped.\r | |
1465 | //\r | |
1466 | #define PXE_STATISTICS_RX_BROADCAST_FRAMES 0x06\r | |
1467 | \r | |
1468 | //\r | |
1469 | // Number of valid mutlicast frames received and not dropped.\r | |
1470 | //\r | |
1471 | #define PXE_STATISTICS_RX_MULTICAST_FRAMES 0x07\r | |
1472 | \r | |
1473 | //\r | |
1474 | // Number of frames w/ CRC or alignment errors.\r | |
1475 | //\r | |
1476 | #define PXE_STATISTICS_RX_CRC_ERROR_FRAMES 0x08\r | |
1477 | \r | |
1478 | //\r | |
1479 | // Total number of bytes received. Includes frames with errors\r | |
1480 | // and dropped frames.\r | |
1481 | //\r | |
1482 | #define PXE_STATISTICS_RX_TOTAL_BYTES 0x09\r | |
1483 | \r | |
1484 | //\r | |
1485 | // Transmit statistics.\r | |
1486 | //\r | |
1487 | #define PXE_STATISTICS_TX_TOTAL_FRAMES 0x0A\r | |
1488 | #define PXE_STATISTICS_TX_GOOD_FRAMES 0x0B\r | |
1489 | #define PXE_STATISTICS_TX_UNDERSIZE_FRAMES 0x0C\r | |
1490 | #define PXE_STATISTICS_TX_OVERSIZE_FRAMES 0x0D\r | |
1491 | #define PXE_STATISTICS_TX_DROPPED_FRAMES 0x0E\r | |
1492 | #define PXE_STATISTICS_TX_UNICAST_FRAMES 0x0F\r | |
1493 | #define PXE_STATISTICS_TX_BROADCAST_FRAMES 0x10\r | |
1494 | #define PXE_STATISTICS_TX_MULTICAST_FRAMES 0x11\r | |
1495 | #define PXE_STATISTICS_TX_CRC_ERROR_FRAMES 0x12\r | |
1496 | #define PXE_STATISTICS_TX_TOTAL_BYTES 0x13\r | |
1497 | \r | |
1498 | //\r | |
1499 | // Number of collisions detection on this subnet.\r | |
1500 | //\r | |
1501 | #define PXE_STATISTICS_COLLISIONS 0x14\r | |
1502 | \r | |
1503 | //\r | |
1504 | // Number of frames destined for unsupported protocol.\r | |
1505 | //\r | |
1506 | #define PXE_STATISTICS_UNSUPPORTED_PROTOCOL 0x15\r | |
1507 | \r | |
1508 | typedef struct s_pxe_cpb_mcast_ip_to_mac {\r | |
1509 | //\r | |
1510 | // Multicast IP address to be converted to multicast MAC address.\r | |
1511 | //\r | |
1512 | PXE_IP_ADDR IP;\r | |
1513 | } PXE_CPB_MCAST_IP_TO_MAC;\r | |
1514 | \r | |
1515 | typedef struct s_pxe_db_mcast_ip_to_mac {\r | |
1516 | //\r | |
1517 | // Multicast MAC address.\r | |
1518 | //\r | |
1519 | PXE_MAC_ADDR MAC;\r | |
1520 | } PXE_DB_MCAST_IP_TO_MAC;\r | |
1521 | \r | |
1522 | typedef struct s_pxe_cpb_nvdata_sparse {\r | |
1523 | //\r | |
1524 | // NvData item list. Only items in this list will be updated.\r | |
1525 | //\r | |
1526 | struct {\r | |
1527 | //\r | |
1528 | // Non-volatile storage address to be changed.\r | |
1529 | //\r | |
1530 | UINT32 Addr;\r | |
1531 | \r | |
1532 | //\r | |
1533 | // Data item to write into above storage address.\r | |
1534 | //\r | |
1535 | union {\r | |
1536 | UINT8 Byte;\r | |
1537 | UINT16 Word;\r | |
1538 | UINT32 Dword;\r | |
1539 | } Data;\r | |
1540 | } Item[MAX_EEPROM_LEN];\r | |
1541 | }\r | |
1542 | PXE_CPB_NVDATA_SPARSE;\r | |
1543 | \r | |
1544 | //\r | |
1545 | // When using bulk update, the size of the CPB structure must be\r | |
1546 | // the same size as the non-volatile NIC storage.\r | |
1547 | //\r | |
1548 | typedef union u_pxe_cpb_nvdata_bulk {\r | |
1549 | //\r | |
1550 | // Array of byte-wide data items.\r | |
1551 | //\r | |
1552 | UINT8 Byte[MAX_EEPROM_LEN << 2];\r | |
1553 | \r | |
1554 | //\r | |
1555 | // Array of word-wide data items.\r | |
1556 | //\r | |
1557 | UINT16 Word[MAX_EEPROM_LEN << 1];\r | |
1558 | \r | |
1559 | //\r | |
1560 | // Array of dword-wide data items.\r | |
1561 | //\r | |
1562 | UINT32 Dword[MAX_EEPROM_LEN];\r | |
1563 | } PXE_CPB_NVDATA_BULK;\r | |
1564 | \r | |
1565 | typedef struct s_pxe_db_nvdata {\r | |
1566 | //\r | |
1567 | // Arrays of data items from non-volatile storage.\r | |
1568 | //\r | |
1569 | union {\r | |
1570 | //\r | |
1571 | // Array of byte-wide data items.\r | |
1572 | //\r | |
1573 | UINT8 Byte[MAX_EEPROM_LEN << 2];\r | |
1574 | \r | |
1575 | //\r | |
1576 | // Array of word-wide data items.\r | |
1577 | //\r | |
1578 | UINT16 Word[MAX_EEPROM_LEN << 1];\r | |
1579 | \r | |
1580 | //\r | |
1581 | // Array of dword-wide data items.\r | |
1582 | //\r | |
1583 | UINT32 Dword[MAX_EEPROM_LEN];\r | |
1584 | } Data;\r | |
1585 | } PXE_DB_NVDATA;\r | |
1586 | \r | |
1587 | typedef struct s_pxe_db_get_status {\r | |
1588 | //\r | |
1589 | // Length of next receive frame (header + data). If this is zero,\r | |
1590 | // there is no next receive frame available.\r | |
1591 | //\r | |
1592 | UINT32 RxFrameLen;\r | |
1593 | \r | |
1594 | //\r | |
1595 | // Reserved, set to zero.\r | |
1596 | //\r | |
1597 | UINT32 reserved;\r | |
1598 | \r | |
1599 | //\r | |
1600 | // Addresses of transmitted buffers that need to be recycled.\r | |
1601 | //\r | |
1602 | UINT64 TxBuffer[MAX_XMIT_BUFFERS];\r | |
1603 | } PXE_DB_GET_STATUS;\r | |
1604 | \r | |
1605 | typedef struct s_pxe_cpb_fill_header {\r | |
1606 | //\r | |
1607 | // Source and destination MAC addresses. These will be copied into\r | |
1608 | // the media header without doing byte swapping.\r | |
1609 | //\r | |
1610 | PXE_MAC_ADDR SrcAddr;\r | |
1611 | PXE_MAC_ADDR DestAddr;\r | |
1612 | \r | |
1613 | //\r | |
1614 | // Address of first byte of media header. The first byte of packet data\r | |
1615 | // follows the last byte of the media header.\r | |
1616 | //\r | |
1617 | UINT64 MediaHeader;\r | |
1618 | \r | |
1619 | //\r | |
1620 | // Length of packet data in bytes (not including the media header).\r | |
1621 | //\r | |
1622 | UINT32 PacketLen;\r | |
1623 | \r | |
1624 | //\r | |
1625 | // Protocol type. This will be copied into the media header without\r | |
1626 | // doing byte swapping. Protocol type numbers can be obtained from\r | |
1627 | // the Assigned Numbers RFC 1700.\r | |
1628 | //\r | |
1629 | UINT16 Protocol;\r | |
1630 | \r | |
1631 | //\r | |
1632 | // Length of the media header in bytes.\r | |
1633 | //\r | |
1634 | UINT16 MediaHeaderLen;\r | |
1635 | } PXE_CPB_FILL_HEADER;\r | |
1636 | \r | |
1637 | #define PXE_PROTOCOL_ETHERNET_IP 0x0800\r | |
1638 | #define PXE_PROTOCOL_ETHERNET_ARP 0x0806\r | |
1639 | #define MAX_XMIT_FRAGMENTS 16\r | |
1640 | \r | |
1641 | typedef struct s_pxe_cpb_fill_header_fragmented {\r | |
1642 | //\r | |
1643 | // Source and destination MAC addresses. These will be copied into\r | |
1644 | // the media header without doing byte swapping.\r | |
1645 | //\r | |
1646 | PXE_MAC_ADDR SrcAddr;\r | |
1647 | PXE_MAC_ADDR DestAddr;\r | |
1648 | \r | |
1649 | //\r | |
1650 | // Length of packet data in bytes (not including the media header).\r | |
1651 | //\r | |
1652 | UINT32 PacketLen;\r | |
1653 | \r | |
1654 | //\r | |
1655 | // Protocol type. This will be copied into the media header without\r | |
1656 | // doing byte swapping. Protocol type numbers can be obtained from\r | |
1657 | // the Assigned Numbers RFC 1700.\r | |
1658 | //\r | |
1659 | PXE_MEDIA_PROTOCOL Protocol;\r | |
1660 | \r | |
1661 | //\r | |
1662 | // Length of the media header in bytes.\r | |
1663 | //\r | |
1664 | UINT16 MediaHeaderLen;\r | |
1665 | \r | |
1666 | //\r | |
1667 | // Number of packet fragment descriptors.\r | |
1668 | //\r | |
1669 | UINT16 FragCnt;\r | |
1670 | \r | |
1671 | //\r | |
1672 | // Reserved, must be set to zero.\r | |
1673 | //\r | |
1674 | UINT16 reserved;\r | |
1675 | \r | |
1676 | //\r | |
1677 | // Array of packet fragment descriptors. The first byte of the media\r | |
1678 | // header is the first byte of the first fragment.\r | |
1679 | //\r | |
1680 | struct {\r | |
1681 | //\r | |
1682 | // Address of this packet fragment.\r | |
1683 | //\r | |
1684 | UINT64 FragAddr;\r | |
1685 | \r | |
1686 | //\r | |
1687 | // Length of this packet fragment.\r | |
1688 | //\r | |
1689 | UINT32 FragLen;\r | |
1690 | \r | |
1691 | //\r | |
1692 | // Reserved, must be set to zero.\r | |
1693 | //\r | |
1694 | UINT32 reserved;\r | |
1695 | } FragDesc[MAX_XMIT_FRAGMENTS];\r | |
1696 | }\r | |
1697 | PXE_CPB_FILL_HEADER_FRAGMENTED;\r | |
1698 | \r | |
1699 | typedef struct s_pxe_cpb_transmit {\r | |
1700 | //\r | |
1701 | // Address of first byte of frame buffer. This is also the first byte\r | |
1702 | // of the media header.\r | |
1703 | //\r | |
1704 | UINT64 FrameAddr;\r | |
1705 | \r | |
1706 | //\r | |
1707 | // Length of the data portion of the frame buffer in bytes. Do not\r | |
1708 | // include the length of the media header.\r | |
1709 | //\r | |
1710 | UINT32 DataLen;\r | |
1711 | \r | |
1712 | //\r | |
1713 | // Length of the media header in bytes.\r | |
1714 | //\r | |
1715 | UINT16 MediaheaderLen;\r | |
1716 | \r | |
1717 | //\r | |
1718 | // Reserved, must be zero.\r | |
1719 | //\r | |
1720 | UINT16 reserved;\r | |
1721 | } PXE_CPB_TRANSMIT;\r | |
1722 | \r | |
1723 | typedef struct s_pxe_cpb_transmit_fragments {\r | |
1724 | //\r | |
1725 | // Length of packet data in bytes (not including the media header).\r | |
1726 | //\r | |
1727 | UINT32 FrameLen;\r | |
1728 | \r | |
1729 | //\r | |
1730 | // Length of the media header in bytes.\r | |
1731 | //\r | |
1732 | UINT16 MediaheaderLen;\r | |
1733 | \r | |
1734 | //\r | |
1735 | // Number of packet fragment descriptors.\r | |
1736 | //\r | |
1737 | UINT16 FragCnt;\r | |
1738 | \r | |
1739 | //\r | |
1740 | // Array of frame fragment descriptors. The first byte of the first\r | |
1741 | // fragment is also the first byte of the media header.\r | |
1742 | //\r | |
1743 | struct {\r | |
1744 | //\r | |
1745 | // Address of this frame fragment.\r | |
1746 | //\r | |
1747 | UINT64 FragAddr;\r | |
1748 | \r | |
1749 | //\r | |
1750 | // Length of this frame fragment.\r | |
1751 | //\r | |
1752 | UINT32 FragLen;\r | |
1753 | \r | |
1754 | //\r | |
1755 | // Reserved, must be set to zero.\r | |
1756 | //\r | |
1757 | UINT32 reserved;\r | |
1758 | } FragDesc[MAX_XMIT_FRAGMENTS];\r | |
1759 | }\r | |
1760 | PXE_CPB_TRANSMIT_FRAGMENTS;\r | |
1761 | \r | |
1762 | typedef struct s_pxe_cpb_receive {\r | |
1763 | //\r | |
1764 | // Address of first byte of receive buffer. This is also the first byte\r | |
1765 | // of the frame header.\r | |
1766 | //\r | |
1767 | UINT64 BufferAddr;\r | |
1768 | \r | |
1769 | //\r | |
1770 | // Length of receive buffer. This must be large enough to hold the\r | |
1771 | // received frame (media header + data). If the length of smaller than\r | |
1772 | // the received frame, data will be lost.\r | |
1773 | //\r | |
1774 | UINT32 BufferLen;\r | |
1775 | \r | |
1776 | //\r | |
1777 | // Reserved, must be set to zero.\r | |
1778 | //\r | |
1779 | UINT32 reserved;\r | |
1780 | } PXE_CPB_RECEIVE;\r | |
1781 | \r | |
1782 | typedef struct s_pxe_db_receive {\r | |
1783 | //\r | |
1784 | // Source and destination MAC addresses from media header.\r | |
1785 | //\r | |
1786 | PXE_MAC_ADDR SrcAddr;\r | |
1787 | PXE_MAC_ADDR DestAddr;\r | |
1788 | \r | |
1789 | //\r | |
1790 | // Length of received frame. May be larger than receive buffer size.\r | |
1791 | // The receive buffer will not be overwritten. This is how to tell\r | |
1792 | // if data was lost because the receive buffer was too small.\r | |
1793 | //\r | |
1794 | UINT32 FrameLen;\r | |
1795 | \r | |
1796 | //\r | |
1797 | // Protocol type from media header.\r | |
1798 | //\r | |
1799 | PXE_MEDIA_PROTOCOL Protocol;\r | |
1800 | \r | |
1801 | //\r | |
1802 | // Length of media header in received frame.\r | |
1803 | //\r | |
1804 | UINT16 MediaHeaderLen;\r | |
1805 | \r | |
1806 | //\r | |
1807 | // Type of receive frame.\r | |
1808 | //\r | |
1809 | PXE_FRAME_TYPE Type;\r | |
1810 | \r | |
1811 | //\r | |
1812 | // Reserved, must be zero.\r | |
1813 | //\r | |
1814 | UINT8 reserved[7];\r | |
1815 | \r | |
1816 | } PXE_DB_RECEIVE;\r | |
1817 | \r | |
1818 | #pragma pack()\r | |
1819 | \r | |
1820 | #endif\r |