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3eb9473e | 1 | /*++\r |
2 | \r | |
3 | Copyright (c) 2007, Intel Corporation \r | |
4 | All rights reserved. This program and the accompanying materials \r | |
5 | are licensed and made available under the terms and conditions of the BSD License \r | |
6 | which accompanies this distribution. The full text of the license may be found at \r | |
7 | http://opensource.org/licenses/bsd-license.php \r | |
8 | \r | |
9 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r | |
10 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r | |
11 | \r | |
12 | Module Name: \r | |
13 | \r | |
14 | SdramSpd.h\r | |
15 | \r | |
16 | Abstract:\r | |
17 | \r | |
18 | This file contains definitions for the SPD fields on an SDRAM.\r | |
19 | \r | |
20 | --*/\r | |
21 | \r | |
22 | #ifndef _SDRAM_SPD_H\r | |
23 | #define _SDRAM_SPD_H\r | |
24 | \r | |
25 | //\r | |
26 | // SDRAM SPD field definitions\r | |
27 | //\r | |
28 | #define SPD_MEMORY_TYPE 2\r | |
29 | #define SPD_SDRAM_ROW_ADDR 3\r | |
30 | #define SPD_SDRAM_COL_ADDR 4\r | |
31 | #define SPD_SDRAM_MODULE_ROWS 5\r | |
32 | #define SPD_SDRAM_MODULE_DATA_WIDTH_LSB 6\r | |
33 | #define SPD_SDRAM_MODULE_DATA_WIDTH_MSB 7\r | |
34 | #define SPD_SDRAM_ECC_SUPPORT 11\r | |
35 | #define SPD_SDRAM_REFRESH 12\r | |
36 | #define SPD_SDRAM_WIDTH 13\r | |
37 | #define SPD_SDRAM_ERROR_WIDTH 14\r | |
38 | #define SPD_SDRAM_BURST_LENGTH 16\r | |
39 | #define SPD_SDRAM_NO_OF_BANKS 17\r | |
40 | #define SPD_SDRAM_CAS_LATENCY 18\r | |
41 | #define SPD_SDRAM_MODULE_ATTR 21\r | |
42 | \r | |
43 | #define SPD_SDRAM_TCLK1_PULSE 9 // cycle time for highest cas latency\r | |
44 | #define SPD_SDRAM_TAC1_PULSE 10 // access time for highest cas latency\r | |
45 | #define SPD_SDRAM_TCLK2_PULSE 23 // cycle time for 2nd highest cas latency\r | |
46 | #define SPD_SDRAM_TAC2_PULSE 24 // access time for 2nd highest cas latency\r | |
47 | #define SPD_SDRAM_TCLK3_PULSE 25 // cycle time for 3rd highest cas latency\r | |
48 | #define SPD_SDRAM_TAC3_PULSE 26 // access time for 3rd highest cas latency\r | |
49 | #define SPD_SDRAM_MIN_PRECHARGE 27\r | |
50 | #define SPD_SDRAM_ACTIVE_MIN 28\r | |
51 | #define SPD_SDRAM_RAS_CAS 29\r | |
52 | #define SPD_SDRAM_RAS_PULSE 30\r | |
53 | #define SPD_SDRAM_DENSITY 31\r | |
54 | \r | |
55 | //\r | |
56 | // Memory Type Definitions\r | |
57 | //\r | |
58 | #define SPD_VAL_SDR_TYPE 4 // SDR SDRAM memory\r | |
59 | #define SPD_VAL_DDR_TYPE 7 // DDR SDRAM memory\r | |
60 | #define SPD_VAL_DDR2_TYPE 8 // DDR2 SDRAM memory\r | |
61 | //\r | |
62 | // ECC Type Definitions\r | |
63 | //\r | |
64 | #define SPD_ECC_TYPE_NONE 0x00 // No error checking\r | |
65 | #define SPD_ECC_TYPE_PARITY 0x01 // No error checking\r | |
66 | #define SPD_ECC_TYPE_ECC 0x02 // Error checking only\r | |
67 | //\r | |
68 | // Module Attributes (Bit positions)\r | |
69 | //\r | |
70 | #define SPD_BUFFERED 0x01\r | |
71 | #define SPD_REGISTERED 0x02\r | |
72 | \r | |
73 | #endif\r |