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3eb9473e | 1 | /*++\r |
2 | \r | |
3 | Copyright (c) 2004 - 2006, Intel Corporation \r | |
4 | All rights reserved. This program and the accompanying materials \r | |
5 | are licensed and made available under the terms and conditions of the BSD License \r | |
6 | which accompanies this distribution. The full text of the license may be found at \r | |
7 | http://opensource.org/licenses/bsd-license.php \r | |
8 | \r | |
9 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r | |
10 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r | |
11 | \r | |
12 | \r | |
13 | Module Name:\r | |
14 | \r | |
15 | CpuBreakpoint.c\r | |
16 | \r | |
17 | Abstract: \r | |
18 | \r | |
19 | \r | |
20 | --*/\r | |
21 | \r | |
c7f33ca4 | 22 | #include "BaseLibInternals.h"\r |
3eb9473e | 23 | \r |
24 | extern\r | |
25 | UINT64\r | |
26 | _break (\r | |
27 | CHAR8 BreakCode\r | |
28 | );\r | |
29 | \r | |
30 | /**\r | |
31 | Generates a breakpoint on the CPU.\r | |
32 | \r | |
33 | Generates a breakpoint on the CPU. The breakpoint must be implemented such\r | |
34 | that code can resume normal execution after the breakpoint.\r | |
35 | \r | |
36 | **/\r | |
37 | VOID\r | |
38 | EFIAPI\r | |
39 | CpuBreakpoint (\r | |
40 | VOID\r | |
41 | )\r | |
42 | {\r | |
43 | _break (3);\r | |
44 | }\r | |
45 | \r | |
46 | /**\r | |
47 | Used to serialize load and store operations.\r | |
48 | \r | |
49 | All loads and stores that proceed calls to this function are guaranteed to be\r | |
50 | globally visible when this function returns.\r | |
51 | \r | |
52 | **/\r | |
53 | VOID\r | |
54 | EFIAPI\r | |
55 | MemoryFence (\r | |
56 | VOID\r | |
57 | )\r | |
58 | {\r | |
59 | }\r | |
60 | \r | |
61 | /**\r | |
62 | Disables CPU interrupts.\r | |
63 | \r | |
64 | Disables CPU interrupts.\r | |
65 | \r | |
66 | **/\r | |
67 | VOID\r | |
68 | EFIAPI\r | |
69 | DisableInterrupts (\r | |
70 | VOID\r | |
71 | )\r | |
72 | {\r | |
73 | ASSERT (FALSE);\r | |
74 | }\r | |
75 | \r | |
76 | /**\r | |
77 | Enables CPU interrupts.\r | |
78 | \r | |
79 | Enables CPU interrupts.\r | |
80 | \r | |
81 | **/\r | |
82 | VOID\r | |
83 | EFIAPI\r | |
84 | EnableInterrupts (\r | |
85 | VOID\r | |
86 | )\r | |
87 | {\r | |
88 | ASSERT (FALSE);\r | |
89 | }\r | |
90 | \r | |
91 | /**\r | |
92 | Retrieves the current CPU interrupt state.\r | |
93 | \r | |
94 | Retrieves the current CPU interrupt state. Returns TRUE is interrupts are\r | |
95 | currently enabled. Otherwise returns FALSE.\r | |
96 | \r | |
97 | @retval TRUE CPU interrupts are enabled.\r | |
98 | @retval FALSE CPU interrupts are disabled.\r | |
99 | \r | |
100 | **/\r | |
101 | BOOLEAN\r | |
102 | EFIAPI\r | |
103 | GlueGetInterruptState (\r | |
104 | VOID\r | |
105 | )\r | |
106 | {\r | |
107 | ASSERT (FALSE);\r | |
108 | return FALSE;\r | |
109 | }\r | |
110 | \r | |
111 | /**\r | |
112 | Enables CPU interrupts for the smallest window required to capture any\r | |
113 | pending interrupts.\r | |
114 | \r | |
115 | Enables CPU interrupts for the smallest window required to capture any\r | |
116 | pending interrupts.\r | |
117 | \r | |
118 | **/\r | |
119 | VOID\r | |
120 | EFIAPI\r | |
121 | EnableDisableInterrupts (\r | |
122 | VOID\r | |
123 | )\r | |
124 | {\r | |
125 | EnableInterrupts ();\r | |
126 | DisableInterrupts ();\r | |
127 | }\r | |
128 | \r | |
129 | /**\r | |
130 | Requests CPU to pause for a short period of time.\r | |
131 | \r | |
132 | Requests CPU to pause for a short period of time. Typically used in MP\r | |
133 | systems to prevent memory starvation while waiting for a spin lock.\r | |
134 | \r | |
135 | **/\r | |
136 | VOID\r | |
137 | EFIAPI\r | |
138 | CpuPause (\r | |
139 | VOID\r | |
140 | )\r | |
141 | {\r | |
142 | }\r | |
143 | \r | |
144 | /**\r | |
145 | Flushes all the Translation Lookaside Buffers(TLB) entries in a CPU.\r | |
146 | \r | |
147 | Flushes all the Translation Lookaside Buffers(TLB) entries in a CPU.\r | |
148 | \r | |
149 | **/\r | |
150 | VOID\r | |
151 | EFIAPI\r | |
152 | CpuFlushTlb (\r | |
153 | VOID\r | |
154 | )\r | |
155 | {\r | |
156 | ASSERT (FALSE);\r | |
157 | }\r | |
158 | \r | |
159 | /**\r | |
160 | Places the CPU in a sleep state until an interrupt is received.\r | |
161 | \r | |
162 | Places the CPU in a sleep state until an interrupt is received. If interrupts\r | |
163 | are disabled prior to calling this function, then the CPU will be placed in a\r | |
164 | sleep state indefinitely.\r | |
165 | \r | |
166 | **/\r | |
167 | VOID\r | |
168 | EFIAPI\r | |
169 | CpuSleep (\r | |
170 | VOID\r | |
171 | )\r | |
172 | {\r | |
173 | }\r |