[mirror_edk2.git] / EdkCompatibilityPkg / Foundation / Library / EdkIIGlueLib / Library / BaseLib / X64 / Thunk16.S

#------------------------------------------------------------------------------\r
#\r
# Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>\r
# This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
# which accompanies this distribution.  The full text of the license may be found at\r
# http://opensource.org/licenses/bsd-license.php\r
#\r
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
#\r
# Module Name:\r
#\r
#   Thunk16.S\r
#\r
# Abstract:\r
#\r
#   Real mode thunk\r
#\r
#------------------------------------------------------------------------------\r
\r
#include <EdkIIGlueBase.h>\r
\r
.globl ASM_PFX(m16Start)\r
.globl ASM_PFX(m16Size)\r
.globl ASM_PFX(mThunk16Attr)\r
.globl ASM_PFX(m16Gdt)\r
.globl ASM_PFX(m16GdtrBase)\r
.globl ASM_PFX(mTransition)\r
.globl ASM_PFX(InternalAsmThunk16)\r
\r
# define the structure of IA32_REGS\r
.set  _EDI, 0       #size 4\r
.set  _ESI, 4       #size 4\r
.set  _EBP, 8       #size 4\r
.set  _ESP, 12      #size 4\r
.set  _EBX, 16      #size 4\r
.set  _EDX, 20      #size 4\r
.set  _ECX, 24      #size 4\r
.set  _EAX, 28      #size 4\r
.set  _DS,  32      #size 2\r
.set  _ES,  34      #size 2\r
.set  _FS,  36      #size 2\r
.set  _GS,  38      #size 2\r
.set  _EFLAGS, 40   #size 8\r
.set  _EIP, 48      #size 4\r
.set  _CS, 52       #size 2\r
.set  _SS, 54       #size 2\r
.set  IA32_REGS_SIZE, 56\r
\r
    .data\r
    \r
#ifndef __APPLE__\r
ASM_PFX(m16Size):         .word      ASM_PFX(InternalAsmThunk16) - ASM_PFX(m16Start)\r
ASM_PFX(mThunk16Attr):    .word      _ThunkAttr - ASM_PFX(m16Start)\r
ASM_PFX(m16Gdt):          .word      ASM_PFX(NullSeg) - ASM_PFX(m16Start)\r
ASM_PFX(m16GdtrBase):     .word      _16GdtrBase - ASM_PFX(m16Start)\r
ASM_PFX(mTransition):     .word      _EntryPoint - ASM_PFX(m16Start)\r
#endif\r
\r
    .text\r
\r
ASM_PFX(m16Start):\r
\r
SavedGdt:    .space 10\r
\r
#------------------------------------------------------------------------------\r
# _BackFromUserCode() takes control in real mode after 'retf' has been executed\r
# by user code. It will be shadowed to somewhere in memory below 1MB.\r
#------------------------------------------------------------------------------\r
.globl ASM_PFX(BackFromUserCode)\r
ASM_PFX(BackFromUserCode):\r
#ifdef __APPLE__\r
    int $3\r
#else\r
    #\r
    # The order of saved registers on the stack matches the order they appears\r
    # in IA32_REGS structure. This facilitates wrapper function to extract them\r
    # into that structure.\r
    #\r
    # Some instructions for manipulation of segment registers have to be written\r
    # in opcode since 64-bit MASM prevents accesses to those registers.\r
    #\r
    .byte 0x16                          # push ss\r
    .byte 0xe                           # push cs\r
    .byte 0x66\r
    call    L_Base                       # push eip\r
L_Base: \r
    .byte 0x66\r
    pushq   $0                          # reserved high order 32 bits of EFlags\r
    .byte 0x66, 0x9c                    # pushfd actually\r
    cli                                 # disable interrupts\r
    push    %gs\r
    push    %fs\r
    .byte 6                             # push es\r
    .byte 0x1e                          # push ds\r
    .byte 0x66,0x60                     # pushad\r
    .byte 0x66,0xba                     # mov edx, imm32\r
_ThunkAttr:  .space  4\r
    testb   $THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15, %dl\r
    jz      L_1\r
    movl    $0x15cd2401,%eax            # mov ax, 2401h & int 15h\r
    cli                                 # disable interrupts\r
    jnc     L_2\r
L_1: \r
    testb   $THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL, %dl\r
    jz      L_2\r
    inb     $0x92,%al\r
    orb     $2,%al\r
    outb    %al, $0x92                   # deactivate A20M#\r
L_2: \r
    xorw    %ax,%ax                      # xor eax, eax\r
    movl    %ss,%eax                     # mov ax, ss\r
    lea     IA32_REGS_SIZE(%esp), %bp\r
    #\r
    # rsi in the following 2 instructions is indeed bp in 16-bit code\r
    #\r
    movw    %bp, (_ESP - IA32_REGS_SIZE)(%rsi)\r
    .byte 0x66\r
    movl    (_EIP - IA32_REGS_SIZE)(%rsi), %ebx\r
    shlw    $4,%ax                      # shl eax, 4\r
    addw    %ax,%bp                     # add ebp, eax\r
    movw    %cs,%ax\r
    shlw    $4,%ax\r
    lea     (L_64BitCode - L_Base)(%ebx, %eax), %ax\r
    .byte 0x66,0x2e,0x89,0x87           # mov cs:[bx + (L_64Eip - L_Base)], eax\r
    .word   L_64Eip - L_Base\r
    .byte 0x66,0xb8                     # mov eax, imm32\r
SavedCr4:   .space  4\r
    movq    %rax, %cr4\r
    #\r
    # rdi in the instruction below is indeed bx in 16-bit code\r
    #\r
    .byte 0x66,0x2e                     # 2eh is "cs:" segment override\r
    lgdt    (SavedGdt - L_Base)(%rdi)\r
    .byte 0x66\r
    movl    $0xc0000080,%ecx\r
    rdmsr\r
    orb     $1,%ah\r
    wrmsr\r
    .byte 0x66,0xb8                     # mov eax, imm32\r
SavedCr0:    .space      4\r
    movq    %rax, %cr0\r
    .byte 0x66,0xea                     # jmp far cs:L_64Bit\r
L_64Eip:     .space      4\r
SavedCs:     .space      2\r
L_64BitCode: \r
    .byte   0x90\r
    .byte   0x67,0xbc                  # mov esp, imm32\r
SavedSp:    .space 4                   # restore stack\r
    nop\r
#endif\r
    ret\r
\r
#ifndef __APPLE__\r
_EntryPoint: .long      ASM_PFX(ToUserCode) - ASM_PFX(m16Start)\r
             .word      CODE16\r
_16Gdtr:     .word      GDT_SIZE - 1\r
_16GdtrBase: .quad      ASM_PFX(NullSeg)\r
_16Idtr:     .word      0x3ff\r
             .long      0\r
#endif\r
\r
#------------------------------------------------------------------------------\r
# _ToUserCode() takes control in real mode before passing control to user code.\r
# It will be shadowed to somewhere in memory below 1MB.\r
#------------------------------------------------------------------------------\r
.globl ASM_PFX(ToUserCode)\r
ASM_PFX(ToUserCode):\r
#ifdef __APPLE__\r
    int $3\r
#else\r
    movl    %edx,%ss                    # set new segment selectors\r
    movl    %edx,%ds\r
    movl    %edx,%es\r
    movl    %edx,%fs\r
    movl    %edx,%gs\r
    .byte 0x66\r
    movl    $0xc0000080,%ecx\r
    movq    %rax, %cr0\r
    rdmsr\r
    andb    $0b11111110, %ah \r
    wrmsr\r
    movq    %rbp, %cr4\r
    movl    %esi,%ss                    # set up 16-bit stack segment\r
    movw    %bx,%sp                     # set up 16-bit stack pointer\r
    .byte 0x66                          # make the following call 32-bit\r
    call    L_Base1                       # push eip\r
L_Base1: \r
    popw    %bp                         # ebp <- address of L_Base1\r
    pushq   (IA32_REGS_SIZE + 2)(%esp)\r
    lea     0x0c(%rsi), %eax\r
    pushq   %rax\r
    lret                                # execution begins at next instruction\r
L_RealMode: \r
    .byte 0x66,0x2e                     # CS and operand size override\r
    lidt    (_16Idtr - L_Base1)(%rsi)\r
    .byte 0x66,0x61                     # popad\r
    .byte 0x1f                          # pop ds\r
    .byte 0x7                           # pop es\r
    .byte 0x0f, 0xa1                    # pop fs\r
    .byte 0x0f, 0xa9                    # pop gs\r
    .byte 0x66, 0x9d                    # popfd\r
    leaw    4(%esp),%sp                 # skip high order 32 bits of EFlags\r
    .byte 0x66                          # make the following retf 32-bit\r
#endif\r
     lret                                # transfer control to user code\r
\r
.set  CODE16,  ASM_PFX(_16Code) - .\r
.set  DATA16,  ASM_PFX(_16Data) - .\r
.set  DATA32,  ASM_PFX(_32Data) - .\r
\r
ASM_PFX(NullSeg):   .quad      0\r
ASM_PFX(_16Code):\r
            .word -1\r
            .word 0\r
            .byte 0\r
            .byte 0x9b\r
            .byte 0x8f                  # 16-bit segment, 4GB limit\r
            .byte 0\r
ASM_PFX(_16Data):\r
            .word -1\r
            .word 0\r
            .byte 0\r
            .byte 0x93\r
            .byte 0x8f                  # 16-bit segment, 4GB limit\r
            .byte 0\r
ASM_PFX(_32Data):\r
            .word -1\r
            .word 0\r
            .byte 0\r
            .byte 0x93\r
            .byte 0xcf                  # 16-bit segment, 4GB limit\r
            .byte 0\r
\r
.set  GDT_SIZE, . - ASM_PFX(NullSeg)\r
\r
#------------------------------------------------------------------------------\r
# IA32_REGISTER_SET *\r
# EFIAPI\r
# InternalAsmThunk16 (\r
#   IN      IA32_REGISTER_SET         *RegisterSet,\r
#   IN OUT  VOID                      *Transition\r
#   );\r
#------------------------------------------------------------------------------\r
\r
.globl ASM_PFX(InternalAsmThunk16)\r
ASM_PFX(InternalAsmThunk16):\r
#ifdef __APPLE__\r
    int $3\r
#else\r
    pushq   %rbp\r
    pushq   %rbx\r
    pushq   %rsi\r
    pushq   %rdi\r
    \r
    movq    %ds, %rbx\r
    pushq   %rbx      # Save ds segment register on the stack\r
    movq    %es, %rbx\r
    pushq   %rbx      # Save es segment register on the stack\r
    movq    %ss, %rbx\r
    pushq   %rbx      # Save ss segment register on the stack\r
\r
    .byte   0x0f, 0xa0                  #push   fs\r
    .byte   0x0f, 0xa8                  #push   gs\r
    movq    %rcx, %rsi\r
    movzwl  _SS(%rsi), %r8d\r
    movl    _ESP(%rsi), %edi\r
    lea     -(IA32_REGS_SIZE + 4)(%edi), %rdi\r
    imul    $16, %r8d, %eax \r
    movl    %edi,%ebx                   # ebx <- stack for 16-bit code\r
    pushq   $(IA32_REGS_SIZE / 4)\r
    addl    %eax,%edi                   # edi <- linear address of 16-bit stack\r
    popq    %rcx\r
    rep\r
    movsl                               # copy RegSet\r
    lea     (SavedCr4 - ASM_PFX(m16Start))(%rdx), %ecx\r
    movl    %edx,%eax                   # eax <- transition code address\r
    andl    $0xf,%edx\r
    shll    $12,%eax                    # segment address in high order 16 bits\r
    lea     (_BackFromUserCode - ASM_PFX(m16Start))(%rdx), %ax\r
    stosl                               # [edi] <- return address of user code\r
    sgdt    (SavedGdt - SavedCr4)(%rcx) \r
    sidt    0x50(%rsp)\r
    movq    %cr0, %rax\r
    movl    %eax, (SavedCr0 - SavedCr4)(%rcx)\r
    andl    $0x7ffffffe,%eax            # clear PE, PG bits\r
    movq    %cr4, %rbp\r
    movl    %ebp, (%rcx)                # save CR4 in SavedCr4\r
    andl    $0x300,%ebp                 # clear all but PCE and OSFXSR bits\r
    movl    %r8d, %esi                  # esi <- 16-bit stack segment\r
    .byte      0x6a, DATA32\r
    popq    %rdx\r
    lgdt    (_16Gdtr - SavedCr4)(%rcx)\r
    movl    %edx,%ss\r
    pushfq\r
    lea     -8(%rdx), %edx\r
    lea     L_RetFromRealMode, %r8\r
    pushq   %r8\r
    movl    %cs, %r8d\r
    movw    %r8w, (SavedCs - SavedCr4)(%rcx)\r
    movl    %esp, (SavedSp - SavedCr4)(%rcx)\r
    .byte   0xff, 0x69                  #  jmp (_EntryPoint - SavedCr4)(%rcx)\r
    .byte   _EntryPoint - SavedCr4\r
L_RetFromRealMode: \r
    popfq\r
    lidt    0x50(%rsp)\r
    lea     -IA32_REGS_SIZE(%rbp), %eax\r
    .byte 0x0f, 0xa9                    # pop gs\r
    .byte 0x0f, 0xa1                    # pop fs\r
    \r
    popq     %rbx\r
    movq     %rbx, %ss\r
    popq     %rbx\r
    movq     %rbx, %es\r
    popq     %rbx\r
    movq     %rbx, %ds\r
    \r
    popq    %rdi\r
    popq    %rsi\r
    popq    %rbx\r
    popq    %rbp\r
#endif\r
    ret\r
Commit	Line	Data
b341712e	1	#------------------------------------------------------------------------------\r
b341712e	2	#\r
0249feb8	3	# Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>\r
2c7e5c2f	4	# This program and the accompanying materials\r
b341712e	5	# are licensed and made available under the terms and conditions of the BSD License\r
	6	# which accompanies this distribution. The full text of the license may be found at\r
	7	# http://opensource.org/licenses/bsd-license.php\r
	8	#\r
	9	# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	10	# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	11	#\r
	12	# Module Name:\r
	13	#\r
	14	# Thunk16.S\r
	15	#\r
	16	# Abstract:\r
	17	#\r
	18	# Real mode thunk\r
	19	#\r
	20	#------------------------------------------------------------------------------\r
	21	\r
	22	#include <EdkIIGlueBase.h>\r
	23	\r
	24	.globl ASM_PFX(m16Start)\r
	25	.globl ASM_PFX(m16Size)\r
	26	.globl ASM_PFX(mThunk16Attr)\r
	27	.globl ASM_PFX(m16Gdt)\r
	28	.globl ASM_PFX(m16GdtrBase)\r
	29	.globl ASM_PFX(mTransition)\r
	30	.globl ASM_PFX(InternalAsmThunk16)\r
	31	\r
	32	# define the structure of IA32_REGS\r
271d2c7f	33	.set _EDI, 0 #size 4\r
	34	.set _ESI, 4 #size 4\r
	35	.set _EBP, 8 #size 4\r
	36	.set _ESP, 12 #size 4\r
	37	.set _EBX, 16 #size 4\r
	38	.set _EDX, 20 #size 4\r
	39	.set _ECX, 24 #size 4\r
	40	.set _EAX, 28 #size 4\r
	41	.set _DS, 32 #size 2\r
	42	.set _ES, 34 #size 2\r
	43	.set _FS, 36 #size 2\r
	44	.set _GS, 38 #size 2\r
	45	.set _EFLAGS, 40 #size 8\r
	46	.set _EIP, 48 #size 4\r
	47	.set _CS, 52 #size 2\r
	48	.set _SS, 54 #size 2\r
	49	.set IA32_REGS_SIZE, 56\r
b341712e	50	\r
b341712e	51	.data\r
271d2c7f	52	\r
271d2c7f	53	#ifndef __APPLE__\r
b341712e	54	ASM_PFX(m16Size): .word ASM_PFX(InternalAsmThunk16) - ASM_PFX(m16Start)\r
	55	ASM_PFX(mThunk16Attr): .word _ThunkAttr - ASM_PFX(m16Start)\r
	56	ASM_PFX(m16Gdt): .word ASM_PFX(NullSeg) - ASM_PFX(m16Start)\r
	57	ASM_PFX(m16GdtrBase): .word _16GdtrBase - ASM_PFX(m16Start)\r
	58	ASM_PFX(mTransition): .word _EntryPoint - ASM_PFX(m16Start)\r
271d2c7f	59	#endif\r
b341712e	60	\r
	61	.text\r
	62	\r
	63	ASM_PFX(m16Start):\r
	64	\r
	65	SavedGdt: .space 10\r
	66	\r
	67	#------------------------------------------------------------------------------\r
	68	# _BackFromUserCode() takes control in real mode after 'retf' has been executed\r
	69	# by user code. It will be shadowed to somewhere in memory below 1MB.\r
	70	#------------------------------------------------------------------------------\r
	71	.globl ASM_PFX(BackFromUserCode)\r
	72	ASM_PFX(BackFromUserCode):\r
271d2c7f	73	#ifdef __APPLE__\r
	74	int $3\r
	75	#else\r
b341712e	76	#\r
	77	# The order of saved registers on the stack matches the order they appears\r
	78	# in IA32_REGS structure. This facilitates wrapper function to extract them\r
	79	# into that structure.\r
	80	#\r
	81	# Some instructions for manipulation of segment registers have to be written\r
	82	# in opcode since 64-bit MASM prevents accesses to those registers.\r
	83	#\r
	84	.byte 0x16 # push ss\r
	85	.byte 0xe # push cs\r
	86	.byte 0x66\r
	87	call L_Base # push eip\r
	88	L_Base: \r
	89	.byte 0x66\r
	90	pushq $0 # reserved high order 32 bits of EFlags\r
	91	.byte 0x66, 0x9c # pushfd actually\r
	92	cli # disable interrupts\r
	93	push %gs\r
	94	push %fs\r
	95	.byte 6 # push es\r
	96	.byte 0x1e # push ds\r
	97	.byte 0x66,0x60 # pushad\r
	98	.byte 0x66,0xba # mov edx, imm32\r
	99	_ThunkAttr: .space 4\r
	100	testb $THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15, %dl\r
	101	jz L_1\r
	102	movl $0x15cd2401,%eax # mov ax, 2401h & int 15h\r
	103	cli # disable interrupts\r
	104	jnc L_2\r
	105	L_1: \r
	106	testb $THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL, %dl\r
	107	jz L_2\r
	108	inb $0x92,%al\r
	109	orb $2,%al\r
	110	outb %al, $0x92 # deactivate A20M#\r
	111	L_2: \r
0249feb8 LG	112	xorw %ax,%ax # xor eax, eax\r
0249feb8 LG	113	movl %ss,%eax # mov ax, ss\r
b341712e	114	lea IA32_REGS_SIZE(%esp), %bp\r
	115	#\r
	116	# rsi in the following 2 instructions is indeed bp in 16-bit code\r
	117	#\r
	118	movw %bp, (_ESP - IA32_REGS_SIZE)(%rsi)\r
	119	.byte 0x66\r
	120	movl (_EIP - IA32_REGS_SIZE)(%rsi), %ebx\r
	121	shlw $4,%ax # shl eax, 4\r
	122	addw %ax,%bp # add ebp, eax\r
	123	movw %cs,%ax\r
	124	shlw $4,%ax\r
	125	lea (L_64BitCode - L_Base)(%ebx, %eax), %ax\r
	126	.byte 0x66,0x2e,0x89,0x87 # mov cs:[bx + (L_64Eip - L_Base)], eax\r
	127	.word L_64Eip - L_Base\r
	128	.byte 0x66,0xb8 # mov eax, imm32\r
	129	SavedCr4: .space 4\r
	130	movq %rax, %cr4\r
	131	#\r
	132	# rdi in the instruction below is indeed bx in 16-bit code\r
	133	#\r
	134	.byte 0x66,0x2e # 2eh is "cs:" segment override\r
	135	lgdt (SavedGdt - L_Base)(%rdi)\r
	136	.byte 0x66\r
	137	movl $0xc0000080,%ecx\r
	138	rdmsr\r
	139	orb $1,%ah\r
	140	wrmsr\r
	141	.byte 0x66,0xb8 # mov eax, imm32\r
	142	SavedCr0: .space 4\r
	143	movq %rax, %cr0\r
	144	.byte 0x66,0xea # jmp far cs:L_64Bit\r
	145	L_64Eip: .space 4\r
	146	SavedCs: .space 2\r
	147	L_64BitCode: \r
	148	.byte 0x90\r
	149	.byte 0x67,0xbc # mov esp, imm32\r
	150	SavedSp: .space 4 # restore stack\r
	151	nop\r
271d2c7f	152	#endif\r
b341712e	153	ret\r
b341712e	154	\r
271d2c7f	155	#ifndef __APPLE__\r
b341712e	156	_EntryPoint: .long ASM_PFX(ToUserCode) - ASM_PFX(m16Start)\r
	157	.word CODE16\r
	158	_16Gdtr: .word GDT_SIZE - 1\r
	159	_16GdtrBase: .quad ASM_PFX(NullSeg)\r
	160	_16Idtr: .word 0x3ff\r
	161	.long 0\r
271d2c7f	162	#endif\r
b341712e	163	\r
	164	#------------------------------------------------------------------------------\r
	165	# _ToUserCode() takes control in real mode before passing control to user code.\r
	166	# It will be shadowed to somewhere in memory below 1MB.\r
	167	#------------------------------------------------------------------------------\r
	168	.globl ASM_PFX(ToUserCode)\r
	169	ASM_PFX(ToUserCode):\r
271d2c7f	170	#ifdef __APPLE__\r
	171	int $3\r
	172	#else\r
b341712e	173	movl %edx,%ss # set new segment selectors\r
	174	movl %edx,%ds\r
	175	movl %edx,%es\r
	176	movl %edx,%fs\r
	177	movl %edx,%gs\r
	178	.byte 0x66\r
	179	movl $0xc0000080,%ecx\r
	180	movq %rax, %cr0\r
	181	rdmsr\r
	182	andb $0b11111110, %ah \r
	183	wrmsr\r
	184	movq %rbp, %cr4\r
	185	movl %esi,%ss # set up 16-bit stack segment\r
	186	movw %bx,%sp # set up 16-bit stack pointer\r
	187	.byte 0x66 # make the following call 32-bit\r
	188	call L_Base1 # push eip\r
	189	L_Base1: \r
	190	popw %bp # ebp <- address of L_Base1\r
	191	pushq (IA32_REGS_SIZE + 2)(%esp)\r
	192	lea 0x0c(%rsi), %eax\r
	193	pushq %rax\r
	194	lret # execution begins at next instruction\r
	195	L_RealMode: \r
	196	.byte 0x66,0x2e # CS and operand size override\r
	197	lidt (_16Idtr - L_Base1)(%rsi)\r
	198	.byte 0x66,0x61 # popad\r
	199	.byte 0x1f # pop ds\r
	200	.byte 0x7 # pop es\r
	201	.byte 0x0f, 0xa1 # pop fs\r
	202	.byte 0x0f, 0xa9 # pop gs\r
	203	.byte 0x66, 0x9d # popfd\r
	204	leaw 4(%esp),%sp # skip high order 32 bits of EFlags\r
	205	.byte 0x66 # make the following retf 32-bit\r
271d2c7f	206	#endif\r
271d2c7f	207	lret # transfer control to user code\r
b341712e	208	\r
271d2c7f	209	.set CODE16, ASM_PFX(_16Code) - .\r
	210	.set DATA16, ASM_PFX(_16Data) - .\r
	211	.set DATA32, ASM_PFX(_32Data) - .\r
b341712e	212	\r
	213	ASM_PFX(NullSeg): .quad 0\r
	214	ASM_PFX(_16Code):\r
	215	.word -1\r
	216	.word 0\r
	217	.byte 0\r
	218	.byte 0x9b\r
	219	.byte 0x8f # 16-bit segment, 4GB limit\r
	220	.byte 0\r
	221	ASM_PFX(_16Data):\r
	222	.word -1\r
	223	.word 0\r
	224	.byte 0\r
	225	.byte 0x93\r
	226	.byte 0x8f # 16-bit segment, 4GB limit\r
	227	.byte 0\r
	228	ASM_PFX(_32Data):\r
	229	.word -1\r
	230	.word 0\r
	231	.byte 0\r
	232	.byte 0x93\r
	233	.byte 0xcf # 16-bit segment, 4GB limit\r
	234	.byte 0\r
	235	\r
271d2c7f	236	.set GDT_SIZE, . - ASM_PFX(NullSeg)\r
b341712e	237	\r
	238	#------------------------------------------------------------------------------\r
	239	# IA32_REGISTER_SET *\r
	240	# EFIAPI\r
	241	# InternalAsmThunk16 (\r
	242	# IN IA32_REGISTER_SET *RegisterSet,\r
	243	# IN OUT VOID *Transition\r
	244	# );\r
	245	#------------------------------------------------------------------------------\r
	246	\r
	247	.globl ASM_PFX(InternalAsmThunk16)\r
	248	ASM_PFX(InternalAsmThunk16):\r
271d2c7f	249	#ifdef __APPLE__\r
	250	int $3\r
	251	#else\r
b341712e	252	pushq %rbp\r
	253	pushq %rbx\r
	254	pushq %rsi\r
	255	pushq %rdi\r
	256	\r
	257	movq %ds, %rbx\r
	258	pushq %rbx # Save ds segment register on the stack\r
	259	movq %es, %rbx\r
	260	pushq %rbx # Save es segment register on the stack\r
	261	movq %ss, %rbx\r
	262	pushq %rbx # Save ss segment register on the stack\r
	263	\r
	264	.byte 0x0f, 0xa0 #push fs\r
	265	.byte 0x0f, 0xa8 #push gs\r
	266	movq %rcx, %rsi\r
	267	movzwl _SS(%rsi), %r8d\r
	268	movl _ESP(%rsi), %edi\r
	269	lea -(IA32_REGS_SIZE + 4)(%edi), %rdi\r
	270	imul $16, %r8d, %eax \r
	271	movl %edi,%ebx # ebx <- stack for 16-bit code\r
	272	pushq $(IA32_REGS_SIZE / 4)\r
	273	addl %eax,%edi # edi <- linear address of 16-bit stack\r
	274	popq %rcx\r
	275	rep\r
	276	movsl # copy RegSet\r
	277	lea (SavedCr4 - ASM_PFX(m16Start))(%rdx), %ecx\r
	278	movl %edx,%eax # eax <- transition code address\r
	279	andl $0xf,%edx\r
	280	shll $12,%eax # segment address in high order 16 bits\r
	281	lea (_BackFromUserCode - ASM_PFX(m16Start))(%rdx), %ax\r
	282	stosl # [edi] <- return address of user code\r
	283	sgdt (SavedGdt - SavedCr4)(%rcx) \r
	284	sidt 0x50(%rsp)\r
	285	movq %cr0, %rax\r
	286	movl %eax, (SavedCr0 - SavedCr4)(%rcx)\r
	287	andl $0x7ffffffe,%eax # clear PE, PG bits\r
	288	movq %cr4, %rbp\r
	289	movl %ebp, (%rcx) # save CR4 in SavedCr4\r
	290	andl $0x300,%ebp # clear all but PCE and OSFXSR bits\r
	291	movl %r8d, %esi # esi <- 16-bit stack segment\r
	292	.byte 0x6a, DATA32\r
	293	popq %rdx\r
	294	lgdt (_16Gdtr - SavedCr4)(%rcx)\r
	295	movl %edx,%ss\r
	296	pushfq\r
	297	lea -8(%rdx), %edx\r
	298	lea L_RetFromRealMode, %r8\r
	299	pushq %r8\r
	300	movl %cs, %r8d\r
	301	movw %r8w, (SavedCs - SavedCr4)(%rcx)\r
	302	movl %esp, (SavedSp - SavedCr4)(%rcx)\r
	303	.byte 0xff, 0x69 # jmp (_EntryPoint - SavedCr4)(%rcx)\r
	304	.byte _EntryPoint - SavedCr4\r
	305	L_RetFromRealMode: \r
	306	popfq\r
	307	lidt 0x50(%rsp)\r
	308	lea -IA32_REGS_SIZE(%rbp), %eax\r
	309	.byte 0x0f, 0xa9 # pop gs\r
	310	.byte 0x0f, 0xa1 # pop fs\r
	311	\r
	312	popq %rbx\r
	313	movq %rbx, %ss\r
	314	popq %rbx\r
	315	movq %rbx, %es\r
316	popq %rbx\r
317	movq %rbx, %ds\r
318	\r
319	popq %rdi\r
320	popq %rsi\r
321	popq %rbx\r
322	popq %rbp\r
271d2c7f	323	#endif\r
b341712e	324	ret\r