| 3eb9473e |
1 | /*++\r |
| 2 | \r |
| 3 | Copyright (c) 2004 - 2006, Intel Corporation \r |
| 4 | All rights reserved. This program and the accompanying materials \r |
| 5 | are licensed and made available under the terms and conditions of the BSD License \r |
| 6 | which accompanies this distribution. The full text of the license may be found at \r |
| 7 | http://opensource.org/licenses/bsd-license.php \r |
| 8 | \r |
| 9 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r |
| 10 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r |
| 11 | \r |
| 12 | \r |
| 13 | Module Name:\r |
| 14 | \r |
| 15 | PciLib.c\r |
| 16 | \r |
| 17 | Abstract: \r |
| 18 | \r |
| 19 | PCI Library using Port CF8/CFC access.\r |
| 20 | \r |
| 21 | --*/\r |
| 22 | \r |
| 23 | #include "EdkIIGlueBase.h"\r |
| 24 | \r |
| 25 | /**\r |
| 26 | Reads an 8-bit PCI configuration register.\r |
| 27 | \r |
| 28 | Reads and returns the 8-bit PCI configuration register specified by Address.\r |
| 29 | This function must guarantee that all PCI read and write operations are\r |
| 30 | serialized.\r |
| 31 | \r |
| 32 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 33 | \r |
| 34 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 35 | Register.\r |
| 36 | \r |
| 37 | @return The read value from the PCI configuration register.\r |
| 38 | \r |
| 39 | **/\r |
| 40 | UINT8\r |
| 41 | EFIAPI\r |
| 42 | PciRead8 (\r |
| 43 | IN UINTN Address\r |
| 44 | )\r |
| 45 | {\r |
| 46 | return PciCf8Read8 (Address);\r |
| 47 | }\r |
| 48 | \r |
| 49 | /**\r |
| 50 | Writes an 8-bit PCI configuration register.\r |
| 51 | \r |
| 52 | Writes the 8-bit PCI configuration register specified by Address with the\r |
| 53 | value specified by Value. Value is returned. This function must guarantee\r |
| 54 | that all PCI read and write operations are serialized.\r |
| 55 | \r |
| 56 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 57 | \r |
| 58 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 59 | Register.\r |
| 60 | @param Value The value to write.\r |
| 61 | \r |
| 62 | @return The value written to the PCI configuration register.\r |
| 63 | \r |
| 64 | **/\r |
| 65 | UINT8\r |
| 66 | EFIAPI\r |
| 67 | PciWrite8 (\r |
| 68 | IN UINTN Address,\r |
| 69 | IN UINT8 Data\r |
| 70 | )\r |
| 71 | {\r |
| 72 | return PciCf8Write8 (Address, Data);\r |
| 73 | }\r |
| 74 | \r |
| 75 | /**\r |
| 76 | Performs a bitwise inclusive OR of an 8-bit PCI configuration register with\r |
| 77 | an 8-bit value.\r |
| 78 | \r |
| 79 | Reads the 8-bit PCI configuration register specified by Address, performs a\r |
| 80 | bitwise inclusive OR between the read result and the value specified by\r |
| 81 | OrData, and writes the result to the 8-bit PCI configuration register\r |
| 82 | specified by Address. The value written to the PCI configuration register is\r |
| 83 | returned. This function must guarantee that all PCI read and write operations\r |
| 84 | are serialized.\r |
| 85 | \r |
| 86 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 87 | \r |
| 88 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 89 | Register.\r |
| 90 | @param OrData The value to OR with the PCI configuration register.\r |
| 91 | \r |
| 92 | @return The value written back to the PCI configuration register.\r |
| 93 | \r |
| 94 | **/\r |
| 95 | UINT8\r |
| 96 | EFIAPI\r |
| 97 | PciOr8 (\r |
| 98 | IN UINTN Address,\r |
| 99 | IN UINT8 OrData\r |
| 100 | )\r |
| 101 | {\r |
| 102 | return PciCf8Or8 (Address, OrData);\r |
| 103 | }\r |
| 104 | \r |
| 105 | /**\r |
| 106 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r |
| 107 | value.\r |
| 108 | \r |
| 109 | Reads the 8-bit PCI configuration register specified by Address, performs a\r |
| 110 | bitwise AND between the read result and the value specified by AndData, and\r |
| 111 | writes the result to the 8-bit PCI configuration register specified by\r |
| 112 | Address. The value written to the PCI configuration register is returned.\r |
| 113 | This function must guarantee that all PCI read and write operations are\r |
| 114 | serialized.\r |
| 115 | \r |
| 116 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 117 | \r |
| 118 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 119 | Register.\r |
| 120 | @param AndData The value to AND with the PCI configuration register.\r |
| 121 | \r |
| 122 | @return The value written back to the PCI configuration register.\r |
| 123 | \r |
| 124 | **/\r |
| 125 | UINT8\r |
| 126 | EFIAPI\r |
| 127 | PciAnd8 (\r |
| 128 | IN UINTN Address,\r |
| 129 | IN UINT8 AndData\r |
| 130 | )\r |
| 131 | {\r |
| 132 | return PciCf8And8 (Address, AndData);\r |
| 133 | }\r |
| 134 | \r |
| 135 | /**\r |
| 136 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r |
| 137 | value, followed a bitwise inclusive OR with another 8-bit value.\r |
| 138 | \r |
| 139 | Reads the 8-bit PCI configuration register specified by Address, performs a\r |
| 140 | bitwise AND between the read result and the value specified by AndData,\r |
| 141 | performs a bitwise inclusive OR between the result of the AND operation and\r |
| 142 | the value specified by OrData, and writes the result to the 8-bit PCI\r |
| 143 | configuration register specified by Address. The value written to the PCI\r |
| 144 | configuration register is returned. This function must guarantee that all PCI\r |
| 145 | read and write operations are serialized.\r |
| 146 | \r |
| 147 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 148 | \r |
| 149 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 150 | Register.\r |
| 151 | @param AndData The value to AND with the PCI configuration register.\r |
| 152 | @param OrData The value to OR with the result of the AND operation.\r |
| 153 | \r |
| 154 | @return The value written back to the PCI configuration register.\r |
| 155 | \r |
| 156 | **/\r |
| 157 | UINT8\r |
| 158 | EFIAPI\r |
| 159 | PciAndThenOr8 (\r |
| 160 | IN UINTN Address,\r |
| 161 | IN UINT8 AndData,\r |
| 162 | IN UINT8 OrData\r |
| 163 | )\r |
| 164 | {\r |
| 165 | return PciCf8AndThenOr8 (Address, AndData, OrData);\r |
| 166 | }\r |
| 167 | \r |
| 168 | /**\r |
| 169 | Reads a bit field of a PCI configuration register.\r |
| 170 | \r |
| 171 | Reads the bit field in an 8-bit PCI configuration register. The bit field is\r |
| 172 | specified by the StartBit and the EndBit. The value of the bit field is\r |
| 173 | returned.\r |
| 174 | \r |
| 175 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 176 | If StartBit is greater than 7, then ASSERT().\r |
| 177 | If EndBit is greater than 7, then ASSERT().\r |
| 178 | If EndBit is less than StartBit, then ASSERT().\r |
| 179 | \r |
| 180 | @param Address PCI configuration register to read.\r |
| 181 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 182 | Range 0..7.\r |
| 183 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 184 | Range 0..7.\r |
| 185 | \r |
| 186 | @return The value of the bit field read from the PCI configuration register.\r |
| 187 | \r |
| 188 | **/\r |
| 189 | UINT8\r |
| 190 | EFIAPI\r |
| 191 | PciBitFieldRead8 (\r |
| 192 | IN UINTN Address,\r |
| 193 | IN UINTN StartBit,\r |
| 194 | IN UINTN EndBit\r |
| 195 | )\r |
| 196 | {\r |
| 197 | return PciCf8BitFieldRead8 (Address, StartBit, EndBit);\r |
| 198 | }\r |
| 199 | \r |
| 200 | /**\r |
| 201 | Writes a bit field to a PCI configuration register.\r |
| 202 | \r |
| 203 | Writes Value to the bit field of the PCI configuration register. The bit\r |
| 204 | field is specified by the StartBit and the EndBit. All other bits in the\r |
| 205 | destination PCI configuration register are preserved. The new value of the\r |
| 206 | 8-bit register is returned.\r |
| 207 | \r |
| 208 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 209 | If StartBit is greater than 7, then ASSERT().\r |
| 210 | If EndBit is greater than 7, then ASSERT().\r |
| 211 | If EndBit is less than StartBit, then ASSERT().\r |
| 212 | \r |
| 213 | @param Address PCI configuration register to write.\r |
| 214 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 215 | Range 0..7.\r |
| 216 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 217 | Range 0..7.\r |
| 218 | @param Value New value of the bit field.\r |
| 219 | \r |
| 220 | @return The value written back to the PCI configuration register.\r |
| 221 | \r |
| 222 | **/\r |
| 223 | UINT8\r |
| 224 | EFIAPI\r |
| 225 | PciBitFieldWrite8 (\r |
| 226 | IN UINTN Address,\r |
| 227 | IN UINTN StartBit,\r |
| 228 | IN UINTN EndBit,\r |
| 229 | IN UINT8 Value\r |
| 230 | )\r |
| 231 | {\r |
| 232 | return PciCf8BitFieldWrite8 (Address, StartBit, EndBit, Value);\r |
| 233 | }\r |
| 234 | \r |
| 235 | /**\r |
| 236 | Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and\r |
| 237 | writes the result back to the bit field in the 8-bit port.\r |
| 238 | \r |
| 239 | Reads the 8-bit PCI configuration register specified by Address, performs a\r |
| 240 | bitwise inclusive OR between the read result and the value specified by\r |
| 241 | OrData, and writes the result to the 8-bit PCI configuration register\r |
| 242 | specified by Address. The value written to the PCI configuration register is\r |
| 243 | returned. This function must guarantee that all PCI read and write operations\r |
| 244 | are serialized. Extra left bits in OrData are stripped.\r |
| 245 | \r |
| 246 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 247 | If StartBit is greater than 7, then ASSERT().\r |
| 248 | If EndBit is greater than 7, then ASSERT().\r |
| 249 | If EndBit is less than StartBit, then ASSERT().\r |
| 250 | \r |
| 251 | @param Address PCI configuration register to write.\r |
| 252 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 253 | Range 0..7.\r |
| 254 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 255 | Range 0..7.\r |
| 256 | @param OrData The value to OR with the PCI configuration register.\r |
| 257 | \r |
| 258 | @return The value written back to the PCI configuration register.\r |
| 259 | \r |
| 260 | **/\r |
| 261 | UINT8\r |
| 262 | EFIAPI\r |
| 263 | PciBitFieldOr8 (\r |
| 264 | IN UINTN Address,\r |
| 265 | IN UINTN StartBit,\r |
| 266 | IN UINTN EndBit,\r |
| 267 | IN UINT8 OrData\r |
| 268 | )\r |
| 269 | {\r |
| 270 | return PciCf8BitFieldOr8 (Address, StartBit, EndBit, OrData);\r |
| 271 | }\r |
| 272 | \r |
| 273 | /**\r |
| 274 | Reads a bit field in an 8-bit PCI configuration register, performs a bitwise\r |
| 275 | AND, and writes the result back to the bit field in the 8-bit register.\r |
| 276 | \r |
| 277 | Reads the 8-bit PCI configuration register specified by Address, performs a\r |
| 278 | bitwise AND between the read result and the value specified by AndData, and\r |
| 279 | writes the result to the 8-bit PCI configuration register specified by\r |
| 280 | Address. The value written to the PCI configuration register is returned.\r |
| 281 | This function must guarantee that all PCI read and write operations are\r |
| 282 | serialized. Extra left bits in AndData are stripped.\r |
| 283 | \r |
| 284 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 285 | If StartBit is greater than 7, then ASSERT().\r |
| 286 | If EndBit is greater than 7, then ASSERT().\r |
| 287 | If EndBit is less than StartBit, then ASSERT().\r |
| 288 | \r |
| 289 | @param Address PCI configuration register to write.\r |
| 290 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 291 | Range 0..7.\r |
| 292 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 293 | Range 0..7.\r |
| 294 | @param AndData The value to AND with the PCI configuration register.\r |
| 295 | \r |
| 296 | @return The value written back to the PCI configuration register.\r |
| 297 | \r |
| 298 | **/\r |
| 299 | UINT8\r |
| 300 | EFIAPI\r |
| 301 | PciBitFieldAnd8 (\r |
| 302 | IN UINTN Address,\r |
| 303 | IN UINTN StartBit,\r |
| 304 | IN UINTN EndBit,\r |
| 305 | IN UINT8 AndData\r |
| 306 | )\r |
| 307 | {\r |
| 308 | return PciCf8BitFieldAnd8 (Address, StartBit, EndBit, AndData);\r |
| 309 | }\r |
| 310 | \r |
| 311 | /**\r |
| 312 | Reads a bit field in an 8-bit port, performs a bitwise AND followed by a\r |
| 313 | bitwise inclusive OR, and writes the result back to the bit field in the\r |
| 314 | 8-bit port.\r |
| 315 | \r |
| 316 | Reads the 8-bit PCI configuration register specified by Address, performs a\r |
| 317 | bitwise AND followed by a bitwise inclusive OR between the read result and\r |
| 318 | the value specified by AndData, and writes the result to the 8-bit PCI\r |
| 319 | configuration register specified by Address. The value written to the PCI\r |
| 320 | configuration register is returned. This function must guarantee that all PCI\r |
| 321 | read and write operations are serialized. Extra left bits in both AndData and\r |
| 322 | OrData are stripped.\r |
| 323 | \r |
| 324 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 325 | If StartBit is greater than 7, then ASSERT().\r |
| 326 | If EndBit is greater than 7, then ASSERT().\r |
| 327 | If EndBit is less than StartBit, then ASSERT().\r |
| 328 | \r |
| 329 | @param Address PCI configuration register to write.\r |
| 330 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 331 | Range 0..7.\r |
| 332 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 333 | Range 0..7.\r |
| 334 | @param AndData The value to AND with the PCI configuration register.\r |
| 335 | @param OrData The value to OR with the result of the AND operation.\r |
| 336 | \r |
| 337 | @return The value written back to the PCI configuration register.\r |
| 338 | \r |
| 339 | **/\r |
| 340 | UINT8\r |
| 341 | EFIAPI\r |
| 342 | PciBitFieldAndThenOr8 (\r |
| 343 | IN UINTN Address,\r |
| 344 | IN UINTN StartBit,\r |
| 345 | IN UINTN EndBit,\r |
| 346 | IN UINT8 AndData,\r |
| 347 | IN UINT8 OrData\r |
| 348 | )\r |
| 349 | {\r |
| 350 | return PciCf8BitFieldAndThenOr8 (Address, StartBit, EndBit, AndData, OrData);\r |
| 351 | }\r |
| 352 | \r |
| 353 | /**\r |
| 354 | Reads a 16-bit PCI configuration register.\r |
| 355 | \r |
| 356 | Reads and returns the 16-bit PCI configuration register specified by Address.\r |
| 357 | This function must guarantee that all PCI read and write operations are\r |
| 358 | serialized.\r |
| 359 | \r |
| 360 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 361 | \r |
| 362 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 363 | Register.\r |
| 364 | \r |
| 365 | @return The read value from the PCI configuration register.\r |
| 366 | \r |
| 367 | **/\r |
| 368 | UINT16\r |
| 369 | EFIAPI\r |
| 370 | PciRead16 (\r |
| 371 | IN UINTN Address\r |
| 372 | )\r |
| 373 | {\r |
| 374 | return PciCf8Read16 (Address);\r |
| 375 | }\r |
| 376 | \r |
| 377 | /**\r |
| 378 | Writes a 16-bit PCI configuration register.\r |
| 379 | \r |
| 380 | Writes the 16-bit PCI configuration register specified by Address with the\r |
| 381 | value specified by Value. Value is returned. This function must guarantee\r |
| 382 | that all PCI read and write operations are serialized.\r |
| 383 | \r |
| 384 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 385 | \r |
| 386 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 387 | Register.\r |
| 388 | @param Value The value to write.\r |
| 389 | \r |
| 390 | @return The value written to the PCI configuration register.\r |
| 391 | \r |
| 392 | **/\r |
| 393 | UINT16\r |
| 394 | EFIAPI\r |
| 395 | PciWrite16 (\r |
| 396 | IN UINTN Address,\r |
| 397 | IN UINT16 Data\r |
| 398 | )\r |
| 399 | {\r |
| 400 | return PciCf8Write16 (Address, Data);\r |
| 401 | }\r |
| 402 | \r |
| 403 | /**\r |
| 404 | Performs a bitwise inclusive OR of a 16-bit PCI configuration register with\r |
| 405 | a 16-bit value.\r |
| 406 | \r |
| 407 | Reads the 16-bit PCI configuration register specified by Address, performs a\r |
| 408 | bitwise inclusive OR between the read result and the value specified by\r |
| 409 | OrData, and writes the result to the 16-bit PCI configuration register\r |
| 410 | specified by Address. The value written to the PCI configuration register is\r |
| 411 | returned. This function must guarantee that all PCI read and write operations\r |
| 412 | are serialized.\r |
| 413 | \r |
| 414 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 415 | \r |
| 416 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 417 | Register.\r |
| 418 | @param OrData The value to OR with the PCI configuration register.\r |
| 419 | \r |
| 420 | @return The value written back to the PCI configuration register.\r |
| 421 | \r |
| 422 | **/\r |
| 423 | UINT16\r |
| 424 | EFIAPI\r |
| 425 | PciOr16 (\r |
| 426 | IN UINTN Address,\r |
| 427 | IN UINT16 OrData\r |
| 428 | )\r |
| 429 | {\r |
| 430 | return PciCf8Or16 (Address, OrData);\r |
| 431 | }\r |
| 432 | \r |
| 433 | /**\r |
| 434 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r |
| 435 | value.\r |
| 436 | \r |
| 437 | Reads the 16-bit PCI configuration register specified by Address, performs a\r |
| 438 | bitwise AND between the read result and the value specified by AndData, and\r |
| 439 | writes the result to the 16-bit PCI configuration register specified by\r |
| 440 | Address. The value written to the PCI configuration register is returned.\r |
| 441 | This function must guarantee that all PCI read and write operations are\r |
| 442 | serialized.\r |
| 443 | \r |
| 444 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 445 | \r |
| 446 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 447 | Register.\r |
| 448 | @param AndData The value to AND with the PCI configuration register.\r |
| 449 | \r |
| 450 | @return The value written back to the PCI configuration register.\r |
| 451 | \r |
| 452 | **/\r |
| 453 | UINT16\r |
| 454 | EFIAPI\r |
| 455 | PciAnd16 (\r |
| 456 | IN UINTN Address,\r |
| 457 | IN UINT16 AndData\r |
| 458 | )\r |
| 459 | {\r |
| 460 | return PciCf8And16 (Address, AndData);\r |
| 461 | }\r |
| 462 | \r |
| 463 | /**\r |
| 464 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r |
| 465 | value, followed a bitwise inclusive OR with another 16-bit value.\r |
| 466 | \r |
| 467 | Reads the 16-bit PCI configuration register specified by Address, performs a\r |
| 468 | bitwise AND between the read result and the value specified by AndData,\r |
| 469 | performs a bitwise inclusive OR between the result of the AND operation and\r |
| 470 | the value specified by OrData, and writes the result to the 16-bit PCI\r |
| 471 | configuration register specified by Address. The value written to the PCI\r |
| 472 | configuration register is returned. This function must guarantee that all PCI\r |
| 473 | read and write operations are serialized.\r |
| 474 | \r |
| 475 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 476 | \r |
| 477 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 478 | Register.\r |
| 479 | @param AndData The value to AND with the PCI configuration register.\r |
| 480 | @param OrData The value to OR with the result of the AND operation.\r |
| 481 | \r |
| 482 | @return The value written back to the PCI configuration register.\r |
| 483 | \r |
| 484 | **/\r |
| 485 | UINT16\r |
| 486 | EFIAPI\r |
| 487 | PciAndThenOr16 (\r |
| 488 | IN UINTN Address,\r |
| 489 | IN UINT16 AndData,\r |
| 490 | IN UINT16 OrData\r |
| 491 | )\r |
| 492 | {\r |
| 493 | return PciCf8AndThenOr16 (Address, AndData, OrData);\r |
| 494 | }\r |
| 495 | \r |
| 496 | /**\r |
| 497 | Reads a bit field of a PCI configuration register.\r |
| 498 | \r |
| 499 | Reads the bit field in a 16-bit PCI configuration register. The bit field is\r |
| 500 | specified by the StartBit and the EndBit. The value of the bit field is\r |
| 501 | returned.\r |
| 502 | \r |
| 503 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 504 | If StartBit is greater than 15, then ASSERT().\r |
| 505 | If EndBit is greater than 15, then ASSERT().\r |
| 506 | If EndBit is less than StartBit, then ASSERT().\r |
| 507 | \r |
| 508 | @param Address PCI configuration register to read.\r |
| 509 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 510 | Range 0..15.\r |
| 511 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 512 | Range 0..15.\r |
| 513 | \r |
| 514 | @return The value of the bit field read from the PCI configuration register.\r |
| 515 | \r |
| 516 | **/\r |
| 517 | UINT16\r |
| 518 | EFIAPI\r |
| 519 | PciBitFieldRead16 (\r |
| 520 | IN UINTN Address,\r |
| 521 | IN UINTN StartBit,\r |
| 522 | IN UINTN EndBit\r |
| 523 | )\r |
| 524 | {\r |
| 525 | return PciCf8BitFieldRead16 (Address, StartBit, EndBit);\r |
| 526 | }\r |
| 527 | \r |
| 528 | /**\r |
| 529 | Writes a bit field to a PCI configuration register.\r |
| 530 | \r |
| 531 | Writes Value to the bit field of the PCI configuration register. The bit\r |
| 532 | field is specified by the StartBit and the EndBit. All other bits in the\r |
| 533 | destination PCI configuration register are preserved. The new value of the\r |
| 534 | 16-bit register is returned.\r |
| 535 | \r |
| 536 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 537 | If StartBit is greater than 15, then ASSERT().\r |
| 538 | If EndBit is greater than 15, then ASSERT().\r |
| 539 | If EndBit is less than StartBit, then ASSERT().\r |
| 540 | \r |
| 541 | @param Address PCI configuration register to write.\r |
| 542 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 543 | Range 0..15.\r |
| 544 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 545 | Range 0..15.\r |
| 546 | @param Value New value of the bit field.\r |
| 547 | \r |
| 548 | @return The value written back to the PCI configuration register.\r |
| 549 | \r |
| 550 | **/\r |
| 551 | UINT16\r |
| 552 | EFIAPI\r |
| 553 | PciBitFieldWrite16 (\r |
| 554 | IN UINTN Address,\r |
| 555 | IN UINTN StartBit,\r |
| 556 | IN UINTN EndBit,\r |
| 557 | IN UINT16 Value\r |
| 558 | )\r |
| 559 | {\r |
| 560 | return PciCf8BitFieldWrite16 (Address, StartBit, EndBit, Value);\r |
| 561 | }\r |
| 562 | \r |
| 563 | /**\r |
| 564 | Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and\r |
| 565 | writes the result back to the bit field in the 16-bit port.\r |
| 566 | \r |
| 567 | Reads the 16-bit PCI configuration register specified by Address, performs a\r |
| 568 | bitwise inclusive OR between the read result and the value specified by\r |
| 569 | OrData, and writes the result to the 16-bit PCI configuration register\r |
| 570 | specified by Address. The value written to the PCI configuration register is\r |
| 571 | returned. This function must guarantee that all PCI read and write operations\r |
| 572 | are serialized. Extra left bits in OrData are stripped.\r |
| 573 | \r |
| 574 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 575 | If StartBit is greater than 15, then ASSERT().\r |
| 576 | If EndBit is greater than 15, then ASSERT().\r |
| 577 | If EndBit is less than StartBit, then ASSERT().\r |
| 578 | \r |
| 579 | @param Address PCI configuration register to write.\r |
| 580 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 581 | Range 0..15.\r |
| 582 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 583 | Range 0..15.\r |
| 584 | @param OrData The value to OR with the PCI configuration register.\r |
| 585 | \r |
| 586 | @return The value written back to the PCI configuration register.\r |
| 587 | \r |
| 588 | **/\r |
| 589 | UINT16\r |
| 590 | EFIAPI\r |
| 591 | PciBitFieldOr16 (\r |
| 592 | IN UINTN Address,\r |
| 593 | IN UINTN StartBit,\r |
| 594 | IN UINTN EndBit,\r |
| 595 | IN UINT16 OrData\r |
| 596 | )\r |
| 597 | {\r |
| 598 | return PciCf8BitFieldOr16 (Address, StartBit, EndBit, OrData);\r |
| 599 | }\r |
| 600 | \r |
| 601 | /**\r |
| 602 | Reads a bit field in a 16-bit PCI configuration register, performs a bitwise\r |
| 603 | AND, and writes the result back to the bit field in the 16-bit register.\r |
| 604 | \r |
| 605 | Reads the 16-bit PCI configuration register specified by Address, performs a\r |
| 606 | bitwise AND between the read result and the value specified by AndData, and\r |
| 607 | writes the result to the 16-bit PCI configuration register specified by\r |
| 608 | Address. The value written to the PCI configuration register is returned.\r |
| 609 | This function must guarantee that all PCI read and write operations are\r |
| 610 | serialized. Extra left bits in AndData are stripped.\r |
| 611 | \r |
| 612 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 613 | If StartBit is greater than 15, then ASSERT().\r |
| 614 | If EndBit is greater than 15, then ASSERT().\r |
| 615 | If EndBit is less than StartBit, then ASSERT().\r |
| 616 | \r |
| 617 | @param Address PCI configuration register to write.\r |
| 618 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 619 | Range 0..15.\r |
| 620 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 621 | Range 0..15.\r |
| 622 | @param AndData The value to AND with the PCI configuration register.\r |
| 623 | \r |
| 624 | @return The value written back to the PCI configuration register.\r |
| 625 | \r |
| 626 | **/\r |
| 627 | UINT16\r |
| 628 | EFIAPI\r |
| 629 | PciBitFieldAnd16 (\r |
| 630 | IN UINTN Address,\r |
| 631 | IN UINTN StartBit,\r |
| 632 | IN UINTN EndBit,\r |
| 633 | IN UINT16 AndData\r |
| 634 | )\r |
| 635 | {\r |
| 636 | return PciCf8BitFieldAnd16 (Address, StartBit, EndBit, AndData);\r |
| 637 | }\r |
| 638 | \r |
| 639 | /**\r |
| 640 | Reads a bit field in a 16-bit port, performs a bitwise AND followed by a\r |
| 641 | bitwise inclusive OR, and writes the result back to the bit field in the\r |
| 642 | 16-bit port.\r |
| 643 | \r |
| 644 | Reads the 16-bit PCI configuration register specified by Address, performs a\r |
| 645 | bitwise AND followed by a bitwise inclusive OR between the read result and\r |
| 646 | the value specified by AndData, and writes the result to the 16-bit PCI\r |
| 647 | configuration register specified by Address. The value written to the PCI\r |
| 648 | configuration register is returned. This function must guarantee that all PCI\r |
| 649 | read and write operations are serialized. Extra left bits in both AndData and\r |
| 650 | OrData are stripped.\r |
| 651 | \r |
| 652 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 653 | If StartBit is greater than 15, then ASSERT().\r |
| 654 | If EndBit is greater than 15, then ASSERT().\r |
| 655 | If EndBit is less than StartBit, then ASSERT().\r |
| 656 | \r |
| 657 | @param Address PCI configuration register to write.\r |
| 658 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 659 | Range 0..15.\r |
| 660 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 661 | Range 0..15.\r |
| 662 | @param AndData The value to AND with the PCI configuration register.\r |
| 663 | @param OrData The value to OR with the result of the AND operation.\r |
| 664 | \r |
| 665 | @return The value written back to the PCI configuration register.\r |
| 666 | \r |
| 667 | **/\r |
| 668 | UINT16\r |
| 669 | EFIAPI\r |
| 670 | PciBitFieldAndThenOr16 (\r |
| 671 | IN UINTN Address,\r |
| 672 | IN UINTN StartBit,\r |
| 673 | IN UINTN EndBit,\r |
| 674 | IN UINT16 AndData,\r |
| 675 | IN UINT16 OrData\r |
| 676 | )\r |
| 677 | {\r |
| 678 | return PciCf8BitFieldAndThenOr16 (Address, StartBit, EndBit, AndData, OrData);\r |
| 679 | }\r |
| 680 | \r |
| 681 | /**\r |
| 682 | Reads a 32-bit PCI configuration register.\r |
| 683 | \r |
| 684 | Reads and returns the 32-bit PCI configuration register specified by Address.\r |
| 685 | This function must guarantee that all PCI read and write operations are\r |
| 686 | serialized.\r |
| 687 | \r |
| 688 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 689 | \r |
| 690 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 691 | Register.\r |
| 692 | \r |
| 693 | @return The read value from the PCI configuration register.\r |
| 694 | \r |
| 695 | **/\r |
| 696 | UINT32\r |
| 697 | EFIAPI\r |
| 698 | PciRead32 (\r |
| 699 | IN UINTN Address\r |
| 700 | )\r |
| 701 | {\r |
| 702 | return PciCf8Read32 (Address);\r |
| 703 | }\r |
| 704 | \r |
| 705 | /**\r |
| 706 | Writes a 32-bit PCI configuration register.\r |
| 707 | \r |
| 708 | Writes the 32-bit PCI configuration register specified by Address with the\r |
| 709 | value specified by Value. Value is returned. This function must guarantee\r |
| 710 | that all PCI read and write operations are serialized.\r |
| 711 | \r |
| 712 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 713 | \r |
| 714 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 715 | Register.\r |
| 716 | @param Value The value to write.\r |
| 717 | \r |
| 718 | @return The value written to the PCI configuration register.\r |
| 719 | \r |
| 720 | **/\r |
| 721 | UINT32\r |
| 722 | EFIAPI\r |
| 723 | PciWrite32 (\r |
| 724 | IN UINTN Address,\r |
| 725 | IN UINT32 Data\r |
| 726 | )\r |
| 727 | {\r |
| 728 | return PciCf8Write32 (Address, Data);\r |
| 729 | }\r |
| 730 | \r |
| 731 | /**\r |
| 732 | Performs a bitwise inclusive OR of a 32-bit PCI configuration register with\r |
| 733 | a 32-bit value.\r |
| 734 | \r |
| 735 | Reads the 32-bit PCI configuration register specified by Address, performs a\r |
| 736 | bitwise inclusive OR between the read result and the value specified by\r |
| 737 | OrData, and writes the result to the 32-bit PCI configuration register\r |
| 738 | specified by Address. The value written to the PCI configuration register is\r |
| 739 | returned. This function must guarantee that all PCI read and write operations\r |
| 740 | are serialized.\r |
| 741 | \r |
| 742 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 743 | \r |
| 744 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 745 | Register.\r |
| 746 | @param OrData The value to OR with the PCI configuration register.\r |
| 747 | \r |
| 748 | @return The value written back to the PCI configuration register.\r |
| 749 | \r |
| 750 | **/\r |
| 751 | UINT32\r |
| 752 | EFIAPI\r |
| 753 | PciOr32 (\r |
| 754 | IN UINTN Address,\r |
| 755 | IN UINT32 OrData\r |
| 756 | )\r |
| 757 | {\r |
| 758 | return PciCf8Or32 (Address, OrData);\r |
| 759 | }\r |
| 760 | \r |
| 761 | /**\r |
| 762 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r |
| 763 | value.\r |
| 764 | \r |
| 765 | Reads the 32-bit PCI configuration register specified by Address, performs a\r |
| 766 | bitwise AND between the read result and the value specified by AndData, and\r |
| 767 | writes the result to the 32-bit PCI configuration register specified by\r |
| 768 | Address. The value written to the PCI configuration register is returned.\r |
| 769 | This function must guarantee that all PCI read and write operations are\r |
| 770 | serialized.\r |
| 771 | \r |
| 772 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 773 | \r |
| 774 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 775 | Register.\r |
| 776 | @param AndData The value to AND with the PCI configuration register.\r |
| 777 | \r |
| 778 | @return The value written back to the PCI configuration register.\r |
| 779 | \r |
| 780 | **/\r |
| 781 | UINT32\r |
| 782 | EFIAPI\r |
| 783 | PciAnd32 (\r |
| 784 | IN UINTN Address,\r |
| 785 | IN UINT32 AndData\r |
| 786 | )\r |
| 787 | {\r |
| 788 | return PciCf8And32 (Address, AndData);\r |
| 789 | }\r |
| 790 | \r |
| 791 | /**\r |
| 792 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r |
| 793 | value, followed a bitwise inclusive OR with another 32-bit value.\r |
| 794 | \r |
| 795 | Reads the 32-bit PCI configuration register specified by Address, performs a\r |
| 796 | bitwise AND between the read result and the value specified by AndData,\r |
| 797 | performs a bitwise inclusive OR between the result of the AND operation and\r |
| 798 | the value specified by OrData, and writes the result to the 32-bit PCI\r |
| 799 | configuration register specified by Address. The value written to the PCI\r |
| 800 | configuration register is returned. This function must guarantee that all PCI\r |
| 801 | read and write operations are serialized.\r |
| 802 | \r |
| 803 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 804 | \r |
| 805 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 806 | Register.\r |
| 807 | @param AndData The value to AND with the PCI configuration register.\r |
| 808 | @param OrData The value to OR with the result of the AND operation.\r |
| 809 | \r |
| 810 | @return The value written back to the PCI configuration register.\r |
| 811 | \r |
| 812 | **/\r |
| 813 | UINT32\r |
| 814 | EFIAPI\r |
| 815 | PciAndThenOr32 (\r |
| 816 | IN UINTN Address,\r |
| 817 | IN UINT32 AndData,\r |
| 818 | IN UINT32 OrData\r |
| 819 | )\r |
| 820 | {\r |
| 821 | return PciCf8AndThenOr32 (Address, AndData, OrData);\r |
| 822 | }\r |
| 823 | \r |
| 824 | /**\r |
| 825 | Reads a bit field of a PCI configuration register.\r |
| 826 | \r |
| 827 | Reads the bit field in a 32-bit PCI configuration register. The bit field is\r |
| 828 | specified by the StartBit and the EndBit. The value of the bit field is\r |
| 829 | returned.\r |
| 830 | \r |
| 831 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 832 | If StartBit is greater than 31, then ASSERT().\r |
| 833 | If EndBit is greater than 31, then ASSERT().\r |
| 834 | If EndBit is less than StartBit, then ASSERT().\r |
| 835 | \r |
| 836 | @param Address PCI configuration register to read.\r |
| 837 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 838 | Range 0..31.\r |
| 839 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 840 | Range 0..31.\r |
| 841 | \r |
| 842 | @return The value of the bit field read from the PCI configuration register.\r |
| 843 | \r |
| 844 | **/\r |
| 845 | UINT32\r |
| 846 | EFIAPI\r |
| 847 | PciBitFieldRead32 (\r |
| 848 | IN UINTN Address,\r |
| 849 | IN UINTN StartBit,\r |
| 850 | IN UINTN EndBit\r |
| 851 | )\r |
| 852 | {\r |
| 853 | return PciCf8BitFieldRead32 (Address, StartBit, EndBit);\r |
| 854 | }\r |
| 855 | \r |
| 856 | /**\r |
| 857 | Writes a bit field to a PCI configuration register.\r |
| 858 | \r |
| 859 | Writes Value to the bit field of the PCI configuration register. The bit\r |
| 860 | field is specified by the StartBit and the EndBit. All other bits in the\r |
| 861 | destination PCI configuration register are preserved. The new value of the\r |
| 862 | 32-bit register is returned.\r |
| 863 | \r |
| 864 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 865 | If StartBit is greater than 31, then ASSERT().\r |
| 866 | If EndBit is greater than 31, then ASSERT().\r |
| 867 | If EndBit is less than StartBit, then ASSERT().\r |
| 868 | \r |
| 869 | @param Address PCI configuration register to write.\r |
| 870 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 871 | Range 0..31.\r |
| 872 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 873 | Range 0..31.\r |
| 874 | @param Value New value of the bit field.\r |
| 875 | \r |
| 876 | @return The value written back to the PCI configuration register.\r |
| 877 | \r |
| 878 | **/\r |
| 879 | UINT32\r |
| 880 | EFIAPI\r |
| 881 | PciBitFieldWrite32 (\r |
| 882 | IN UINTN Address,\r |
| 883 | IN UINTN StartBit,\r |
| 884 | IN UINTN EndBit,\r |
| 885 | IN UINT32 Value\r |
| 886 | )\r |
| 887 | {\r |
| 888 | return PciCf8BitFieldWrite32 (Address, StartBit, EndBit, Value);\r |
| 889 | }\r |
| 890 | \r |
| 891 | /**\r |
| 892 | Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and\r |
| 893 | writes the result back to the bit field in the 32-bit port.\r |
| 894 | \r |
| 895 | Reads the 32-bit PCI configuration register specified by Address, performs a\r |
| 896 | bitwise inclusive OR between the read result and the value specified by\r |
| 897 | OrData, and writes the result to the 32-bit PCI configuration register\r |
| 898 | specified by Address. The value written to the PCI configuration register is\r |
| 899 | returned. This function must guarantee that all PCI read and write operations\r |
| 900 | are serialized. Extra left bits in OrData are stripped.\r |
| 901 | \r |
| 902 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 903 | If StartBit is greater than 31, then ASSERT().\r |
| 904 | If EndBit is greater than 31, then ASSERT().\r |
| 905 | If EndBit is less than StartBit, then ASSERT().\r |
| 906 | \r |
| 907 | @param Address PCI configuration register to write.\r |
| 908 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 909 | Range 0..31.\r |
| 910 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 911 | Range 0..31.\r |
| 912 | @param OrData The value to OR with the PCI configuration register.\r |
| 913 | \r |
| 914 | @return The value written back to the PCI configuration register.\r |
| 915 | \r |
| 916 | **/\r |
| 917 | UINT32\r |
| 918 | EFIAPI\r |
| 919 | PciBitFieldOr32 (\r |
| 920 | IN UINTN Address,\r |
| 921 | IN UINTN StartBit,\r |
| 922 | IN UINTN EndBit,\r |
| 923 | IN UINT32 OrData\r |
| 924 | )\r |
| 925 | {\r |
| 926 | return PciCf8BitFieldOr32 (Address, StartBit, EndBit, OrData);\r |
| 927 | }\r |
| 928 | \r |
| 929 | /**\r |
| 930 | Reads a bit field in a 32-bit PCI configuration register, performs a bitwise\r |
| 931 | AND, and writes the result back to the bit field in the 32-bit register.\r |
| 932 | \r |
| 933 | Reads the 32-bit PCI configuration register specified by Address, performs a\r |
| 934 | bitwise AND between the read result and the value specified by AndData, and\r |
| 935 | writes the result to the 32-bit PCI configuration register specified by\r |
| 936 | Address. The value written to the PCI configuration register is returned.\r |
| 937 | This function must guarantee that all PCI read and write operations are\r |
| 938 | serialized. Extra left bits in AndData are stripped.\r |
| 939 | \r |
| 940 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 941 | If StartBit is greater than 31, then ASSERT().\r |
| 942 | If EndBit is greater than 31, then ASSERT().\r |
| 943 | If EndBit is less than StartBit, then ASSERT().\r |
| 944 | \r |
| 945 | @param Address PCI configuration register to write.\r |
| 946 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 947 | Range 0..31.\r |
| 948 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 949 | Range 0..31.\r |
| 950 | @param AndData The value to AND with the PCI configuration register.\r |
| 951 | \r |
| 952 | @return The value written back to the PCI configuration register.\r |
| 953 | \r |
| 954 | **/\r |
| 955 | UINT32\r |
| 956 | EFIAPI\r |
| 957 | PciBitFieldAnd32 (\r |
| 958 | IN UINTN Address,\r |
| 959 | IN UINTN StartBit,\r |
| 960 | IN UINTN EndBit,\r |
| 961 | IN UINT32 AndData\r |
| 962 | )\r |
| 963 | {\r |
| 964 | return PciCf8BitFieldAnd32 (Address, StartBit, EndBit, AndData);\r |
| 965 | }\r |
| 966 | \r |
| 967 | /**\r |
| 968 | Reads a bit field in a 32-bit port, performs a bitwise AND followed by a\r |
| 969 | bitwise inclusive OR, and writes the result back to the bit field in the\r |
| 970 | 32-bit port.\r |
| 971 | \r |
| 972 | Reads the 32-bit PCI configuration register specified by Address, performs a\r |
| 973 | bitwise AND followed by a bitwise inclusive OR between the read result and\r |
| 974 | the value specified by AndData, and writes the result to the 32-bit PCI\r |
| 975 | configuration register specified by Address. The value written to the PCI\r |
| 976 | configuration register is returned. This function must guarantee that all PCI\r |
| 977 | read and write operations are serialized. Extra left bits in both AndData and\r |
| 978 | OrData are stripped.\r |
| 979 | \r |
| 980 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 981 | If StartBit is greater than 31, then ASSERT().\r |
| 982 | If EndBit is greater than 31, then ASSERT().\r |
| 983 | If EndBit is less than StartBit, then ASSERT().\r |
| 984 | \r |
| 985 | @param Address PCI configuration register to write.\r |
| 986 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 987 | Range 0..31.\r |
| 988 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 989 | Range 0..31.\r |
| 990 | @param AndData The value to AND with the PCI configuration register.\r |
| 991 | @param OrData The value to OR with the result of the AND operation.\r |
| 992 | \r |
| 993 | @return The value written back to the PCI configuration register.\r |
| 994 | \r |
| 995 | **/\r |
| 996 | UINT32\r |
| 997 | EFIAPI\r |
| 998 | PciBitFieldAndThenOr32 (\r |
| 999 | IN UINTN Address,\r |
| 1000 | IN UINTN StartBit,\r |
| 1001 | IN UINTN EndBit,\r |
| 1002 | IN UINT32 AndData,\r |
| 1003 | IN UINT32 OrData\r |
| 1004 | )\r |
| 1005 | {\r |
| 1006 | return PciCf8BitFieldAndThenOr32 (Address, StartBit, EndBit, AndData, OrData);\r |
| 1007 | }\r |
| 1008 | \r |
| 1009 | /**\r |
| 1010 | Reads a range of PCI configuration registers into a caller supplied buffer.\r |
| 1011 | \r |
| 1012 | Reads the range of PCI configuration registers specified by StartAddress and\r |
| 1013 | Size into the buffer specified by Buffer. This function only allows the PCI\r |
| 1014 | configuration registers from a single PCI function to be read. Size is\r |
| 1015 | returned. When possible 32-bit PCI configuration read cycles are used to read\r |
| 1016 | from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit\r |
| 1017 | and 16-bit PCI configuration read cycles may be used at the beginning and the\r |
| 1018 | end of the range.\r |
| 1019 | \r |
| 1020 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r |
| 1021 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r |
| 1022 | If Size > 0 and Buffer is NULL, then ASSERT().\r |
| 1023 | \r |
| 1024 | @param StartAddress Starting address that encodes the PCI Bus, Device,\r |
| 1025 | Function and Register.\r |
| 1026 | @param Size Size in bytes of the transfer.\r |
| 1027 | @param Buffer Pointer to a buffer receiving the data read.\r |
| 1028 | \r |
| 1029 | @return Size\r |
| 1030 | \r |
| 1031 | **/\r |
| 1032 | UINTN\r |
| 1033 | EFIAPI\r |
| 1034 | PciReadBuffer (\r |
| 1035 | IN UINTN StartAddress,\r |
| 1036 | IN UINTN Size,\r |
| 1037 | OUT VOID *Buffer\r |
| 1038 | )\r |
| 1039 | {\r |
| 1040 | return PciCf8ReadBuffer (StartAddress, Size, Buffer);\r |
| 1041 | }\r |
| 1042 | \r |
| 1043 | /**\r |
| 1044 | Copies the data in a caller supplied buffer to a specified range of PCI\r |
| 1045 | configuration space.\r |
| 1046 | \r |
| 1047 | Writes the range of PCI configuration registers specified by StartAddress and\r |
| 1048 | Size from the buffer specified by Buffer. This function only allows the PCI\r |
| 1049 | configuration registers from a single PCI function to be written. Size is\r |
| 1050 | returned. When possible 32-bit PCI configuration write cycles are used to\r |
| 1051 | write from StartAdress to StartAddress + Size. Due to alignment restrictions,\r |
| 1052 | 8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r |
| 1053 | and the end of the range.\r |
| 1054 | \r |
| 1055 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r |
| 1056 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r |
| 1057 | If Size > 0 and Buffer is NULL, then ASSERT().\r |
| 1058 | \r |
| 1059 | @param StartAddress Starting address that encodes the PCI Bus, Device,\r |
| 1060 | Function and Register.\r |
| 1061 | @param Size Size in bytes of the transfer.\r |
| 1062 | @param Buffer Pointer to a buffer containing the data to write.\r |
| 1063 | \r |
| 1064 | @return Size\r |
| 1065 | \r |
| 1066 | **/\r |
| 1067 | UINTN\r |
| 1068 | EFIAPI\r |
| 1069 | PciWriteBuffer (\r |
| 1070 | IN UINTN StartAddress,\r |
| 1071 | IN UINTN Size,\r |
| 1072 | IN VOID *Buffer\r |
| 1073 | )\r |
| 1074 | {\r |
| 1075 | return PciCf8WriteBuffer (StartAddress, Size, Buffer);\r |
| 1076 | }\r |
projects / mirror_edk2.git / blame