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3eb9473e | 1 | /*++\r |
2 | \r | |
2c7e5c2f HT |
3 | Copyright (c) 2004 - 2006, Intel Corporation. All rights reserved.<BR>\r |
4 | This program and the accompanying materials \r | |
3eb9473e | 5 | are licensed and made available under the terms and conditions of the BSD License \r |
6 | which accompanies this distribution. The full text of the license may be found at \r | |
7 | http://opensource.org/licenses/bsd-license.php \r | |
8 | \r | |
9 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r | |
10 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r | |
11 | \r | |
12 | \r | |
13 | Module Name:\r | |
14 | \r | |
15 | EbcTimerLib.c\r | |
16 | \r | |
17 | Abstract: \r | |
18 | \r | |
19 | Timer Library functions built upon local APIC on IA32/x64.\r | |
20 | \r | |
21 | @bug Should use PCD to retrieve all the constants including index of\r | |
22 | the IA32_APIC_BASE MSR, the offsets of InitialCount, CorrentCount\r | |
23 | and DivideConfiguration.\r | |
24 | \r | |
25 | --*/\r | |
26 | \r | |
27 | #include "EdkIIGlueBase.h"\r | |
28 | \r | |
29 | /**\r | |
30 | Stalls the CPU for at least the given number of microseconds.\r | |
31 | \r | |
32 | Stalls the CPU for the number of microseconds specified by MicroSeconds.\r | |
33 | \r | |
34 | @param MicroSeconds The minimum number of microseconds to delay.\r | |
35 | \r | |
36 | @return MicroSeconds\r | |
37 | \r | |
38 | **/\r | |
39 | UINTN\r | |
40 | EFIAPI\r | |
41 | MicroSecondDelay (\r | |
42 | IN UINTN MicroSeconds\r | |
43 | )\r | |
44 | {\r | |
45 | //\r | |
46 | // EBC architecture does not support local APIC timer.\r | |
47 | //\r | |
48 | ASSERT (FALSE);\r | |
49 | return MicroSeconds;\r | |
50 | }\r | |
51 | \r | |
52 | /**\r | |
53 | Stalls the CPU for at least the given number of nanoseconds.\r | |
54 | \r | |
55 | Stalls the CPU for the number of nanoseconds specified by NanoSeconds.\r | |
56 | \r | |
57 | @param NanoSeconds The minimum number of nanoseconds to delay.\r | |
58 | \r | |
59 | @return NanoSeconds\r | |
60 | \r | |
61 | **/\r | |
62 | UINTN\r | |
63 | EFIAPI\r | |
64 | NanoSecondDelay (\r | |
65 | IN UINTN NanoSeconds\r | |
66 | )\r | |
67 | {\r | |
68 | //\r | |
69 | // EBC architecture does not support local APIC timer.\r | |
70 | //\r | |
71 | ASSERT (FALSE);\r | |
72 | return NanoSeconds;\r | |
73 | }\r | |
74 | \r | |
75 | /**\r | |
76 | Retrieves the current value of a 64-bit free running performance counter.\r | |
77 | \r | |
78 | Retrieves the current value of a 64-bit free running performance counter. The\r | |
79 | counter can either count up by 1 or count down by 1. If the physical\r | |
80 | performance counter counts by a larger increment, then the counter values\r | |
81 | must be translated. The properties of the counter can be retrieved from\r | |
82 | GetPerformanceCounterProperties().\r | |
83 | \r | |
84 | @return The current value of the free running performance counter.\r | |
85 | \r | |
86 | **/\r | |
87 | UINT64\r | |
88 | EFIAPI\r | |
89 | GetPerformanceCounter (\r | |
90 | VOID\r | |
91 | )\r | |
92 | {\r | |
93 | //\r | |
94 | // EBC architecture does not support local APIC timer.\r | |
95 | //\r | |
96 | ASSERT (FALSE);\r | |
97 | return 0;\r | |
98 | }\r | |
99 | \r | |
100 | /**\r | |
101 | Retrieves the 64-bit frequency in Hz and the range of performance counter\r | |
102 | values.\r | |
103 | \r | |
104 | If StartValue is not NULL, then the value that the performance counter starts\r | |
105 | with immediately after is it rolls over is returned in StartValue. If\r | |
106 | EndValue is not NULL, then the value that the performance counter end with\r | |
107 | immediately before it rolls over is returned in EndValue. The 64-bit\r | |
108 | frequency of the performance counter in Hz is always returned. If StartValue\r | |
109 | is less than EndValue, then the performance counter counts up. If StartValue\r | |
110 | is greater than EndValue, then the performance counter counts down. For\r | |
111 | example, a 64-bit free running counter that counts up would have a StartValue\r | |
112 | of 0 and an EndValue of 0xFFFFFFFFFFFFFFFF. A 24-bit free running counter\r | |
113 | that counts down would have a StartValue of 0xFFFFFF and an EndValue of 0.\r | |
114 | \r | |
115 | @param StartValue The value the performance counter starts with when it\r | |
116 | rolls over.\r | |
117 | @param EndValue The value that the performance counter ends with before\r | |
118 | it rolls over.\r | |
119 | \r | |
120 | @return The frequency in Hz.\r | |
121 | \r | |
122 | **/\r | |
123 | UINT64\r | |
124 | EFIAPI\r | |
125 | GetPerformanceCounterProperties (\r | |
126 | OUT UINT64 *StartValue, OPTIONAL\r | |
127 | OUT UINT64 *EndValue OPTIONAL\r | |
128 | )\r | |
129 | {\r | |
130 | //\r | |
131 | // EBC architecture does not support local APIC timer.\r | |
132 | //\r | |
133 | ASSERT (FALSE);\r | |
134 | return 0;\r | |
135 | }\r |