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878ddf1f | 1 | /*++\r |
2 | \r | |
3 | Copyright (c) 2006, Intel Corporation \r | |
4 | All rights reserved. This program and the accompanying materials \r | |
5 | are licensed and made available under the terms and conditions of the BSD License \r | |
6 | which accompanies this distribution. The full text of the license may be found at \r | |
7 | http://opensource.org/licenses/bsd-license.php \r | |
8 | \r | |
9 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r | |
10 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r | |
11 | \r | |
12 | Module Name:\r | |
13 | \r | |
14 | Uhci.c\r | |
15 | \r | |
16 | Abstract: \r | |
17 | \r | |
18 | \r | |
19 | Revision History\r | |
20 | --*/\r | |
21 | \r | |
22 | #include "uhci.h"\r | |
23 | \r | |
24 | //\r | |
25 | // Prototypes\r | |
26 | // Driver model protocol interface\r | |
27 | //\r | |
28 | \r | |
878ddf1f | 29 | EFI_STATUS\r |
30 | EFIAPI\r | |
31 | UHCIDriverBindingSupported (\r | |
32 | IN EFI_DRIVER_BINDING_PROTOCOL *This,\r | |
33 | IN EFI_HANDLE Controller,\r | |
34 | IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath\r | |
35 | );\r | |
36 | \r | |
37 | EFI_STATUS\r | |
38 | EFIAPI\r | |
39 | UHCIDriverBindingStart (\r | |
40 | IN EFI_DRIVER_BINDING_PROTOCOL *This,\r | |
41 | IN EFI_HANDLE Controller,\r | |
42 | IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath\r | |
43 | );\r | |
44 | \r | |
45 | EFI_STATUS\r | |
46 | EFIAPI\r | |
47 | UHCIDriverBindingStop (\r | |
48 | IN EFI_DRIVER_BINDING_PROTOCOL *This,\r | |
49 | IN EFI_HANDLE Controller,\r | |
50 | IN UINTN NumberOfChildren,\r | |
51 | IN EFI_HANDLE *ChildHandleBuffer\r | |
52 | );\r | |
53 | \r | |
54 | //\r | |
55 | // UHCI interface functions\r | |
56 | //\r | |
57 | \r | |
58 | EFI_STATUS\r | |
59 | EFIAPI\r | |
60 | UHCIReset (\r | |
61 | IN EFI_USB_HC_PROTOCOL *This,\r | |
62 | IN UINT16 Attributes\r | |
63 | );\r | |
64 | \r | |
65 | EFI_STATUS\r | |
66 | EFIAPI\r | |
67 | UHCIGetState (\r | |
68 | IN EFI_USB_HC_PROTOCOL *This,\r | |
69 | OUT EFI_USB_HC_STATE *State\r | |
70 | );\r | |
71 | \r | |
72 | EFI_STATUS\r | |
73 | EFIAPI\r | |
74 | UHCISetState (\r | |
75 | IN EFI_USB_HC_PROTOCOL *This,\r | |
76 | IN EFI_USB_HC_STATE State\r | |
77 | );\r | |
78 | \r | |
79 | EFI_STATUS\r | |
80 | EFIAPI\r | |
81 | UHCIControlTransfer (\r | |
82 | IN EFI_USB_HC_PROTOCOL *This,\r | |
83 | IN UINT8 DeviceAddress,\r | |
84 | IN BOOLEAN IsSlowDevice,\r | |
85 | IN UINT8 MaximumPacketLength,\r | |
86 | IN EFI_USB_DEVICE_REQUEST *Request,\r | |
87 | IN EFI_USB_DATA_DIRECTION TransferDirection,\r | |
88 | IN OUT VOID *Data, OPTIONAL\r | |
89 | IN OUT UINTN *DataLength, OPTIONAL\r | |
90 | IN UINTN TimeOut,\r | |
91 | OUT UINT32 *TransferResult\r | |
92 | );\r | |
93 | \r | |
94 | EFI_STATUS\r | |
95 | EFIAPI\r | |
96 | UHCIBulkTransfer (\r | |
97 | IN EFI_USB_HC_PROTOCOL *This,\r | |
98 | IN UINT8 DeviceAddress,\r | |
99 | IN UINT8 EndPointAddress,\r | |
100 | IN UINT8 MaximumPacketLength,\r | |
101 | IN OUT VOID *Data,\r | |
102 | IN OUT UINTN *DataLength,\r | |
103 | IN OUT UINT8 *DataToggle,\r | |
104 | IN UINTN TimeOut,\r | |
105 | OUT UINT32 *TransferResult\r | |
106 | );\r | |
107 | \r | |
108 | EFI_STATUS\r | |
109 | EFIAPI\r | |
110 | UHCIAsyncInterruptTransfer (\r | |
111 | IN EFI_USB_HC_PROTOCOL * This,\r | |
112 | IN UINT8 DeviceAddress,\r | |
113 | IN UINT8 EndPointAddress,\r | |
114 | IN BOOLEAN IsSlowDevice,\r | |
562d2849 | 115 | IN UINT8 MaximumPacketLength,\r |
878ddf1f | 116 | IN BOOLEAN IsNewTransfer,\r |
117 | IN OUT UINT8 *DataToggle,\r | |
118 | IN UINTN PollingInterval, OPTIONAL\r | |
119 | IN UINTN DataLength, OPTIONAL\r | |
120 | IN EFI_ASYNC_USB_TRANSFER_CALLBACK CallBackFunction, OPTIONAL\r | |
121 | IN VOID *Context OPTIONAL\r | |
122 | );\r | |
123 | \r | |
124 | EFI_STATUS\r | |
125 | EFIAPI\r | |
126 | UHCISyncInterruptTransfer (\r | |
127 | IN EFI_USB_HC_PROTOCOL *This,\r | |
128 | IN UINT8 DeviceAddress,\r | |
129 | IN UINT8 EndPointAddress,\r | |
130 | IN BOOLEAN IsSlowDevice,\r | |
131 | IN UINT8 MaximumPacketLength,\r | |
132 | IN OUT VOID *Data,\r | |
133 | IN OUT UINTN *DataLength,\r | |
134 | IN OUT UINT8 *DataToggle,\r | |
135 | IN UINTN TimeOut,\r | |
136 | OUT UINT32 *TransferResult\r | |
137 | );\r | |
138 | \r | |
139 | EFI_STATUS\r | |
140 | EFIAPI\r | |
141 | UHCIIsochronousTransfer (\r | |
142 | IN EFI_USB_HC_PROTOCOL *This,\r | |
143 | IN UINT8 DeviceAddress,\r | |
144 | IN UINT8 EndPointAddress,\r | |
145 | IN UINT8 MaximumPacketLength,\r | |
146 | IN OUT VOID *Data,\r | |
147 | IN UINTN DataLength,\r | |
148 | OUT UINT32 *TransferResult\r | |
149 | );\r | |
150 | \r | |
151 | EFI_STATUS\r | |
152 | EFIAPI\r | |
153 | UHCIAsyncIsochronousTransfer (\r | |
154 | IN EFI_USB_HC_PROTOCOL * This,\r | |
155 | IN UINT8 DeviceAddress,\r | |
156 | IN UINT8 EndPointAddress,\r | |
157 | IN UINT8 MaximumPacketLength,\r | |
158 | IN OUT VOID *Data,\r | |
159 | IN UINTN DataLength,\r | |
160 | IN EFI_ASYNC_USB_TRANSFER_CALLBACK IsochronousCallBack,\r | |
161 | IN VOID *Context OPTIONAL\r | |
162 | );\r | |
163 | \r | |
164 | EFI_STATUS\r | |
165 | EFIAPI\r | |
166 | UHCIGetRootHubPortNumber (\r | |
167 | IN EFI_USB_HC_PROTOCOL *This,\r | |
168 | OUT UINT8 *PortNumber\r | |
169 | );\r | |
170 | \r | |
171 | EFI_STATUS\r | |
172 | EFIAPI\r | |
173 | UHCIGetRootHubPortStatus (\r | |
174 | IN EFI_USB_HC_PROTOCOL *This,\r | |
175 | IN UINT8 PortNumber,\r | |
176 | OUT EFI_USB_PORT_STATUS *PortStatus\r | |
177 | );\r | |
178 | \r | |
179 | EFI_STATUS\r | |
180 | EFIAPI\r | |
181 | UHCISetRootHubPortFeature (\r | |
182 | IN EFI_USB_HC_PROTOCOL *This,\r | |
183 | IN UINT8 PortNumber,\r | |
184 | IN EFI_USB_PORT_FEATURE PortFeature\r | |
185 | );\r | |
186 | \r | |
187 | EFI_STATUS\r | |
188 | EFIAPI\r | |
189 | UHCIClearRootHubPortFeature (\r | |
190 | IN EFI_USB_HC_PROTOCOL *This,\r | |
191 | IN UINT8 PortNumber,\r | |
192 | IN EFI_USB_PORT_FEATURE PortFeature\r | |
193 | );\r | |
194 | \r | |
562d2849 | 195 | //\r |
196 | // UEFI 2.0 Protocol\r | |
197 | //\r | |
198 | \r | |
199 | EFI_STATUS\r | |
200 | EFIAPI\r | |
201 | UHCI2GetCapability(\r | |
202 | IN EFI_USB2_HC_PROTOCOL * This,\r | |
203 | OUT UINT8 *MaxSpeed,\r | |
204 | OUT UINT8 *PortNumber,\r | |
205 | OUT UINT8 *Is64BitCapable\r | |
206 | );\r | |
207 | \r | |
208 | EFI_STATUS\r | |
209 | EFIAPI\r | |
210 | UHCI2Reset (\r | |
211 | IN EFI_USB2_HC_PROTOCOL * This,\r | |
212 | IN UINT16 Attributes\r | |
213 | );\r | |
214 | \r | |
215 | EFI_STATUS\r | |
216 | EFIAPI\r | |
217 | UHCI2GetState (\r | |
218 | IN EFI_USB2_HC_PROTOCOL * This,\r | |
219 | OUT EFI_USB_HC_STATE * State\r | |
220 | );\r | |
221 | \r | |
222 | EFI_STATUS\r | |
223 | EFIAPI\r | |
224 | UHCI2SetState (\r | |
225 | IN EFI_USB2_HC_PROTOCOL * This,\r | |
226 | IN EFI_USB_HC_STATE State\r | |
227 | );\r | |
228 | \r | |
229 | EFI_STATUS\r | |
230 | EFIAPI\r | |
231 | UHCI2ControlTransfer (\r | |
232 | IN EFI_USB2_HC_PROTOCOL * This,\r | |
233 | IN UINT8 DeviceAddress,\r | |
234 | IN UINT8 DeviceSpeed,\r | |
235 | IN UINTN MaximumPacketLength,\r | |
236 | IN EFI_USB_DEVICE_REQUEST * Request,\r | |
237 | IN EFI_USB_DATA_DIRECTION TransferDirection,\r | |
238 | IN OUT VOID *Data, OPTIONAL\r | |
239 | IN OUT UINTN *DataLength, OPTIONAL\r | |
240 | IN UINTN TimeOut,\r | |
241 | IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Translator,\r | |
242 | OUT UINT32 *TransferResult\r | |
243 | );\r | |
244 | \r | |
245 | EFI_STATUS\r | |
246 | EFIAPI\r | |
247 | UHCI2BulkTransfer (\r | |
248 | IN EFI_USB2_HC_PROTOCOL * This,\r | |
249 | IN UINT8 DeviceAddress,\r | |
250 | IN UINT8 EndPointAddress,\r | |
251 | IN UINT8 DeviceSpeed,\r | |
252 | IN UINTN MaximumPacketLength,\r | |
253 | IN UINT8 DataBuffersNumber,\r | |
254 | IN OUT VOID *Data[EFI_USB_MAX_BULK_BUFFER_NUM],\r | |
255 | IN OUT UINTN *DataLength,\r | |
256 | IN OUT UINT8 *DataToggle,\r | |
257 | IN UINTN TimeOut,\r | |
258 | IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Translator,\r | |
259 | OUT UINT32 *TransferResult\r | |
260 | );\r | |
261 | \r | |
262 | EFI_STATUS\r | |
263 | EFIAPI\r | |
264 | UHCI2AsyncInterruptTransfer (\r | |
265 | IN EFI_USB2_HC_PROTOCOL * This,\r | |
266 | IN UINT8 DeviceAddress,\r | |
267 | IN UINT8 EndPointAddress,\r | |
268 | IN UINT8 DeviceSpeed,\r | |
269 | IN UINTN MaximumPacketLength,\r | |
270 | IN BOOLEAN IsNewTransfer,\r | |
271 | IN OUT UINT8 *DataToggle,\r | |
272 | IN UINTN PollingInterval, OPTIONAL\r | |
273 | IN UINTN DataLength, OPTIONAL\r | |
274 | IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Translator,\r | |
275 | IN EFI_ASYNC_USB_TRANSFER_CALLBACK CallBackFunction, OPTIONAL\r | |
276 | IN VOID *Context OPTIONAL\r | |
277 | );\r | |
278 | \r | |
279 | EFI_STATUS\r | |
280 | EFIAPI\r | |
281 | UHCI2SyncInterruptTransfer (\r | |
282 | IN EFI_USB2_HC_PROTOCOL * This,\r | |
283 | IN UINT8 DeviceAddress,\r | |
284 | IN UINT8 EndPointAddress,\r | |
285 | IN UINT8 DeviceSpeed,\r | |
286 | IN UINTN MaximumPacketLength,\r | |
287 | IN OUT VOID *Data,\r | |
288 | IN OUT UINTN *DataLength,\r | |
289 | IN OUT UINT8 *DataToggle,\r | |
290 | IN UINTN TimeOut,\r | |
291 | IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Translator,\r | |
292 | OUT UINT32 *TransferResult\r | |
293 | );\r | |
294 | \r | |
295 | EFI_STATUS\r | |
296 | EFIAPI\r | |
297 | UHCI2IsochronousTransfer (\r | |
298 | IN EFI_USB2_HC_PROTOCOL * This,\r | |
299 | IN UINT8 DeviceAddress,\r | |
300 | IN UINT8 EndPointAddress,\r | |
301 | IN UINT8 DeviceSpeed,\r | |
302 | IN UINTN MaximumPacketLength,\r | |
303 | IN UINT8 DataBuffersNumber,\r | |
304 | IN OUT VOID *Data[EFI_USB_MAX_ISO_BUFFER_NUM],\r | |
305 | IN UINTN DataLength,\r | |
306 | IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Translator,\r | |
307 | OUT UINT32 *TransferResult\r | |
308 | );\r | |
309 | \r | |
310 | EFI_STATUS\r | |
311 | EFIAPI\r | |
312 | UHCI2AsyncIsochronousTransfer (\r | |
313 | IN EFI_USB2_HC_PROTOCOL * This,\r | |
314 | IN UINT8 DeviceAddress,\r | |
315 | IN UINT8 EndPointAddress,\r | |
316 | IN UINT8 DeviceSpeed,\r | |
317 | IN UINTN MaximumPacketLength,\r | |
318 | IN UINT8 DataBuffersNumber,\r | |
319 | IN OUT VOID *Data[EFI_USB_MAX_ISO_BUFFER_NUM],\r | |
320 | IN UINTN DataLength,\r | |
321 | IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Translator,\r | |
322 | IN EFI_ASYNC_USB_TRANSFER_CALLBACK IsochronousCallBack,\r | |
323 | IN VOID *Context OPTIONAL\r | |
324 | );\r | |
325 | \r | |
326 | EFI_STATUS\r | |
327 | EFIAPI\r | |
328 | UHCI2GetRootHubPortStatus (\r | |
329 | IN EFI_USB2_HC_PROTOCOL * This,\r | |
330 | IN UINT8 PortNumber,\r | |
331 | OUT EFI_USB_PORT_STATUS * PortStatus\r | |
332 | );\r | |
333 | \r | |
334 | EFI_STATUS\r | |
335 | EFIAPI\r | |
336 | UHCI2SetRootHubPortFeature (\r | |
337 | IN EFI_USB2_HC_PROTOCOL * This,\r | |
338 | IN UINT8 PortNumber,\r | |
339 | IN EFI_USB_PORT_FEATURE PortFeature\r | |
340 | );\r | |
341 | \r | |
342 | EFI_STATUS\r | |
343 | EFIAPI\r | |
344 | UHCI2ClearRootHubPortFeature (\r | |
345 | IN EFI_USB2_HC_PROTOCOL * This,\r | |
346 | IN UINT8 PortNumber,\r | |
347 | IN EFI_USB_PORT_FEATURE PortFeature\r | |
348 | );\r | |
349 | \r | |
878ddf1f | 350 | //\r |
351 | // Asynchronous interrupt transfer monitor function\r | |
352 | //\r | |
353 | VOID\r | |
354 | EFIAPI\r | |
355 | MonitorInterruptTrans (\r | |
356 | IN EFI_EVENT Event,\r | |
357 | IN VOID *Context\r | |
358 | );\r | |
359 | \r | |
360 | //\r | |
361 | // UHCI Driver Global Variables\r | |
362 | //\r | |
363 | EFI_DRIVER_BINDING_PROTOCOL gUhciDriverBinding = {\r | |
364 | UHCIDriverBindingSupported,\r | |
365 | UHCIDriverBindingStart,\r | |
366 | UHCIDriverBindingStop,\r | |
367 | 0x10,\r | |
368 | NULL,\r | |
369 | NULL\r | |
370 | };\r | |
371 | \r | |
372 | EFI_STATUS\r | |
373 | EFIAPI\r | |
374 | UHCIDriverBindingSupported (\r | |
375 | IN EFI_DRIVER_BINDING_PROTOCOL *This,\r | |
376 | IN EFI_HANDLE Controller,\r | |
377 | IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath\r | |
378 | )\r | |
379 | /*++\r | |
380 | \r | |
381 | Routine Description:\r | |
382 | Test to see if this driver supports ControllerHandle. Any ControllerHandle\r | |
383 | that has UsbHcProtocol installed will be supported.\r | |
384 | \r | |
385 | Arguments:\r | |
386 | This - Protocol instance pointer.\r | |
562d2849 | 387 | Controller - Handle of device to test\r |
878ddf1f | 388 | RemainingDevicePath - Not used\r |
389 | \r | |
390 | Returns:\r | |
391 | EFI_SUCCESS - This driver supports this device.\r | |
392 | EFI_UNSUPPORTED - This driver does not support this device.\r | |
393 | \r | |
394 | --*/\r | |
395 | {\r | |
396 | EFI_STATUS OpenStatus;\r | |
397 | EFI_STATUS Status;\r | |
398 | EFI_PCI_IO_PROTOCOL *PciIo;\r | |
399 | USB_CLASSC UsbClassCReg;\r | |
400 | \r | |
401 | //\r | |
402 | // Test whether there is PCI IO Protocol attached on the controller handle.\r | |
403 | //\r | |
404 | OpenStatus = gBS->OpenProtocol (\r | |
405 | Controller,\r | |
406 | &gEfiPciIoProtocolGuid,\r | |
407 | (VOID **) &PciIo,\r | |
408 | This->DriverBindingHandle,\r | |
409 | Controller,\r | |
410 | EFI_OPEN_PROTOCOL_BY_DRIVER\r | |
411 | );\r | |
412 | if (EFI_ERROR (OpenStatus)) {\r | |
413 | return OpenStatus;\r | |
414 | }\r | |
415 | \r | |
416 | Status = PciIo->Pci.Read (\r | |
417 | PciIo,\r | |
418 | EfiPciIoWidthUint8,\r | |
419 | CLASSC,\r | |
420 | sizeof (USB_CLASSC) / sizeof (UINT8),\r | |
421 | &UsbClassCReg\r | |
422 | );\r | |
423 | if (EFI_ERROR (Status)) {\r | |
424 | gBS->CloseProtocol (\r | |
425 | Controller,\r | |
426 | &gEfiPciIoProtocolGuid,\r | |
427 | This->DriverBindingHandle,\r | |
428 | Controller\r | |
429 | );\r | |
430 | return EFI_UNSUPPORTED;\r | |
431 | }\r | |
432 | //\r | |
433 | // Test whether the controller belongs to UHCI type\r | |
434 | //\r | |
435 | if ((UsbClassCReg.BaseCode != PCI_CLASS_SERIAL) ||\r | |
436 | (UsbClassCReg.SubClassCode != PCI_CLASS_SERIAL_USB) ||\r | |
437 | (UsbClassCReg.PI != PCI_CLASSC_PI_UHCI)) {\r | |
438 | \r | |
439 | gBS->CloseProtocol (\r | |
562d2849 | 440 | Controller,\r |
441 | &gEfiPciIoProtocolGuid,\r | |
442 | This->DriverBindingHandle,\r | |
443 | Controller\r | |
444 | );\r | |
878ddf1f | 445 | \r |
446 | return EFI_UNSUPPORTED;\r | |
447 | }\r | |
448 | gBS->CloseProtocol (\r | |
562d2849 | 449 | Controller,\r |
450 | &gEfiPciIoProtocolGuid,\r | |
451 | This->DriverBindingHandle,\r | |
452 | Controller\r | |
453 | );\r | |
878ddf1f | 454 | return EFI_SUCCESS;\r |
455 | \r | |
456 | }\r | |
457 | \r | |
458 | EFI_STATUS\r | |
459 | EFIAPI\r | |
460 | UHCIDriverBindingStart (\r | |
461 | IN EFI_DRIVER_BINDING_PROTOCOL *This,\r | |
462 | IN EFI_HANDLE Controller,\r | |
463 | IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath\r | |
464 | )\r | |
465 | /*++\r | |
466 | \r | |
467 | Routine Description:\r | |
468 | Starting the Usb UHCI Driver\r | |
469 | \r | |
470 | Arguments:\r | |
471 | This - Protocol instance pointer.\r | |
472 | Controller - Handle of device to test\r | |
473 | RemainingDevicePath - Not used\r | |
474 | \r | |
475 | Returns:\r | |
476 | EFI_SUCCESS - This driver supports this device.\r | |
477 | EFI_UNSUPPORTED - This driver does not support this device.\r | |
478 | EFI_DEVICE_ERROR - This driver cannot be started due to device\r | |
479 | Error\r | |
480 | EFI_OUT_OF_RESOURCES\r | |
481 | \r | |
482 | --*/\r | |
483 | { \r | |
484 | EFI_STATUS Status; \r | |
485 | UINTN FlBaseAddrReg; \r | |
486 | EFI_PCI_IO_PROTOCOL *PciIo; \r | |
487 | USB_HC_DEV *HcDev;\r | |
488 | \r | |
489 | HcDev = NULL;\r | |
490 | \r | |
491 | Status = gBS->OpenProtocol (\r | |
492 | Controller,\r | |
493 | &gEfiPciIoProtocolGuid,\r | |
494 | (VOID **) &PciIo,\r | |
495 | This->DriverBindingHandle,\r | |
496 | Controller,\r | |
497 | EFI_OPEN_PROTOCOL_BY_DRIVER\r | |
498 | );\r | |
499 | if (EFI_ERROR (Status)) {\r | |
500 | return Status;\r | |
501 | }\r | |
562d2849 | 502 | \r |
878ddf1f | 503 | //\r |
504 | // Turn off USB emulation\r | |
505 | //\r | |
506 | TurnOffUSBEmulation (PciIo);\r | |
507 | \r | |
508 | //\r | |
509 | // Enable the USB Host Controller\r | |
510 | //\r | |
511 | Status = PciIo->Attributes (\r | |
512 | PciIo,\r | |
513 | EfiPciIoAttributeOperationEnable,\r | |
514 | EFI_PCI_DEVICE_ENABLE,\r | |
515 | NULL\r | |
516 | );\r | |
517 | if (EFI_ERROR (Status)) {\r | |
518 | gBS->CloseProtocol (\r | |
562d2849 | 519 | Controller,\r |
520 | &gEfiPciIoProtocolGuid,\r | |
521 | This->DriverBindingHandle,\r | |
522 | Controller\r | |
523 | );\r | |
878ddf1f | 524 | return EFI_UNSUPPORTED;\r |
525 | }\r | |
526 | \r | |
527 | //\r | |
528 | // allocate memory for UHC private data structure\r | |
529 | //\r | |
530 | HcDev = AllocateZeroPool (sizeof (USB_HC_DEV));\r | |
531 | if (HcDev == NULL) {\r | |
532 | gBS->CloseProtocol (\r | |
562d2849 | 533 | Controller,\r |
534 | &gEfiPciIoProtocolGuid,\r | |
535 | This->DriverBindingHandle,\r | |
536 | Controller\r | |
537 | );\r | |
878ddf1f | 538 | return EFI_OUT_OF_RESOURCES;\r |
539 | }\r | |
562d2849 | 540 | \r |
878ddf1f | 541 | //\r |
542 | // init EFI_USB_HC_PROTOCOL protocol interface and install the protocol\r | |
543 | //\r | |
544 | HcDev->UsbHc.Reset = UHCIReset;\r | |
545 | HcDev->UsbHc.GetState = UHCIGetState;\r | |
546 | HcDev->UsbHc.SetState = UHCISetState;\r | |
547 | HcDev->UsbHc.ControlTransfer = UHCIControlTransfer;\r | |
548 | HcDev->UsbHc.BulkTransfer = UHCIBulkTransfer;\r | |
549 | HcDev->UsbHc.AsyncInterruptTransfer = UHCIAsyncInterruptTransfer;\r | |
550 | HcDev->UsbHc.SyncInterruptTransfer = UHCISyncInterruptTransfer;\r | |
551 | HcDev->UsbHc.IsochronousTransfer = UHCIIsochronousTransfer;\r | |
552 | HcDev->UsbHc.AsyncIsochronousTransfer = UHCIAsyncIsochronousTransfer;\r | |
553 | HcDev->UsbHc.GetRootHubPortNumber = UHCIGetRootHubPortNumber;\r | |
554 | HcDev->UsbHc.GetRootHubPortStatus = UHCIGetRootHubPortStatus;\r | |
555 | HcDev->UsbHc.SetRootHubPortFeature = UHCISetRootHubPortFeature;\r | |
556 | HcDev->UsbHc.ClearRootHubPortFeature = UHCIClearRootHubPortFeature;\r | |
557 | \r | |
558 | HcDev->UsbHc.MajorRevision = 0x1;\r | |
559 | HcDev->UsbHc.MinorRevision = 0x1;\r | |
560 | \r | |
562d2849 | 561 | //\r |
562 | //\r | |
563 | // init EFI_USB2_HC_PROTOCOL protocol interface and install the protocol\r | |
564 | //\r | |
565 | HcDev->Usb2Hc.GetCapability = UHCI2GetCapability;\r | |
566 | HcDev->Usb2Hc.Reset = UHCI2Reset;\r | |
567 | HcDev->Usb2Hc.GetState = UHCI2GetState;\r | |
568 | HcDev->Usb2Hc.SetState = UHCI2SetState;\r | |
569 | HcDev->Usb2Hc.ControlTransfer = UHCI2ControlTransfer;\r | |
570 | HcDev->Usb2Hc.BulkTransfer = UHCI2BulkTransfer;\r | |
571 | HcDev->Usb2Hc.AsyncInterruptTransfer = UHCI2AsyncInterruptTransfer;\r | |
572 | HcDev->Usb2Hc.SyncInterruptTransfer = UHCI2SyncInterruptTransfer;\r | |
573 | HcDev->Usb2Hc.IsochronousTransfer = UHCI2IsochronousTransfer;\r | |
574 | HcDev->Usb2Hc.AsyncIsochronousTransfer = UHCI2AsyncIsochronousTransfer;\r | |
575 | HcDev->Usb2Hc.GetRootHubPortStatus = UHCI2GetRootHubPortStatus;\r | |
576 | HcDev->Usb2Hc.SetRootHubPortFeature = UHCI2SetRootHubPortFeature;\r | |
577 | HcDev->Usb2Hc.ClearRootHubPortFeature = UHCI2ClearRootHubPortFeature;\r | |
578 | \r | |
579 | HcDev->Usb2Hc.MajorRevision = 0x1;\r | |
580 | HcDev->Usb2Hc.MinorRevision = 0x1;\r | |
581 | \r | |
878ddf1f | 582 | //\r |
583 | // Init UHCI private data structures\r | |
584 | //\r | |
585 | HcDev->Signature = USB_HC_DEV_SIGNATURE;\r | |
586 | HcDev->PciIo = PciIo;\r | |
587 | \r | |
588 | FlBaseAddrReg = USBFLBASEADD;\r | |
589 | \r | |
590 | //\r | |
591 | // Allocate and Init Host Controller's Frame List Entry\r | |
592 | //\r | |
593 | Status = CreateFrameList (HcDev, (UINT32) FlBaseAddrReg);\r | |
594 | if (EFI_ERROR (Status)) {\r | |
595 | \r | |
596 | if (HcDev != NULL) {\r | |
597 | gBS->FreePool (HcDev);\r | |
598 | }\r | |
599 | \r | |
600 | gBS->CloseProtocol (\r | |
562d2849 | 601 | Controller,\r |
602 | &gEfiPciIoProtocolGuid,\r | |
603 | This->DriverBindingHandle,\r | |
604 | Controller\r | |
605 | );\r | |
878ddf1f | 606 | return EFI_OUT_OF_RESOURCES;\r |
607 | }\r | |
562d2849 | 608 | \r |
878ddf1f | 609 | //\r |
610 | // Init interrupt list head in the HcDev structure.\r | |
611 | //\r | |
612 | InitializeListHead (&(HcDev->InterruptListHead));\r | |
613 | \r | |
614 | //\r | |
615 | // Create timer for interrupt transfer result polling\r | |
616 | //\r | |
617 | Status = gBS->CreateEvent (\r | |
618 | EFI_EVENT_TIMER | EFI_EVENT_NOTIFY_SIGNAL,\r | |
619 | EFI_TPL_NOTIFY,\r | |
620 | MonitorInterruptTrans,\r | |
621 | HcDev,\r | |
622 | &HcDev->InterruptTransTimer\r | |
623 | );\r | |
624 | if (EFI_ERROR (Status)) {\r | |
625 | \r | |
626 | FreeFrameListEntry (HcDev);\r | |
627 | \r | |
628 | if (HcDev != NULL) {\r | |
629 | gBS->FreePool (HcDev);\r | |
630 | }\r | |
631 | \r | |
632 | gBS->CloseProtocol (\r | |
562d2849 | 633 | Controller,\r |
634 | &gEfiPciIoProtocolGuid,\r | |
635 | This->DriverBindingHandle,\r | |
636 | Controller\r | |
637 | );\r | |
878ddf1f | 638 | return EFI_UNSUPPORTED;\r |
639 | }\r | |
640 | \r | |
641 | //\r | |
642 | // Here set interrupt transfer polling timer in 50ms unit.\r | |
643 | //\r | |
644 | Status = gBS->SetTimer (\r | |
645 | HcDev->InterruptTransTimer,\r | |
646 | TimerPeriodic,\r | |
647 | INTERRUPT_POLLING_TIME\r | |
648 | );\r | |
649 | if (EFI_ERROR (Status)) {\r | |
650 | gBS->CloseEvent (HcDev->InterruptTransTimer);\r | |
651 | \r | |
652 | FreeFrameListEntry (HcDev);\r | |
653 | \r | |
654 | if (HcDev != NULL) {\r | |
655 | gBS->FreePool (HcDev);\r | |
656 | }\r | |
657 | \r | |
658 | gBS->CloseProtocol (\r | |
562d2849 | 659 | Controller,\r |
660 | &gEfiPciIoProtocolGuid,\r | |
661 | This->DriverBindingHandle,\r | |
662 | Controller\r | |
663 | );\r | |
878ddf1f | 664 | return EFI_UNSUPPORTED;\r |
665 | }\r | |
666 | \r | |
667 | //\r | |
668 | // QH,TD structures must in common buffer that will be\r | |
669 | // accessed by both cpu and usb bus master at the same time.\r | |
670 | // so, there must has memory management for QH,TD structures.\r | |
671 | //\r | |
672 | Status = InitializeMemoryManagement (HcDev);\r | |
673 | if (EFI_ERROR (Status)) {\r | |
674 | \r | |
675 | gBS->CloseEvent (HcDev->InterruptTransTimer);\r | |
676 | \r | |
677 | FreeFrameListEntry (HcDev);\r | |
678 | \r | |
679 | if (HcDev != NULL) {\r | |
680 | gBS->FreePool (HcDev);\r | |
681 | }\r | |
682 | \r | |
683 | gBS->CloseProtocol (\r | |
684 | Controller, \r | |
685 | &gEfiPciIoProtocolGuid, \r | |
686 | This->DriverBindingHandle, \r | |
687 | Controller\r | |
688 | );\r | |
689 | return Status;\r | |
690 | }\r | |
562d2849 | 691 | \r |
878ddf1f | 692 | //\r |
693 | // Install Host Controller Protocol\r | |
694 | //\r | |
695 | Status = gBS->InstallProtocolInterface (\r | |
696 | &Controller,\r | |
697 | &gEfiUsbHcProtocolGuid,\r | |
698 | EFI_NATIVE_INTERFACE,\r | |
699 | &HcDev->UsbHc\r | |
700 | );\r | |
701 | if (EFI_ERROR (Status)) {\r | |
702 | gBS->CloseEvent (HcDev->InterruptTransTimer);\r | |
703 | FreeFrameListEntry (HcDev);\r | |
704 | DelMemoryManagement (HcDev);\r | |
705 | \r | |
706 | if (HcDev != NULL) {\r | |
707 | gBS->FreePool (HcDev);\r | |
708 | }\r | |
709 | \r | |
710 | gBS->CloseProtocol (\r | |
562d2849 | 711 | Controller,\r |
712 | &gEfiPciIoProtocolGuid,\r | |
713 | This->DriverBindingHandle,\r | |
714 | Controller\r | |
715 | );\r | |
716 | return Status;\r | |
717 | }\r | |
718 | \r | |
719 | //\r | |
720 | // Install USB2.0 Host Controller Protocol\r | |
721 | //\r | |
722 | Status = gBS->InstallProtocolInterface (\r | |
723 | &Controller,\r | |
724 | &gEfiUsb2HcProtocolGuid,\r | |
725 | EFI_NATIVE_INTERFACE,\r | |
726 | &HcDev->Usb2Hc\r | |
727 | );\r | |
728 | if (EFI_ERROR (Status)) {\r | |
729 | gBS->CloseEvent (HcDev->InterruptTransTimer);\r | |
730 | FreeFrameListEntry (HcDev);\r | |
731 | DelMemoryManagement (HcDev);\r | |
732 | \r | |
733 | if (HcDev != NULL) {\r | |
734 | gBS->FreePool (HcDev);\r | |
735 | }\r | |
736 | \r | |
737 | gBS->CloseProtocol (\r | |
738 | Controller,\r | |
739 | &gEfiPciIoProtocolGuid,\r | |
740 | This->DriverBindingHandle,\r | |
741 | Controller\r | |
742 | );\r | |
743 | \r | |
878ddf1f | 744 | return Status;\r |
745 | }\r | |
746 | \r | |
747 | //\r | |
748 | // component name protocol.\r | |
749 | //\r | |
562d2849 | 750 | \r |
878ddf1f | 751 | HcDev->ControllerNameTable = NULL;\r |
752 | AddUnicodeString (\r | |
753 | "eng",\r | |
754 | gUhciComponentName.SupportedLanguages,\r | |
755 | &HcDev->ControllerNameTable,\r | |
756 | (CHAR16 *) L"Usb Universal Host Controller"\r | |
757 | );\r | |
758 | \r | |
759 | return EFI_SUCCESS;\r | |
760 | }\r | |
761 | \r | |
762 | \r | |
763 | EFI_STATUS\r | |
764 | UnInstallUHCInterface (\r | |
765 | IN EFI_HANDLE Controller,\r | |
766 | IN EFI_USB_HC_PROTOCOL *This\r | |
767 | )\r | |
768 | /*++\r | |
769 | Routine Description:\r | |
770 | UnInstall UHCInterface\r | |
771 | Arguments:\r | |
772 | Controller - Controller handle\r | |
773 | This - Protocol instance pointer.\r | |
774 | Returns:\r | |
775 | EFI_SUCCESS\r | |
776 | others\r | |
777 | --*/\r | |
778 | {\r | |
779 | USB_HC_DEV *HcDev;\r | |
780 | \r | |
781 | HcDev = USB_HC_DEV_FROM_THIS (This);\r | |
782 | \r | |
783 | gBS->UninstallProtocolInterface (\r | |
562d2849 | 784 | Controller,\r |
785 | &gEfiUsbHcProtocolGuid,\r | |
786 | &HcDev->UsbHc\r | |
787 | );\r | |
788 | \r | |
789 | gBS->UninstallProtocolInterface (\r | |
790 | Controller,\r | |
791 | &gEfiUsb2HcProtocolGuid,\r | |
792 | &HcDev->Usb2Hc\r | |
793 | );\r | |
794 | // \r | |
878ddf1f | 795 | // first stop USB Host Controller\r |
796 | //\r | |
797 | This->SetState (This, EfiUsbHcStateHalt);\r | |
798 | \r | |
799 | //\r | |
800 | // Delete interrupt transfer polling timer\r | |
801 | //\r | |
802 | gBS->CloseEvent (HcDev->InterruptTransTimer);\r | |
803 | \r | |
804 | //\r | |
805 | // Delete all the asynchronous interrupt transfers in the interrupt list\r | |
806 | // and free associated memory\r | |
807 | //\r | |
808 | ReleaseInterruptList (HcDev, &(HcDev->InterruptListHead));\r | |
809 | \r | |
810 | //\r | |
811 | // free Frame List Entry.\r | |
812 | //\r | |
813 | FreeFrameListEntry (HcDev);\r | |
814 | \r | |
815 | //\r | |
816 | // Free common buffer allocated for QH,TD structures\r | |
817 | //\r | |
818 | DelMemoryManagement (HcDev);\r | |
819 | \r | |
820 | if (HcDev->ControllerNameTable) {\r | |
821 | FreeUnicodeStringTable (HcDev->ControllerNameTable);\r | |
822 | }\r | |
823 | //\r | |
824 | // Disable the USB Host Controller\r | |
825 | //\r | |
826 | HcDev->PciIo->Attributes (\r | |
827 | HcDev->PciIo,\r | |
828 | EfiPciIoAttributeOperationDisable,\r | |
829 | EFI_PCI_DEVICE_ENABLE,\r | |
830 | NULL\r | |
831 | );\r | |
832 | \r | |
833 | gBS->FreePool (HcDev);\r | |
834 | \r | |
835 | return EFI_SUCCESS;\r | |
836 | }\r | |
837 | \r | |
838 | \r | |
839 | EFI_STATUS\r | |
840 | EFIAPI\r | |
841 | UHCIDriverBindingStop (\r | |
842 | IN EFI_DRIVER_BINDING_PROTOCOL *This,\r | |
843 | IN EFI_HANDLE Controller,\r | |
844 | IN UINTN NumberOfChildren,\r | |
845 | IN EFI_HANDLE *ChildHandleBuffer\r | |
846 | )\r | |
847 | /*++\r | |
848 | \r | |
849 | Routine Description:\r | |
850 | Stop this driver on ControllerHandle. Support stoping any child handles\r | |
851 | created by this driver.\r | |
852 | \r | |
853 | Arguments:\r | |
854 | This - Protocol instance pointer.\r | |
855 | Controller - Handle of device to stop driver on\r | |
856 | NumberOfChildren - Number of Children in the ChildHandleBuffer\r | |
857 | ChildHandleBuffer - List of handles for the children we need to stop.\r | |
858 | \r | |
859 | Returns:\r | |
860 | EFI_SUCCESS\r | |
861 | others\r | |
862 | \r | |
863 | --*/\r | |
864 | {\r | |
865 | EFI_USB_HC_PROTOCOL *UsbHc;\r | |
562d2849 | 866 | EFI_USB2_HC_PROTOCOL *Usb2Hc;\r |
878ddf1f | 867 | EFI_STATUS OpenStatus;\r |
868 | \r | |
869 | OpenStatus = gBS->OpenProtocol (\r | |
870 | Controller,\r | |
871 | &gEfiUsbHcProtocolGuid,\r | |
562d2849 | 872 | (VOID **)&UsbHc,\r |
873 | This->DriverBindingHandle,\r | |
874 | Controller,\r | |
875 | EFI_OPEN_PROTOCOL_GET_PROTOCOL\r | |
876 | );\r | |
877 | \r | |
878 | //\r | |
879 | // Test whether the Controller handler passed in is a valid\r | |
880 | // Usb controller handle that should be supported, if not,\r | |
881 | // return the error status directly\r | |
882 | //\r | |
883 | if (EFI_ERROR (OpenStatus)) {\r | |
884 | return OpenStatus;\r | |
885 | }\r | |
886 | \r | |
887 | OpenStatus = gBS->OpenProtocol (\r | |
888 | Controller,\r | |
889 | &gEfiUsb2HcProtocolGuid,\r | |
890 | (VOID **) &Usb2Hc,\r | |
878ddf1f | 891 | This->DriverBindingHandle,\r |
892 | Controller,\r | |
893 | EFI_OPEN_PROTOCOL_GET_PROTOCOL\r | |
894 | );\r | |
895 | \r | |
896 | //\r | |
897 | // Test whether the Controller handler passed in is a valid\r | |
898 | // Usb controller handle that should be supported, if not,\r | |
899 | // return the error status directly\r | |
900 | //\r | |
901 | if (EFI_ERROR (OpenStatus)) {\r | |
902 | return OpenStatus;\r | |
903 | }\r | |
904 | //\r | |
905 | // free all the controller related memory and uninstall UHCI Protocol.\r | |
906 | //\r | |
907 | UnInstallUHCInterface (Controller, UsbHc);\r | |
908 | \r | |
909 | gBS->CloseProtocol (\r | |
562d2849 | 910 | Controller,\r |
911 | &gEfiPciIoProtocolGuid,\r | |
912 | This->DriverBindingHandle,\r | |
913 | Controller\r | |
914 | );\r | |
878ddf1f | 915 | \r |
916 | return EFI_SUCCESS;\r | |
917 | \r | |
918 | }\r | |
919 | \r | |
920 | \r | |
921 | EFI_STATUS\r | |
922 | EFIAPI\r | |
923 | UHCIReset (\r | |
924 | IN EFI_USB_HC_PROTOCOL *This,\r | |
925 | IN UINT16 Attributes\r | |
926 | )\r | |
927 | /*++\r | |
928 | \r | |
929 | Routine Description:\r | |
930 | Provides software reset for the USB host controller.\r | |
931 | \r | |
932 | Arguments:\r | |
933 | \r | |
934 | This A pointer to the EFI_USB_HC_PROTOCOL instance. \r | |
935 | \r | |
936 | Attributes A bit mask of the reset operation to perform. \r | |
937 | See below for a list of the supported bit mask values.\r | |
938 | \r | |
939 | #define EFI_USB_HC_RESET_GLOBAL 0x0001\r | |
940 | #define EFI_USB_HC_RESET_HOST_CONTROLLER 0x0002\r | |
941 | \r | |
942 | EFI_USB_HC_RESET_GLOBAL \r | |
943 | If this bit is set, a global reset signal will be sent to the USB bus.\r | |
944 | This resets all of the USB bus logic, including the USB host \r | |
945 | controller hardware and all the devices attached on the USB bus.\r | |
946 | EFI_USB_HC_RESET_HOST_CONTROLLER \r | |
947 | If this bit is set, the USB host controller hardware will be reset. \r | |
948 | No reset signal will be sent to the USB bus.\r | |
949 | \r | |
950 | Returns:\r | |
951 | EFI_SUCCESS \r | |
952 | The reset operation succeeded.\r | |
953 | EFI_INVALID_PARAMETER \r | |
954 | Attributes is not valid.\r | |
955 | EFI_DEVICE_ERROR \r | |
956 | An error was encountered while attempting to perform \r | |
957 | the reset operation.\r | |
958 | --*/\r | |
959 | {\r | |
960 | BOOLEAN Match;\r | |
961 | USB_HC_DEV *HcDev;\r | |
962 | UINT32 CommandRegAddr;\r | |
963 | UINT32 FlBaseAddrReg;\r | |
964 | UINT16 Command;\r | |
965 | EFI_STATUS Status;\r | |
966 | \r | |
967 | Match = FALSE;\r | |
968 | HcDev = USB_HC_DEV_FROM_THIS (This);\r | |
969 | \r | |
970 | CommandRegAddr = (UINT32) (USBCMD);\r | |
971 | FlBaseAddrReg = (UINT32) (USBFLBASEADD);\r | |
972 | \r | |
973 | if ((Attributes & EFI_USB_HC_RESET_GLOBAL) != 0) {\r | |
974 | Match = TRUE;\r | |
975 | //\r | |
976 | // set the Global Reset bit in the command register\r | |
977 | //\r | |
978 | Status = ReadUHCCommandReg (\r | |
562d2849 | 979 | HcDev->PciIo,\r |
980 | CommandRegAddr,\r | |
981 | &Command\r | |
982 | );\r | |
878ddf1f | 983 | if (EFI_ERROR (Status)) {\r |
984 | return EFI_DEVICE_ERROR;\r | |
985 | }\r | |
986 | \r | |
987 | Command |= USBCMD_GRESET;\r | |
988 | Status = WriteUHCCommandReg (\r | |
562d2849 | 989 | HcDev->PciIo,\r |
990 | CommandRegAddr,\r | |
991 | Command\r | |
992 | );\r | |
878ddf1f | 993 | if (EFI_ERROR (Status)) {\r |
994 | return EFI_DEVICE_ERROR;\r | |
995 | }\r | |
996 | \r | |
997 | //\r | |
998 | // Wait 50ms for root port to let reset complete\r | |
999 | // See UHCI spec page122 Reset signaling\r | |
1000 | //\r | |
1001 | gBS->Stall (ROOT_PORT_REST_TIME);\r | |
1002 | \r | |
1003 | //\r | |
1004 | // Clear the Global Reset bit to zero.\r | |
1005 | //\r | |
1006 | Command &= ~USBCMD_GRESET;\r | |
1007 | Status = WriteUHCCommandReg (\r | |
562d2849 | 1008 | HcDev->PciIo,\r |
1009 | CommandRegAddr,\r | |
1010 | Command\r | |
1011 | );\r | |
878ddf1f | 1012 | if (EFI_ERROR (Status)) {\r |
1013 | return EFI_DEVICE_ERROR;\r | |
1014 | }\r | |
1015 | //\r | |
1016 | // UHCI spec page120 reset recovery time\r | |
1017 | //\r | |
1018 | gBS->Stall (PORT_RESET_RECOVERY_TIME);\r | |
1019 | }\r | |
1020 | \r | |
1021 | if ((Attributes & EFI_USB_HC_RESET_HOST_CONTROLLER) != 0) {\r | |
1022 | Match = TRUE;\r | |
1023 | //\r | |
1024 | // set Host Controller Reset bit to 1\r | |
1025 | //\r | |
1026 | Status = ReadUHCCommandReg (\r | |
562d2849 | 1027 | HcDev->PciIo,\r |
1028 | CommandRegAddr,\r | |
1029 | &Command\r | |
1030 | );\r | |
878ddf1f | 1031 | if (EFI_ERROR (Status)) {\r |
1032 | return EFI_DEVICE_ERROR;\r | |
1033 | }\r | |
1034 | \r | |
1035 | Command |= USBCMD_HCRESET;\r | |
1036 | Status = WriteUHCCommandReg (\r | |
562d2849 | 1037 | HcDev->PciIo,\r |
1038 | CommandRegAddr,\r | |
1039 | Command\r | |
1040 | );\r | |
878ddf1f | 1041 | if (EFI_ERROR (Status)) {\r |
1042 | return EFI_DEVICE_ERROR;\r | |
1043 | }\r | |
1044 | //\r | |
1045 | // this bit will be reset by Host Controller when reset is completed.\r | |
1046 | // wait 10ms to let reset complete\r | |
1047 | //\r | |
1048 | gBS->Stall (PORT_RESET_RECOVERY_TIME);\r | |
1049 | }\r | |
1050 | \r | |
1051 | if (!Match) {\r | |
1052 | return EFI_INVALID_PARAMETER;\r | |
1053 | }\r | |
1054 | \r | |
1055 | //\r | |
1056 | // Delete all old transactions on the USB bus\r | |
1057 | //\r | |
1058 | CleanUsbTransactions (HcDev);\r | |
1059 | \r | |
1060 | //\r | |
1061 | // Initialize Universal Host Controller's Frame List Data Structure\r | |
1062 | //\r | |
1063 | InitFrameList (HcDev);\r | |
1064 | \r | |
1065 | //\r | |
1066 | // Reset may cause Frame List Base Address Register reset to zero,\r | |
1067 | // so set the original value back again.\r | |
1068 | //\r | |
1069 | SetFrameListBaseAddress (\r | |
1070 | HcDev->PciIo,\r | |
1071 | FlBaseAddrReg,\r | |
1072 | (UINT32) ((UINTN) HcDev->FrameListEntry)\r | |
1073 | );\r | |
1074 | \r | |
1075 | return EFI_SUCCESS;\r | |
1076 | }\r | |
1077 | \r | |
1078 | EFI_STATUS\r | |
1079 | EFIAPI\r | |
1080 | UHCIGetState (\r | |
1081 | IN EFI_USB_HC_PROTOCOL *This,\r | |
1082 | OUT EFI_USB_HC_STATE *State\r | |
1083 | )\r | |
1084 | /*++\r | |
1085 | \r | |
1086 | Routine Description:\r | |
1087 | Retrieves current state of the USB host controller.\r | |
1088 | \r | |
1089 | Arguments:\r | |
1090 | \r | |
1091 | This A pointer to the EFI_USB_HC_PROTOCOL instance.\r | |
1092 | \r | |
1093 | State A pointer to the EFI_USB_HC_STATE data structure that \r | |
1094 | indicates current state of the USB host controller. \r | |
1095 | Type EFI_USB_HC_STATE is defined below.\r | |
1096 | \r | |
1097 | typedef enum {\r | |
1098 | EfiUsbHcStateHalt,\r | |
1099 | EfiUsbHcStateOperational,\r | |
1100 | EfiUsbHcStateSuspend,\r | |
1101 | EfiUsbHcStateMaximum\r | |
1102 | } EFI_USB_HC_STATE;\r | |
1103 | \r | |
1104 | Returns:\r | |
1105 | EFI_SUCCESS \r | |
1106 | The state information of the host controller was returned in State.\r | |
1107 | EFI_INVALID_PARAMETER \r | |
1108 | State is NULL.\r | |
1109 | EFI_DEVICE_ERROR \r | |
1110 | An error was encountered while attempting to retrieve the \r | |
1111 | host controller's current state. \r | |
1112 | --*/\r | |
1113 | {\r | |
1114 | USB_HC_DEV *HcDev;\r | |
1115 | UINT32 CommandRegAddr;\r | |
1116 | UINT32 StatusRegAddr;\r | |
1117 | UINT16 UhcCommand;\r | |
1118 | UINT16 UhcStatus;\r | |
1119 | EFI_STATUS Status;\r | |
1120 | \r | |
1121 | if (State == NULL) {\r | |
1122 | return EFI_INVALID_PARAMETER;\r | |
1123 | }\r | |
1124 | \r | |
1125 | HcDev = USB_HC_DEV_FROM_THIS (This);\r | |
1126 | \r | |
1127 | CommandRegAddr = (UINT32) (USBCMD);\r | |
1128 | StatusRegAddr = (UINT32) (USBSTS);\r | |
1129 | \r | |
1130 | Status = ReadUHCCommandReg (\r | |
562d2849 | 1131 | HcDev->PciIo,\r |
1132 | CommandRegAddr,\r | |
1133 | &UhcCommand\r | |
1134 | );\r | |
878ddf1f | 1135 | \r |
1136 | if (EFI_ERROR (Status)) {\r | |
1137 | return EFI_DEVICE_ERROR;\r | |
1138 | }\r | |
1139 | \r | |
1140 | Status = ReadUHCCommandReg (\r | |
562d2849 | 1141 | HcDev->PciIo,\r |
1142 | StatusRegAddr,\r | |
1143 | &UhcStatus\r | |
1144 | );\r | |
878ddf1f | 1145 | if (EFI_ERROR (Status)) {\r |
1146 | return EFI_DEVICE_ERROR;\r | |
1147 | }\r | |
1148 | \r | |
1149 | if (UhcCommand & USBCMD_EGSM) {\r | |
1150 | *State = EfiUsbHcStateSuspend;\r | |
1151 | return EFI_SUCCESS;\r | |
1152 | }\r | |
1153 | \r | |
1154 | if ((UhcStatus & USBSTS_HCH) == 0) {\r | |
1155 | *State = EfiUsbHcStateOperational;\r | |
1156 | } else {\r | |
1157 | *State = EfiUsbHcStateHalt;\r | |
1158 | }\r | |
1159 | \r | |
1160 | return EFI_SUCCESS;\r | |
1161 | }\r | |
1162 | \r | |
1163 | \r | |
1164 | EFI_STATUS\r | |
1165 | EFIAPI\r | |
1166 | UHCISetState (\r | |
1167 | IN EFI_USB_HC_PROTOCOL *This,\r | |
1168 | IN EFI_USB_HC_STATE State\r | |
1169 | )\r | |
1170 | /*++\r | |
1171 | \r | |
1172 | Routine Description:\r | |
1173 | Sets the USB host controller to a specific state.\r | |
1174 | \r | |
1175 | Arguments:\r | |
1176 | \r | |
1177 | This A pointer to the EFI_USB_HC_PROTOCOL instance.\r | |
1178 | \r | |
1179 | State Indicates the state of the host controller that will be set.\r | |
1180 | \r | |
1181 | Returns:\r | |
1182 | EFI_SUCCESS \r | |
1183 | The USB host controller was successfully placed in the state \r | |
1184 | specified by State.\r | |
1185 | EFI_INVALID_PARAMETER \r | |
1186 | State is invalid.\r | |
1187 | EFI_DEVICE_ERROR \r | |
1188 | Failed to set the state specified by State due to device error. \r | |
1189 | --*/\r | |
1190 | {\r | |
1191 | USB_HC_DEV *HcDev;\r | |
1192 | UINT32 CommandRegAddr;\r | |
1193 | UINT32 StatusRegAddr;\r | |
1194 | UINT16 Command;\r | |
1195 | EFI_USB_HC_STATE CurrentState;\r | |
1196 | EFI_STATUS Status;\r | |
1197 | \r | |
1198 | HcDev = USB_HC_DEV_FROM_THIS (This);\r | |
1199 | \r | |
1200 | CommandRegAddr = (UINT32) (USBCMD);\r | |
1201 | StatusRegAddr = (UINT32) (USBSTS);\r | |
1202 | \r | |
1203 | Status = UHCIGetState (This, &CurrentState);\r | |
1204 | if (EFI_ERROR (Status)) {\r | |
1205 | return EFI_DEVICE_ERROR;\r | |
1206 | }\r | |
1207 | \r | |
1208 | switch (State) {\r | |
1209 | \r | |
1210 | case EfiUsbHcStateHalt:\r | |
1211 | if (CurrentState == EfiUsbHcStateHalt) {\r | |
1212 | return EFI_SUCCESS;\r | |
1213 | }\r | |
1214 | \r | |
1215 | Status = ReadUHCCommandReg (\r | |
562d2849 | 1216 | HcDev->PciIo,\r |
1217 | CommandRegAddr,\r | |
1218 | &Command\r | |
1219 | );\r | |
878ddf1f | 1220 | if (EFI_ERROR (Status)) {\r |
1221 | return EFI_DEVICE_ERROR;\r | |
1222 | }\r | |
1223 | \r | |
1224 | Command &= ~USBCMD_RS;\r | |
1225 | \r | |
1226 | Status = WriteUHCCommandReg (\r | |
562d2849 | 1227 | HcDev->PciIo,\r |
1228 | CommandRegAddr,\r | |
1229 | Command\r | |
1230 | );\r | |
878ddf1f | 1231 | if (EFI_ERROR (Status)) {\r |
1232 | return EFI_DEVICE_ERROR;\r | |
1233 | }\r | |
1234 | \r | |
1235 | StatusRegAddr = (UINT32) (USBSTS);\r | |
1236 | //\r | |
1237 | // ensure the HC is in halt status after send the stop command\r | |
1238 | //\r | |
1239 | if (WaitForUHCHalt (HcDev->PciIo, StatusRegAddr, STALL_1_SECOND) == EFI_TIMEOUT) {\r | |
1240 | return EFI_DEVICE_ERROR;\r | |
1241 | }\r | |
1242 | break;\r | |
1243 | \r | |
1244 | case EfiUsbHcStateOperational:\r | |
1245 | if (IsHostSysOrProcessErr (HcDev->PciIo, StatusRegAddr)) {\r | |
1246 | return EFI_DEVICE_ERROR;\r | |
1247 | }\r | |
1248 | \r | |
1249 | switch (CurrentState) {\r | |
1250 | \r | |
1251 | case EfiUsbHcStateOperational:\r | |
1252 | return EFI_SUCCESS;\r | |
1253 | \r | |
1254 | case EfiUsbHcStateHalt:\r | |
1255 | //\r | |
1256 | // Set Run/Stop bit to 1.\r | |
1257 | //\r | |
1258 | Status = ReadUHCCommandReg (\r | |
562d2849 | 1259 | HcDev->PciIo,\r |
1260 | CommandRegAddr,\r | |
1261 | &Command\r | |
1262 | );\r | |
878ddf1f | 1263 | if (EFI_ERROR (Status)) {\r |
1264 | return EFI_DEVICE_ERROR;\r | |
1265 | }\r | |
1266 | \r | |
1267 | Command |= USBCMD_RS | USBCMD_MAXP;\r | |
1268 | Status = WriteUHCCommandReg (\r | |
562d2849 | 1269 | HcDev->PciIo,\r |
1270 | CommandRegAddr,\r | |
1271 | Command\r | |
1272 | );\r | |
878ddf1f | 1273 | if (EFI_ERROR (Status)) {\r |
1274 | return EFI_DEVICE_ERROR;\r | |
1275 | }\r | |
1276 | \r | |
1277 | break;\r | |
1278 | \r | |
1279 | case EfiUsbHcStateSuspend:\r | |
1280 | Status = ReadUHCCommandReg (\r | |
562d2849 | 1281 | HcDev->PciIo,\r |
1282 | CommandRegAddr,\r | |
1283 | &Command\r | |
1284 | );\r | |
878ddf1f | 1285 | if (EFI_ERROR (Status)) {\r |
1286 | return EFI_DEVICE_ERROR;\r | |
1287 | }\r | |
1288 | \r | |
1289 | //\r | |
1290 | // FGR(Force Global Resume) bit is 0\r | |
1291 | //\r | |
1292 | if ((Command | (~USBCMD_FGR)) != 0xFF) {\r | |
1293 | //\r | |
1294 | // Write FGR bit to 1\r | |
1295 | //\r | |
1296 | Command |= USBCMD_FGR;\r | |
1297 | WriteUHCCommandReg (\r | |
1298 | HcDev->PciIo,\r | |
1299 | CommandRegAddr,\r | |
1300 | Command\r | |
1301 | );\r | |
1302 | }\r | |
1303 | \r | |
1304 | //\r | |
1305 | // wait 20ms to let resume complete\r | |
1306 | // (20ms is specified by UHCI spec)\r | |
1307 | //\r | |
1308 | gBS->Stall (FORCE_GLOBAL_RESUME_TIME);\r | |
1309 | \r | |
1310 | //\r | |
1311 | // Write FGR bit to 0 and EGSM(Enter Global Suspend Mode) bit to 0\r | |
1312 | //\r | |
1313 | Command &= ~USBCMD_FGR;\r | |
1314 | Command &= ~USBCMD_EGSM;\r | |
1315 | Command |= USBCMD_RS;\r | |
1316 | WriteUHCCommandReg (\r | |
1317 | HcDev->PciIo,\r | |
1318 | CommandRegAddr,\r | |
1319 | Command\r | |
1320 | );\r | |
1321 | break;\r | |
1322 | \r | |
1323 | default:\r | |
1324 | break;\r | |
1325 | }\r | |
1326 | break;\r | |
1327 | \r | |
1328 | case EfiUsbHcStateSuspend:\r | |
1329 | if (CurrentState == EfiUsbHcStateSuspend) {\r | |
1330 | return EFI_SUCCESS;\r | |
1331 | }\r | |
1332 | \r | |
1333 | Status = UHCISetState (This, EfiUsbHcStateHalt);\r | |
1334 | if (EFI_ERROR (Status)) {\r | |
1335 | return EFI_DEVICE_ERROR;\r | |
1336 | }\r | |
1337 | //\r | |
1338 | // Set Enter Global Suspend Mode bit to 1.\r | |
1339 | //\r | |
1340 | Status = ReadUHCCommandReg (\r | |
562d2849 | 1341 | HcDev->PciIo,\r |
1342 | CommandRegAddr,\r | |
1343 | &Command\r | |
1344 | );\r | |
878ddf1f | 1345 | if (EFI_ERROR (Status)) {\r |
1346 | return EFI_DEVICE_ERROR;\r | |
1347 | }\r | |
1348 | \r | |
1349 | Command |= USBCMD_EGSM;\r | |
1350 | Status = WriteUHCCommandReg (\r | |
562d2849 | 1351 | HcDev->PciIo,\r |
1352 | CommandRegAddr,\r | |
1353 | Command\r | |
1354 | );\r | |
878ddf1f | 1355 | if (EFI_ERROR (Status)) {\r |
1356 | return EFI_DEVICE_ERROR;\r | |
1357 | }\r | |
1358 | break;\r | |
1359 | \r | |
1360 | default:\r | |
1361 | return EFI_INVALID_PARAMETER;\r | |
1362 | }\r | |
1363 | \r | |
1364 | return EFI_SUCCESS;\r | |
1365 | }\r | |
1366 | \r | |
1367 | EFI_STATUS\r | |
1368 | EFIAPI\r | |
1369 | UHCIGetRootHubPortNumber (\r | |
1370 | IN EFI_USB_HC_PROTOCOL *This,\r | |
1371 | OUT UINT8 *PortNumber\r | |
1372 | )\r | |
1373 | /*++\r | |
1374 | \r | |
1375 | Routine Description:\r | |
1376 | Retrieves the number of root hub ports.\r | |
1377 | \r | |
1378 | Arguments:\r | |
1379 | \r | |
1380 | This A pointer to the EFI_USB_HC_PROTOCOL instance.\r | |
1381 | \r | |
1382 | PortNumber A pointer to the number of the root hub ports.\r | |
1383 | \r | |
1384 | Returns:\r | |
1385 | EFI_SUCCESS \r | |
1386 | The port number was retrieved successfully.\r | |
1387 | EFI_INVALID_PARAMETER \r | |
1388 | PortNumber is NULL.\r | |
1389 | EFI_DEVICE_ERROR \r | |
1390 | An error was encountered while attempting to \r | |
1391 | retrieve the port number. \r | |
1392 | --*/\r | |
1393 | {\r | |
1394 | USB_HC_DEV *HcDev;\r | |
1395 | UINT32 PSAddr;\r | |
1396 | UINT16 RHPortControl;\r | |
1397 | UINT32 Index;\r | |
1398 | EFI_STATUS Status;\r | |
1399 | \r | |
1400 | HcDev = USB_HC_DEV_FROM_THIS (This);\r | |
1401 | \r | |
1402 | if (PortNumber == NULL) {\r | |
1403 | return EFI_INVALID_PARAMETER;\r | |
1404 | }\r | |
1405 | \r | |
1406 | *PortNumber = 0;\r | |
1407 | \r | |
1408 | for (Index = 0; Index < 2; Index++) {\r | |
1409 | PSAddr = (UINT32) (USBPORTSC1 + Index * 2);\r | |
1410 | Status = ReadRootPortReg (\r | |
562d2849 | 1411 | HcDev->PciIo,\r |
1412 | PSAddr,\r | |
1413 | &RHPortControl\r | |
1414 | );\r | |
878ddf1f | 1415 | if (EFI_ERROR (Status)) {\r |
1416 | return EFI_DEVICE_ERROR;\r | |
1417 | }\r | |
1418 | //\r | |
1419 | // Port Register content is valid\r | |
1420 | //\r | |
1421 | if (RHPortControl != 0xff) {\r | |
1422 | (*PortNumber)++;\r | |
1423 | }\r | |
1424 | }\r | |
1425 | \r | |
1426 | return EFI_SUCCESS;\r | |
1427 | }\r | |
1428 | \r | |
1429 | EFI_STATUS\r | |
1430 | EFIAPI\r | |
1431 | UHCIGetRootHubPortStatus (\r | |
1432 | IN EFI_USB_HC_PROTOCOL *This,\r | |
1433 | IN UINT8 PortNumber,\r | |
1434 | OUT EFI_USB_PORT_STATUS *PortStatus\r | |
1435 | )\r | |
1436 | /*++\r | |
1437 | \r | |
1438 | Routine Description:\r | |
1439 | Retrieves the current status of a USB root hub port.\r | |
1440 | \r | |
1441 | Arguments:\r | |
1442 | \r | |
1443 | This A pointer to the EFI_USB_HC_PROTOCOL.\r | |
1444 | \r | |
1445 | PortNumber Specifies the root hub port from which the status \r | |
1446 | is to be retrieved. This value is zero-based. For example, \r | |
1447 | if a root hub has two ports, then the first port is numbered 0,\r | |
1448 | and the second port is numbered 1.\r | |
1449 | \r | |
1450 | PortStatus A pointer to the current port status bits and \r | |
1451 | port status change bits. \r | |
1452 | \r | |
1453 | Returns:\r | |
1454 | EFI_SUCCESS \r | |
1455 | The status of the USB root hub port specified by PortNumber \r | |
1456 | was returned in PortStatus.\r | |
1457 | EFI_INVALID_PARAMETER \r | |
1458 | PortNumber is invalid. \r | |
1459 | EFI_DEVICE_ERROR - Can't read register \r | |
1460 | --*/\r | |
1461 | {\r | |
1462 | USB_HC_DEV *HcDev;\r | |
1463 | UINT32 PSAddr;\r | |
1464 | UINT16 RHPortStatus;\r | |
1465 | UINT8 TotalPortNumber;\r | |
1466 | EFI_STATUS Status;\r | |
1467 | \r | |
1468 | if (PortStatus == NULL) {\r | |
1469 | return EFI_INVALID_PARAMETER;\r | |
1470 | }\r | |
1471 | \r | |
1472 | UHCIGetRootHubPortNumber (This, &TotalPortNumber);\r | |
1473 | if (PortNumber >= TotalPortNumber) {\r | |
1474 | return EFI_INVALID_PARAMETER;\r | |
1475 | }\r | |
1476 | \r | |
1477 | HcDev = USB_HC_DEV_FROM_THIS (This);\r | |
1478 | PSAddr = (UINT32) (USBPORTSC1 + PortNumber * 2);\r | |
1479 | \r | |
1480 | //\r | |
1481 | // Clear port status\r | |
1482 | //\r | |
1483 | PortStatus->PortStatus = 0;\r | |
1484 | PortStatus->PortChangeStatus = 0;\r | |
1485 | \r | |
1486 | Status = ReadRootPortReg (\r | |
562d2849 | 1487 | HcDev->PciIo,\r |
1488 | PSAddr,\r | |
1489 | &RHPortStatus\r | |
1490 | );\r | |
878ddf1f | 1491 | \r |
1492 | if (EFI_ERROR (Status)) {\r | |
1493 | return EFI_DEVICE_ERROR;\r | |
1494 | }\r | |
1495 | //\r | |
1496 | // Fill Port Status bits\r | |
1497 | //\r | |
1498 | \r | |
1499 | //\r | |
1500 | // Current Connect Status\r | |
1501 | //\r | |
1502 | if (RHPortStatus & USBPORTSC_CCS) {\r | |
1503 | PortStatus->PortStatus |= USB_PORT_STAT_CONNECTION;\r | |
1504 | }\r | |
1505 | //\r | |
1506 | // Port Enabled/Disabled\r | |
1507 | //\r | |
1508 | if (RHPortStatus & USBPORTSC_PED) {\r | |
1509 | PortStatus->PortStatus |= USB_PORT_STAT_ENABLE;\r | |
1510 | }\r | |
1511 | \r | |
1512 | //\r | |
1513 | // Port Suspend\r | |
1514 | //\r | |
1515 | if (RHPortStatus & USBPORTSC_SUSP) {\r | |
1516 | PortStatus->PortStatus |= USB_PORT_STAT_SUSPEND;\r | |
1517 | }\r | |
1518 | \r | |
1519 | //\r | |
1520 | // Port Reset\r | |
1521 | //\r | |
1522 | if (RHPortStatus & USBPORTSC_PR) {\r | |
1523 | PortStatus->PortStatus |= USB_PORT_STAT_RESET;\r | |
1524 | }\r | |
1525 | \r | |
1526 | //\r | |
1527 | // Low Speed Device Attached\r | |
1528 | //\r | |
1529 | if (RHPortStatus & USBPORTSC_LSDA) {\r | |
1530 | PortStatus->PortStatus |= USB_PORT_STAT_LOW_SPEED;\r | |
1531 | }\r | |
1532 | //\r | |
562d2849 | 1533 | // CHC will always return one in this bit\r |
1534 | //\r | |
1535 | PortStatus->PortStatus |= USB_PORT_STAT_OWNER;\r | |
1536 | //\r | |
878ddf1f | 1537 | // Fill Port Status Change bits\r |
1538 | //\r | |
1539 | \r | |
1540 | //\r | |
1541 | // Connect Status Change\r | |
1542 | //\r | |
1543 | if (RHPortStatus & USBPORTSC_CSC) {\r | |
1544 | PortStatus->PortChangeStatus |= USB_PORT_STAT_C_CONNECTION;\r | |
1545 | }\r | |
1546 | \r | |
1547 | //\r | |
1548 | // Port Enabled/Disabled Change\r | |
1549 | //\r | |
1550 | if (RHPortStatus & USBPORTSC_PEDC) {\r | |
1551 | PortStatus->PortChangeStatus |= USB_PORT_STAT_C_ENABLE;\r | |
1552 | }\r | |
1553 | \r | |
1554 | return EFI_SUCCESS;\r | |
1555 | }\r | |
1556 | \r | |
1557 | EFI_STATUS\r | |
1558 | EFIAPI\r | |
1559 | UHCISetRootHubPortFeature (\r | |
1560 | IN EFI_USB_HC_PROTOCOL *This,\r | |
1561 | IN UINT8 PortNumber,\r | |
1562 | IN EFI_USB_PORT_FEATURE PortFeature\r | |
1563 | )\r | |
1564 | /*++\r | |
1565 | \r | |
1566 | Routine Description:\r | |
1567 | Sets a feature for the specified root hub port.\r | |
1568 | \r | |
1569 | Arguments:\r | |
1570 | \r | |
1571 | This A pointer to the EFI_USB_HC_PROTOCOL.\r | |
1572 | \r | |
1573 | PortNumber Specifies the root hub port whose feature \r | |
1574 | is requested to be set.\r | |
1575 | \r | |
1576 | PortFeature Indicates the feature selector associated \r | |
1577 | with the feature set request. \r | |
1578 | \r | |
1579 | Returns:\r | |
1580 | EFI_SUCCESS \r | |
1581 | The feature specified by PortFeature was set for the \r | |
1582 | USB root hub port specified by PortNumber.\r | |
1583 | EFI_INVALID_PARAMETER \r | |
1584 | PortNumber is invalid or PortFeature is invalid.\r | |
1585 | EFI_DEVICE_ERROR\r | |
1586 | Can't read register\r | |
1587 | --*/\r | |
1588 | {\r | |
1589 | USB_HC_DEV *HcDev;\r | |
1590 | UINT32 PSAddr;\r | |
1591 | UINT32 CommandRegAddr;\r | |
1592 | //\r | |
1593 | // root hub port status\r | |
1594 | //\r | |
1595 | UINT16 RHPortControl;\r | |
1596 | UINT16 Command;\r | |
1597 | UINT8 TotalPortNumber;\r | |
1598 | EFI_STATUS Status;\r | |
1599 | \r | |
1600 | UHCIGetRootHubPortNumber (This, &TotalPortNumber);\r | |
1601 | if (PortNumber >= TotalPortNumber) {\r | |
1602 | return EFI_INVALID_PARAMETER;\r | |
1603 | }\r | |
1604 | \r | |
1605 | HcDev = USB_HC_DEV_FROM_THIS (This);\r | |
1606 | \r | |
1607 | PSAddr = (UINT32) (USBPORTSC1 + PortNumber * 2);\r | |
1608 | CommandRegAddr = (UINT32) (USBCMD);\r | |
1609 | \r | |
1610 | Status = ReadRootPortReg (\r | |
1611 | HcDev->PciIo,\r | |
1612 | PSAddr,\r | |
1613 | &RHPortControl\r | |
1614 | );\r | |
1615 | if (EFI_ERROR (Status)) {\r | |
1616 | return EFI_DEVICE_ERROR;\r | |
1617 | }\r | |
1618 | \r | |
1619 | switch (PortFeature) {\r | |
1620 | \r | |
1621 | case EfiUsbPortSuspend:\r | |
1622 | Status = ReadUHCCommandReg (\r | |
562d2849 | 1623 | HcDev->PciIo,\r |
1624 | CommandRegAddr,\r | |
1625 | &Command\r | |
1626 | );\r | |
878ddf1f | 1627 | if (EFI_ERROR (Status)) {\r |
1628 | return EFI_DEVICE_ERROR;\r | |
1629 | }\r | |
1630 | \r | |
1631 | if (!(Command & USBCMD_EGSM)) {\r | |
1632 | //\r | |
1633 | // if global suspend is not active, can set port suspend\r | |
1634 | //\r | |
1635 | RHPortControl &= 0xfff5;\r | |
1636 | RHPortControl |= USBPORTSC_SUSP;\r | |
1637 | }\r | |
1638 | break;\r | |
1639 | \r | |
1640 | case EfiUsbPortReset:\r | |
1641 | RHPortControl &= 0xfff5;\r | |
1642 | //\r | |
1643 | // Set the reset bit\r | |
1644 | //\r | |
1645 | RHPortControl |= USBPORTSC_PR;\r | |
1646 | break;\r | |
1647 | \r | |
1648 | case EfiUsbPortPower:\r | |
1649 | break;\r | |
1650 | \r | |
1651 | case EfiUsbPortEnable:\r | |
1652 | RHPortControl &= 0xfff5;\r | |
1653 | RHPortControl |= USBPORTSC_PED;\r | |
1654 | break;\r | |
1655 | \r | |
1656 | default:\r | |
1657 | return EFI_INVALID_PARAMETER;\r | |
1658 | }\r | |
1659 | \r | |
1660 | WriteRootPortReg (\r | |
1661 | HcDev->PciIo,\r | |
1662 | PSAddr,\r | |
1663 | RHPortControl\r | |
1664 | );\r | |
1665 | \r | |
1666 | return EFI_SUCCESS;\r | |
1667 | }\r | |
1668 | \r | |
1669 | EFI_STATUS\r | |
1670 | EFIAPI\r | |
1671 | UHCIClearRootHubPortFeature (\r | |
1672 | IN EFI_USB_HC_PROTOCOL *This,\r | |
1673 | IN UINT8 PortNumber,\r | |
1674 | IN EFI_USB_PORT_FEATURE PortFeature\r | |
1675 | )\r | |
1676 | /*++\r | |
1677 | \r | |
1678 | Routine Description:\r | |
1679 | Clears a feature for the specified root hub port.\r | |
1680 | \r | |
1681 | Arguments:\r | |
1682 | \r | |
1683 | This A pointer to the EFI_USB_HC_PROTOCOL instance.\r | |
1684 | \r | |
1685 | PortNumber Specifies the root hub port whose feature \r | |
1686 | is requested to be cleared.\r | |
1687 | \r | |
1688 | PortFeature Indicates the feature selector associated with the \r | |
1689 | feature clear request.\r | |
1690 | \r | |
1691 | Returns:\r | |
1692 | EFI_SUCCESS \r | |
1693 | The feature specified by PortFeature was cleared for the \r | |
1694 | USB root hub port specified by PortNumber.\r | |
1695 | EFI_INVALID_PARAMETER \r | |
1696 | PortNumber is invalid or PortFeature is invalid.\r | |
1697 | EFI_DEVICE_ERROR\r | |
1698 | Can't read register\r | |
1699 | --*/\r | |
1700 | {\r | |
1701 | USB_HC_DEV *HcDev;\r | |
1702 | UINT32 PSAddr;\r | |
1703 | UINT16 RHPortControl;\r | |
1704 | UINT8 TotalPortNumber;\r | |
1705 | EFI_STATUS Status;\r | |
1706 | \r | |
1707 | UHCIGetRootHubPortNumber (This, &TotalPortNumber);\r | |
1708 | \r | |
1709 | if (PortNumber >= TotalPortNumber) {\r | |
1710 | return EFI_INVALID_PARAMETER;\r | |
1711 | }\r | |
1712 | \r | |
1713 | HcDev = USB_HC_DEV_FROM_THIS (This);\r | |
1714 | PSAddr = (UINT32) (USBPORTSC1 + PortNumber * 2);\r | |
1715 | \r | |
1716 | Status = ReadRootPortReg (\r | |
562d2849 | 1717 | HcDev->PciIo,\r |
1718 | PSAddr,\r | |
1719 | &RHPortControl\r | |
1720 | );\r | |
878ddf1f | 1721 | if (EFI_ERROR (Status)) {\r |
1722 | return EFI_DEVICE_ERROR;\r | |
1723 | }\r | |
1724 | \r | |
1725 | switch (PortFeature) {\r | |
1726 | //\r | |
1727 | // clear PORT_ENABLE feature means disable port.\r | |
1728 | //\r | |
1729 | case EfiUsbPortEnable:\r | |
1730 | RHPortControl &= 0xfff5;\r | |
1731 | RHPortControl &= ~USBPORTSC_PED;\r | |
1732 | break;\r | |
1733 | \r | |
1734 | //\r | |
1735 | // clear PORT_SUSPEND feature means resume the port.\r | |
1736 | // (cause a resume on the specified port if in suspend mode)\r | |
1737 | //\r | |
1738 | case EfiUsbPortSuspend:\r | |
1739 | RHPortControl &= 0xfff5;\r | |
1740 | RHPortControl &= ~USBPORTSC_SUSP;\r | |
1741 | break;\r | |
1742 | \r | |
1743 | //\r | |
1744 | // no operation\r | |
1745 | //\r | |
1746 | case EfiUsbPortPower:\r | |
1747 | break;\r | |
1748 | \r | |
1749 | //\r | |
1750 | // clear PORT_RESET means clear the reset signal.\r | |
1751 | //\r | |
1752 | case EfiUsbPortReset:\r | |
1753 | RHPortControl &= 0xfff5;\r | |
1754 | RHPortControl &= ~USBPORTSC_PR;\r | |
1755 | break;\r | |
1756 | \r | |
1757 | //\r | |
1758 | // clear connect status change\r | |
1759 | //\r | |
1760 | case EfiUsbPortConnectChange:\r | |
1761 | RHPortControl &= 0xfff5;\r | |
1762 | RHPortControl |= USBPORTSC_CSC;\r | |
1763 | break;\r | |
1764 | \r | |
1765 | //\r | |
1766 | // clear enable/disable status change\r | |
1767 | //\r | |
1768 | case EfiUsbPortEnableChange:\r | |
1769 | RHPortControl &= 0xfff5;\r | |
1770 | RHPortControl |= USBPORTSC_PEDC;\r | |
1771 | break;\r | |
1772 | \r | |
1773 | //\r | |
1774 | // root hub does not support this request\r | |
1775 | //\r | |
1776 | case EfiUsbPortSuspendChange:\r | |
1777 | break;\r | |
1778 | \r | |
1779 | //\r | |
1780 | // root hub does not support this request\r | |
1781 | //\r | |
1782 | case EfiUsbPortOverCurrentChange:\r | |
1783 | break;\r | |
1784 | \r | |
1785 | //\r | |
1786 | // root hub does not support this request\r | |
1787 | //\r | |
1788 | case EfiUsbPortResetChange:\r | |
1789 | break;\r | |
1790 | \r | |
1791 | default:\r | |
1792 | return EFI_INVALID_PARAMETER;\r | |
1793 | }\r | |
1794 | \r | |
1795 | WriteRootPortReg (\r | |
1796 | HcDev->PciIo,\r | |
1797 | PSAddr,\r | |
1798 | RHPortControl\r | |
1799 | );\r | |
1800 | \r | |
1801 | return EFI_SUCCESS;\r | |
1802 | }\r | |
1803 | \r | |
1804 | EFI_STATUS\r | |
1805 | EFIAPI\r | |
1806 | UHCIControlTransfer (\r | |
1807 | IN EFI_USB_HC_PROTOCOL *This,\r | |
1808 | IN UINT8 DeviceAddress,\r | |
1809 | IN BOOLEAN IsSlowDevice,\r | |
1810 | IN UINT8 MaximumPacketLength,\r | |
1811 | IN EFI_USB_DEVICE_REQUEST *Request,\r | |
1812 | IN EFI_USB_DATA_DIRECTION TransferDirection,\r | |
1813 | IN OUT VOID *Data, OPTIONAL\r | |
1814 | IN OUT UINTN *DataLength, OPTIONAL\r | |
1815 | IN UINTN TimeOut,\r | |
1816 | OUT UINT32 *TransferResult\r | |
1817 | )\r | |
1818 | /*++\r | |
1819 | \r | |
1820 | Routine Description:\r | |
1821 | Submits control transfer to a target USB device.\r | |
1822 | \r | |
1823 | Arguments:\r | |
1824 | \r | |
1825 | This A pointer to the EFI_USB_HC_PROTOCOL instance.\r | |
1826 | \r | |
1827 | DeviceAddress Represents the address of the target device on the USB,\r | |
1828 | which is assigned during USB enumeration.\r | |
1829 | \r | |
1830 | IsSlowDevice Indicates whether the target device is slow device \r | |
1831 | or full-speed device.\r | |
1832 | \r | |
1833 | MaximumPacketLength Indicates the maximum packet size that the \r | |
1834 | default control transfer endpoint is capable of \r | |
1835 | sending or receiving.\r | |
1836 | \r | |
1837 | Request A pointer to the USB device request that will be sent \r | |
1838 | to the USB device. \r | |
1839 | \r | |
1840 | TransferDirection Specifies the data direction for the transfer.\r | |
1841 | There are three values available, DataIn, DataOut \r | |
1842 | and NoData.\r | |
1843 | \r | |
1844 | Data A pointer to the buffer of data that will be transmitted \r | |
1845 | to USB device or received from USB device.\r | |
1846 | \r | |
1847 | DataLength Indicates the size, in bytes, of the data buffer \r | |
1848 | specified by Data.\r | |
1849 | \r | |
1850 | TimeOut Indicates the maximum time, in microseconds, \r | |
1851 | which the transfer is allowed to complete.\r | |
1852 | \r | |
1853 | TransferResult A pointer to the detailed result information generated \r | |
1854 | by this control transfer.\r | |
1855 | \r | |
1856 | Returns:\r | |
1857 | EFI_SUCCESS \r | |
1858 | The control transfer was completed successfully.\r | |
1859 | EFI_OUT_OF_RESOURCES \r | |
1860 | The control transfer could not be completed due to a lack of resources.\r | |
1861 | EFI_INVALID_PARAMETER \r | |
1862 | Some parameters are invalid.\r | |
1863 | EFI_TIMEOUT \r | |
1864 | The control transfer failed due to timeout.\r | |
1865 | EFI_DEVICE_ERROR \r | |
1866 | The control transfer failed due to host controller or device error. \r | |
1867 | Caller should check TranferResult for detailed error information.\r | |
1868 | \r | |
1869 | --*/\r | |
1870 | {\r | |
1871 | USB_HC_DEV *HcDev;\r | |
1872 | UINT32 StatusReg;\r | |
1873 | UINT32 FrameNumReg;\r | |
1874 | UINT8 PktID;\r | |
1875 | QH_STRUCT *PtrQH;\r | |
1876 | TD_STRUCT *PtrTD;\r | |
1877 | TD_STRUCT *PtrPreTD;\r | |
1878 | TD_STRUCT *PtrSetupTD;\r | |
1879 | TD_STRUCT *PtrStatusTD;\r | |
1880 | EFI_STATUS Status;\r | |
1881 | UINTN Index;\r | |
1882 | UINTN DataLen;\r | |
1883 | UINT8 *PtrDataSource;\r | |
1884 | UINT8 *Ptr;\r | |
1885 | UINT8 DataToggle;\r | |
1886 | UINT16 LoadFrameListIndex;\r | |
1887 | UINT8 PktSize;\r | |
1888 | \r | |
1889 | UINT8 *RequestMappedAddress;\r | |
1890 | VOID *RequestMapping;\r | |
1891 | UINTN RequestLen;\r | |
1892 | \r | |
1893 | EFI_PHYSICAL_ADDRESS TempPtr;\r | |
1894 | VOID *Mapping;\r | |
1895 | \r | |
1896 | TD_STRUCT *PtrFirstDataTD;\r | |
1897 | TD_STRUCT *ptrLastDataTD;\r | |
1898 | BOOLEAN FirstTD;\r | |
1899 | \r | |
1900 | FirstTD = FALSE;\r | |
1901 | RequestMappedAddress = NULL;\r | |
1902 | RequestMapping = NULL;\r | |
1903 | Mapping = NULL;\r | |
1904 | PtrFirstDataTD = NULL;\r | |
1905 | ptrLastDataTD = NULL;\r | |
1906 | PktID = INPUT_PACKET_ID;\r | |
1907 | Mapping = NULL;\r | |
1908 | HcDev = USB_HC_DEV_FROM_THIS (This);\r | |
1909 | StatusReg = (UINT32) (USBSTS);\r | |
1910 | FrameNumReg = (UINT32) (USBFRNUM);\r | |
1911 | PtrPreTD = NULL;\r | |
1912 | PtrTD = NULL;\r | |
1913 | \r | |
1914 | //\r | |
1915 | // Parameters Checking\r | |
1916 | //\r | |
1917 | if (Request == NULL || TransferResult == NULL) {\r | |
1918 | return EFI_INVALID_PARAMETER;\r | |
1919 | }\r | |
1920 | \r | |
1921 | //\r | |
1922 | // if errors exist that cause host controller halt,\r | |
1923 | // then return EFI_DEVICE_ERROR.\r | |
1924 | //\r | |
1925 | if (!IsStatusOK (HcDev->PciIo, StatusReg)) {\r | |
1926 | \r | |
1927 | ClearStatusReg (HcDev->PciIo, StatusReg);\r | |
1928 | *TransferResult = EFI_USB_ERR_SYSTEM;\r | |
1929 | return EFI_DEVICE_ERROR;\r | |
1930 | }\r | |
1931 | \r | |
1932 | //\r | |
1933 | // low speed usb devices are limited to only an eight-byte\r | |
1934 | // maximum data payload size\r | |
1935 | //\r | |
1936 | if (IsSlowDevice && (MaximumPacketLength != 8)) {\r | |
1937 | return EFI_INVALID_PARAMETER;\r | |
1938 | }\r | |
1939 | \r | |
1940 | if (MaximumPacketLength != 8 && \r | |
1941 | MaximumPacketLength != 16 &&\r | |
1942 | MaximumPacketLength != 32 &&\r | |
1943 | MaximumPacketLength != 64) {\r | |
1944 | return EFI_INVALID_PARAMETER;\r | |
1945 | }\r | |
1946 | \r | |
1947 | if ((TransferDirection != EfiUsbNoData) && (DataLength == NULL)) {\r | |
1948 | return EFI_INVALID_PARAMETER;\r | |
1949 | }\r | |
1950 | \r | |
1951 | switch (TransferDirection) {\r | |
1952 | \r | |
1953 | case EfiUsbDataIn:\r | |
1954 | PktID = INPUT_PACKET_ID;\r | |
1955 | PtrDataSource = Data;\r | |
1956 | DataLen = *DataLength;\r | |
1957 | \r | |
1958 | //\r | |
1959 | // map the source data buffer for bus master access.\r | |
1960 | // BusMasterWrite means cpu read\r | |
1961 | //\r | |
1962 | Status = HcDev->PciIo->Map (\r | |
562d2849 | 1963 | HcDev->PciIo,\r |
1964 | EfiPciIoOperationBusMasterWrite,\r | |
1965 | PtrDataSource,\r | |
1966 | &DataLen,\r | |
1967 | &TempPtr,\r | |
1968 | &Mapping\r | |
1969 | );\r | |
878ddf1f | 1970 | if (EFI_ERROR (Status)) {\r |
1971 | return Status;\r | |
1972 | }\r | |
1973 | \r | |
1974 | Ptr = (UINT8 *) ((UINTN) TempPtr);\r | |
1975 | break;\r | |
1976 | \r | |
1977 | case EfiUsbDataOut:\r | |
1978 | PktID = OUTPUT_PACKET_ID;\r | |
1979 | PtrDataSource = Data;\r | |
1980 | DataLen = *DataLength;\r | |
1981 | \r | |
1982 | //\r | |
1983 | // map the source data buffer for bus master access.\r | |
1984 | // BusMasterRead means cpu write\r | |
1985 | //\r | |
1986 | Status = HcDev->PciIo->Map (\r | |
562d2849 | 1987 | HcDev->PciIo,\r |
1988 | EfiPciIoOperationBusMasterRead,\r | |
1989 | PtrDataSource,\r | |
1990 | &DataLen,\r | |
1991 | &TempPtr,\r | |
1992 | &Mapping\r | |
1993 | );\r | |
878ddf1f | 1994 | if (EFI_ERROR (Status)) {\r |
1995 | return Status;\r | |
1996 | }\r | |
1997 | \r | |
1998 | Ptr = (UINT8 *) ((UINTN) TempPtr);\r | |
1999 | break;\r | |
2000 | \r | |
2001 | //\r | |
2002 | // no data stage\r | |
2003 | //\r | |
2004 | case EfiUsbNoData:\r | |
2005 | if ((DataLength != NULL) && (*DataLength != 0)) {\r | |
2006 | return EFI_INVALID_PARAMETER;\r | |
2007 | }\r | |
2008 | \r | |
2009 | PktID = OUTPUT_PACKET_ID;\r | |
2010 | PtrDataSource = NULL;\r | |
2011 | DataLen = 0;\r | |
2012 | Ptr = NULL;\r | |
2013 | break;\r | |
2014 | \r | |
2015 | default:\r | |
2016 | return EFI_INVALID_PARAMETER;\r | |
2017 | }\r | |
2018 | \r | |
2019 | Status = ClearStatusReg (HcDev->PciIo, StatusReg);\r | |
2020 | if (EFI_ERROR (Status)) {\r | |
2021 | HcDev->PciIo->Unmap (HcDev->PciIo, Mapping);\r | |
2022 | return EFI_DEVICE_ERROR;\r | |
2023 | }\r | |
2024 | //\r | |
2025 | // create QH structure and init\r | |
2026 | //\r | |
2027 | Status = CreateQH (HcDev, &PtrQH);\r | |
2028 | if (EFI_ERROR (Status)) {\r | |
2029 | HcDev->PciIo->Unmap (HcDev->PciIo, Mapping);\r | |
2030 | return Status;\r | |
2031 | }\r | |
2032 | \r | |
2033 | //\r | |
2034 | // map the Request for bus master access.\r | |
2035 | // BusMasterRead means cpu write\r | |
2036 | //\r | |
2037 | RequestLen = sizeof (EFI_USB_DEVICE_REQUEST);\r | |
2038 | Status = HcDev->PciIo->Map (\r | |
562d2849 | 2039 | HcDev->PciIo,\r |
2040 | EfiPciIoOperationBusMasterRead,\r | |
2041 | (UINT8 *) Request,\r | |
2042 | &RequestLen,\r | |
2043 | &TempPtr,\r | |
2044 | &RequestMapping\r | |
2045 | );\r | |
878ddf1f | 2046 | \r |
2047 | if (EFI_ERROR (Status)) {\r | |
2048 | HcDev->PciIo->Unmap (HcDev->PciIo, Mapping);\r | |
2049 | UhciFreePool (HcDev, (UINT8 *) PtrQH, sizeof (QH_STRUCT));\r | |
2050 | return Status;\r | |
2051 | }\r | |
2052 | \r | |
2053 | RequestMappedAddress = (UINT8 *) ((UINTN) TempPtr);\r | |
2054 | \r | |
2055 | //\r | |
2056 | // generate Setup Stage TD\r | |
2057 | //\r | |
2058 | Status = GenSetupStageTD (\r | |
562d2849 | 2059 | HcDev,\r |
2060 | DeviceAddress,\r | |
2061 | 0,\r | |
2062 | IsSlowDevice,\r | |
2063 | (UINT8 *) RequestMappedAddress,\r | |
2064 | sizeof (EFI_USB_DEVICE_REQUEST),\r | |
2065 | &PtrSetupTD\r | |
2066 | );\r | |
878ddf1f | 2067 | \r |
2068 | if (EFI_ERROR (Status)) {\r | |
2069 | HcDev->PciIo->Unmap (HcDev->PciIo, Mapping);\r | |
2070 | UhciFreePool (HcDev, (UINT8 *) PtrQH, sizeof (QH_STRUCT));\r | |
2071 | HcDev->PciIo->Unmap (HcDev->PciIo, RequestMapping);\r | |
2072 | return Status;\r | |
2073 | }\r | |
2074 | \r | |
2075 | //\r | |
2076 | // Data Stage of Control Transfer\r | |
2077 | //\r | |
2078 | DataToggle = 1;\r | |
2079 | FirstTD = TRUE;\r | |
2080 | while (DataLen > 0) {\r | |
2081 | //\r | |
2082 | // create TD structures and link together\r | |
2083 | //\r | |
2084 | \r | |
2085 | //\r | |
2086 | // PktSize is the data load size that each TD carries.\r | |
2087 | //\r | |
2088 | PktSize = (UINT8) DataLen;\r | |
2089 | if (DataLen > MaximumPacketLength) {\r | |
2090 | PktSize = MaximumPacketLength;\r | |
2091 | }\r | |
2092 | \r | |
2093 | Status = GenDataTD (\r | |
562d2849 | 2094 | HcDev,\r |
2095 | DeviceAddress,\r | |
2096 | 0,\r | |
2097 | Ptr,\r | |
2098 | PktSize,\r | |
2099 | PktID,\r | |
2100 | DataToggle,\r | |
2101 | IsSlowDevice,\r | |
2102 | &PtrTD\r | |
2103 | );\r | |
878ddf1f | 2104 | \r |
2105 | if (EFI_ERROR (Status)) {\r | |
2106 | //\r | |
2107 | // free all resources occupied\r | |
2108 | //\r | |
2109 | HcDev->PciIo->Unmap (HcDev->PciIo, Mapping);\r | |
2110 | UhciFreePool (HcDev, (UINT8 *) PtrQH, sizeof (QH_STRUCT));\r | |
2111 | HcDev->PciIo->Unmap (HcDev->PciIo, RequestMapping);\r | |
2112 | DeleteQueuedTDs (HcDev, PtrSetupTD);\r | |
2113 | DeleteQueuedTDs (HcDev, PtrFirstDataTD);\r | |
2114 | return Status;\r | |
2115 | }\r | |
2116 | \r | |
2117 | //\r | |
2118 | // Link two TDs in vertical depth\r | |
2119 | //\r | |
2120 | if (FirstTD) {\r | |
2121 | PtrFirstDataTD = PtrTD;\r | |
2122 | PtrFirstDataTD->ptrNextTD = NULL;\r | |
2123 | FirstTD = FALSE;\r | |
2124 | } else {\r | |
2125 | LinkTDToTD (PtrPreTD, PtrTD);\r | |
2126 | }\r | |
2127 | \r | |
2128 | PtrPreTD = PtrTD;\r | |
2129 | \r | |
2130 | DataToggle ^= 1;\r | |
2131 | Ptr += PktSize;\r | |
2132 | DataLen -= PktSize;\r | |
2133 | }\r | |
2134 | \r | |
2135 | ptrLastDataTD = PtrTD;\r | |
2136 | \r | |
2137 | //\r | |
2138 | // Status Stage of Control Transfer\r | |
2139 | //\r | |
2140 | if (PktID == OUTPUT_PACKET_ID) {\r | |
2141 | PktID = INPUT_PACKET_ID;\r | |
2142 | } else {\r | |
2143 | PktID = OUTPUT_PACKET_ID;\r | |
2144 | }\r | |
2145 | \r | |
2146 | //\r | |
2147 | // create Status Stage TD structure\r | |
2148 | //\r | |
2149 | Status = CreateStatusTD (\r | |
562d2849 | 2150 | HcDev,\r |
2151 | DeviceAddress,\r | |
2152 | 0,\r | |
2153 | PktID,\r | |
2154 | IsSlowDevice,\r | |
2155 | &PtrStatusTD\r | |
2156 | );\r | |
878ddf1f | 2157 | \r |
2158 | if (EFI_ERROR (Status)) {\r | |
2159 | HcDev->PciIo->Unmap (HcDev->PciIo, Mapping);\r | |
2160 | UhciFreePool (HcDev, (UINT8 *) PtrQH, sizeof (QH_STRUCT));\r | |
2161 | HcDev->PciIo->Unmap (HcDev->PciIo, RequestMapping);\r | |
2162 | DeleteQueuedTDs (HcDev, PtrSetupTD);\r | |
2163 | DeleteQueuedTDs (HcDev, PtrFirstDataTD);\r | |
2164 | return Status;\r | |
2165 | }\r | |
2166 | \r | |
2167 | if (IsSlowDevice) {\r | |
2168 | //\r | |
2169 | // link setup TD structures to QH structure\r | |
2170 | //\r | |
2171 | LinkTDToQH (PtrQH, PtrSetupTD);\r | |
2172 | \r | |
2173 | LoadFrameListIndex = (UINT16) ((GetCurrentFrameNumber (HcDev->PciIo, FrameNumReg)) & 0x3FF);\r | |
2174 | \r | |
2175 | //\r | |
2176 | // link QH-TDs to total 100 frame list entry to speed up the execution.\r | |
2177 | //\r | |
2178 | for (Index = 0; Index < 100; Index++) {\r | |
2179 | LinkQHToFrameList (\r | |
2180 | HcDev->FrameListEntry,\r | |
2181 | (UINT16) ((LoadFrameListIndex + Index) & 0x3FF),\r | |
2182 | PtrQH\r | |
2183 | );\r | |
2184 | }\r | |
2185 | //\r | |
2186 | // Poll QH-TDs execution and get result.\r | |
2187 | // detail status is returned\r | |
2188 | //\r | |
2189 | Status = ExecuteControlTransfer (\r | |
2190 | HcDev,\r | |
2191 | PtrSetupTD,\r | |
2192 | LoadFrameListIndex,\r | |
2193 | DataLength,\r | |
2194 | TimeOut,\r | |
2195 | TransferResult\r | |
2196 | );\r | |
2197 | //\r | |
2198 | // Remove Control Transfer QH-TDs structure from the frame list\r | |
2199 | // and update the pointers in the Frame List\r | |
2200 | // and other pointers in other related QH structures.\r | |
2201 | //\r | |
2202 | for (Index = 0; Index < 100; Index++) {\r | |
2203 | DelLinkSingleQH (\r | |
2204 | HcDev,\r | |
2205 | PtrQH,\r | |
2206 | (UINT16) ((LoadFrameListIndex + Index) & 0x3FF),\r | |
2207 | FALSE,\r | |
2208 | FALSE\r | |
2209 | );\r | |
2210 | }\r | |
2211 | //\r | |
2212 | // delete setup stage TD; the QH is reserved for the next stages.\r | |
2213 | //\r | |
2214 | DeleteQueuedTDs (HcDev, PtrSetupTD);\r | |
2215 | \r | |
2216 | //\r | |
2217 | // if setup stage error, return error\r | |
2218 | //\r | |
2219 | if (EFI_ERROR (Status)) {\r | |
2220 | goto Done;\r | |
2221 | }\r | |
2222 | //\r | |
2223 | // some control transfers do not have Data Stage\r | |
2224 | //\r | |
2225 | if (PtrFirstDataTD != NULL) {\r | |
2226 | \r | |
2227 | LinkTDToQH (PtrQH, PtrFirstDataTD);\r | |
2228 | LoadFrameListIndex = (UINT16) ((GetCurrentFrameNumber (HcDev->PciIo, FrameNumReg)) & 0x3FF);\r | |
2229 | \r | |
2230 | for (Index = 0; Index < 500; Index++) {\r | |
2231 | LinkQHToFrameList (\r | |
2232 | HcDev->FrameListEntry,\r | |
2233 | (UINT16) ((LoadFrameListIndex + Index) & 0x3FF),\r | |
2234 | PtrQH\r | |
2235 | );\r | |
2236 | }\r | |
2237 | \r | |
2238 | Status = ExecuteControlTransfer (\r | |
562d2849 | 2239 | HcDev,\r |
2240 | PtrFirstDataTD,\r | |
2241 | LoadFrameListIndex,\r | |
2242 | DataLength,\r | |
2243 | TimeOut,\r | |
2244 | TransferResult\r | |
2245 | );\r | |
878ddf1f | 2246 | \r |
2247 | for (Index = 0; Index < 500; Index++) {\r | |
2248 | DelLinkSingleQH (\r | |
2249 | HcDev,\r | |
2250 | PtrQH,\r | |
2251 | (UINT16) ((LoadFrameListIndex + Index) & 0x3FF),\r | |
2252 | FALSE,\r | |
2253 | FALSE\r | |
2254 | );\r | |
2255 | }\r | |
2256 | //\r | |
2257 | // delete data stage TD; the QH is reserved for the next stage.\r | |
2258 | //\r | |
2259 | DeleteQueuedTDs (HcDev, PtrFirstDataTD);\r | |
2260 | }\r | |
2261 | //\r | |
2262 | // if data stage error, goto done and return error\r | |
2263 | //\r | |
2264 | if (EFI_ERROR (Status)) {\r | |
2265 | goto Done;\r | |
2266 | }\r | |
2267 | \r | |
2268 | LinkTDToQH (PtrQH, PtrStatusTD);\r | |
2269 | //\r | |
2270 | // get the frame list index that the QH-TDs will be linked to.\r | |
2271 | //\r | |
2272 | LoadFrameListIndex = (UINT16) ((GetCurrentFrameNumber (HcDev->PciIo, FrameNumReg)) & 0x3FF);\r | |
2273 | \r | |
2274 | for (Index = 0; Index < 100; Index++) {\r | |
2275 | //\r | |
2276 | // put the QH-TDs directly or indirectly into the proper place\r | |
2277 | // in the Frame List\r | |
2278 | //\r | |
2279 | LinkQHToFrameList (\r | |
2280 | HcDev->FrameListEntry,\r | |
2281 | (UINT16) ((LoadFrameListIndex + Index) & 0x3FF),\r | |
2282 | PtrQH\r | |
2283 | );\r | |
2284 | }\r | |
2285 | //\r | |
2286 | // Poll QH-TDs execution and get result.\r | |
2287 | // detail status is returned\r | |
2288 | //\r | |
2289 | Status = ExecuteControlTransfer (\r | |
562d2849 | 2290 | HcDev,\r |
2291 | PtrStatusTD,\r | |
2292 | LoadFrameListIndex,\r | |
2293 | DataLength,\r | |
2294 | TimeOut,\r | |
2295 | TransferResult\r | |
2296 | );\r | |
878ddf1f | 2297 | \r |
2298 | //\r | |
2299 | // Delete Control Transfer QH-TDs structure\r | |
2300 | // and update the pointers in the Frame List\r | |
2301 | // and other pointers in other related QH structures.\r | |
2302 | //\r | |
2303 | // TRUE means must search other framelistindex\r | |
2304 | //\r | |
2305 | for (Index = 0; Index < 100; Index++) {\r | |
2306 | DelLinkSingleQH (\r | |
2307 | HcDev,\r | |
2308 | PtrQH,\r | |
2309 | (UINT16) ((LoadFrameListIndex + Index) & 0x3FF),\r | |
2310 | FALSE,\r | |
2311 | FALSE\r | |
2312 | );\r | |
2313 | }\r | |
2314 | \r | |
2315 | DeleteQueuedTDs (HcDev, PtrStatusTD);\r | |
2316 | \r | |
2317 | } else {\r | |
2318 | //\r | |
2319 | // link setup stage TD with data stage TD\r | |
2320 | //\r | |
2321 | PtrPreTD = PtrSetupTD;\r | |
2322 | if (PtrFirstDataTD != NULL) {\r | |
2323 | LinkTDToTD (PtrSetupTD, PtrFirstDataTD);\r | |
2324 | PtrPreTD = ptrLastDataTD;\r | |
2325 | }\r | |
2326 | //\r | |
2327 | // link status TD with previous TD\r | |
2328 | //\r | |
2329 | LinkTDToTD (PtrPreTD, PtrStatusTD);\r | |
2330 | \r | |
2331 | //\r | |
2332 | // link QH with TD\r | |
2333 | //\r | |
2334 | LinkTDToQH (PtrQH, PtrSetupTD);\r | |
2335 | \r | |
2336 | LoadFrameListIndex = (UINT16) ((GetCurrentFrameNumber (HcDev->PciIo, FrameNumReg)) & 0x3FF);\r | |
2337 | for (Index = 0; Index < 500; Index++) {\r | |
2338 | //\r | |
2339 | // put the QH-TDs directly or indirectly into the proper place\r | |
2340 | // in the Frame List\r | |
2341 | //\r | |
2342 | LinkQHToFrameList (\r | |
2343 | HcDev->FrameListEntry,\r | |
2344 | (UINT16) ((LoadFrameListIndex + Index) & 0x3FF),\r | |
2345 | PtrQH\r | |
2346 | );\r | |
2347 | }\r | |
2348 | //\r | |
2349 | // Poll QH-TDs execution and get result.\r | |
2350 | // detail status is returned\r | |
2351 | //\r | |
2352 | Status = ExecuteControlTransfer (\r | |
562d2849 | 2353 | HcDev,\r |
2354 | PtrSetupTD,\r | |
2355 | LoadFrameListIndex,\r | |
2356 | DataLength,\r | |
2357 | TimeOut,\r | |
2358 | TransferResult\r | |
2359 | );\r | |
878ddf1f | 2360 | //\r |
2361 | // Remove Control Transfer QH-TDs structure from the frame list\r | |
2362 | // and update the pointers in the Frame List\r | |
2363 | // and other pointers in other related QH structures.\r | |
2364 | //\r | |
2365 | for (Index = 0; Index < 500; Index++) {\r | |
2366 | DelLinkSingleQH (\r | |
2367 | HcDev,\r | |
2368 | PtrQH,\r | |
2369 | (UINT16) ((LoadFrameListIndex + Index) & 0x3FF),\r | |
2370 | FALSE,\r | |
2371 | FALSE\r | |
2372 | );\r | |
2373 | }\r | |
2374 | \r | |
2375 | DeleteQueuedTDs (HcDev, PtrSetupTD);\r | |
2376 | }\r | |
2377 | \r | |
2378 | Done:\r | |
2379 | \r | |
2380 | UhciFreePool (HcDev, (UINT8 *) PtrQH, sizeof (QH_STRUCT));\r | |
2381 | \r | |
2382 | if (Mapping != NULL) {\r | |
2383 | HcDev->PciIo->Unmap (HcDev->PciIo, Mapping);\r | |
2384 | }\r | |
2385 | \r | |
2386 | if (RequestMapping != NULL) {\r | |
2387 | HcDev->PciIo->Unmap (HcDev->PciIo, RequestMapping);\r | |
2388 | }\r | |
2389 | //\r | |
2390 | // if has errors that cause host controller halt,\r | |
2391 | // then return EFI_DEVICE_ERROR directly.\r | |
2392 | //\r | |
2393 | if (!IsStatusOK (HcDev->PciIo, StatusReg)) {\r | |
2394 | \r | |
2395 | ClearStatusReg (HcDev->PciIo, StatusReg);\r | |
2396 | *TransferResult |= EFI_USB_ERR_SYSTEM;\r | |
2397 | return EFI_DEVICE_ERROR;\r | |
2398 | }\r | |
2399 | \r | |
2400 | ClearStatusReg (HcDev->PciIo, StatusReg);\r | |
2401 | HcDev->PciIo->Flush (HcDev->PciIo);\r | |
2402 | return Status;\r | |
2403 | }\r | |
2404 | \r | |
2405 | EFI_STATUS\r | |
2406 | EFIAPI\r | |
2407 | UHCIBulkTransfer (\r | |
2408 | IN EFI_USB_HC_PROTOCOL *This,\r | |
2409 | IN UINT8 DeviceAddress,\r | |
2410 | IN UINT8 EndPointAddress,\r | |
2411 | IN UINT8 MaximumPacketLength,\r | |
2412 | IN OUT VOID *Data,\r | |
2413 | IN OUT UINTN *DataLength,\r | |
2414 | IN OUT UINT8 *DataToggle,\r | |
2415 | IN UINTN TimeOut,\r | |
2416 | OUT UINT32 *TransferResult\r | |
2417 | )\r | |
2418 | /*++\r | |
2419 | \r | |
2420 | Routine Description:\r | |
2421 | Submits bulk transfer to a bulk endpoint of a USB device.\r | |
2422 | \r | |
2423 | Arguments:\r | |
2424 | \r | |
2425 | This A pointer to the EFI_USB_HC_PROTOCOL instance.\r | |
2426 | \r | |
2427 | DeviceAddress Represents the address of the target device on the USB,\r | |
2428 | which is assigned during USB enumeration.\r | |
2429 | EndPointAddress The combination of an endpoint number and an \r | |
2430 | endpoint direction of the target USB device. \r | |
2431 | Each endpoint address supports data transfer in \r | |
2432 | one direction except the control endpoint \r | |
2433 | (whose default endpoint address is 0). \r | |
2434 | It is the caller's responsibility to make sure that \r | |
2435 | the EndPointAddress represents a bulk endpoint. \r | |
2436 | \r | |
2437 | MaximumPacketLength Indicates the maximum packet size the target endpoint\r | |
2438 | is capable of sending or receiving.\r | |
2439 | \r | |
2440 | Data A pointer to the buffer of data that will be transmitted \r | |
2441 | to USB device or received from USB device.\r | |
2442 | DataLength When input, indicates the size, in bytes, of the data buffer\r | |
2443 | specified by Data. When output, indicates the actually \r | |
2444 | transferred data size.\r | |
2445 | \r | |
2446 | DataToggle A pointer to the data toggle value. On input, it indicates \r | |
2447 | the initial data toggle value the bulk transfer should adopt;\r | |
2448 | on output, it is updated to indicate the data toggle value \r | |
2449 | of the subsequent bulk transfer. \r | |
2450 | \r | |
2451 | TimeOut Indicates the maximum time, in microseconds, which the \r | |
2452 | transfer is allowed to complete.\r | |
2453 | \r | |
2454 | TransferResult A pointer to the detailed result information of the \r | |
2455 | bulk transfer.\r | |
2456 | \r | |
2457 | Returns:\r | |
2458 | EFI_SUCCESS \r | |
2459 | The bulk transfer was completed successfully.\r | |
2460 | EFI_OUT_OF_RESOURCES \r | |
2461 | The bulk transfer could not be submitted due to lack of resource.\r | |
2462 | EFI_INVALID_PARAMETER \r | |
2463 | Some parameters are invalid.\r | |
2464 | EFI_TIMEOUT \r | |
2465 | The bulk transfer failed due to timeout.\r | |
2466 | EFI_DEVICE_ERROR \r | |
2467 | The bulk transfer failed due to host controller or device error.\r | |
2468 | Caller should check TranferResult for detailed error information.\r | |
2469 | \r | |
2470 | --*/\r | |
2471 | {\r | |
2472 | USB_HC_DEV *HcDev;\r | |
2473 | UINT32 StatusReg;\r | |
2474 | UINT32 FrameNumReg;\r | |
2475 | UINTN DataLen;\r | |
2476 | QH_STRUCT *PtrQH;\r | |
2477 | TD_STRUCT *PtrFirstTD;\r | |
2478 | TD_STRUCT *PtrTD;\r | |
2479 | TD_STRUCT *PtrPreTD;\r | |
2480 | UINT16 LoadFrameListIndex;\r | |
2481 | UINT16 SavedFrameListIndex;\r | |
2482 | UINT8 PktID;\r | |
2483 | UINT8 *PtrDataSource;\r | |
2484 | UINT8 *Ptr;\r | |
2485 | BOOLEAN IsFirstTD;\r | |
2486 | EFI_STATUS Status;\r | |
2487 | UINT32 Index;\r | |
2488 | UINT8 PktSize;\r | |
2489 | \r | |
2490 | EFI_USB_DATA_DIRECTION TransferDirection;\r | |
2491 | //\r | |
2492 | // Used to calculate how many entries are linked to the\r | |
2493 | // specified bulk transfer QH-TDs\r | |
2494 | //\r | |
2495 | UINT32 LinkTimes;\r | |
2496 | \r | |
2497 | BOOLEAN ShortPacketEnable;\r | |
2498 | EFI_PHYSICAL_ADDRESS TempPtr;\r | |
2499 | VOID *Mapping;\r | |
2500 | \r | |
2501 | HcDev = USB_HC_DEV_FROM_THIS (This);\r | |
2502 | StatusReg = (UINT32) (USBSTS);\r | |
2503 | FrameNumReg = (UINT32) (USBFRNUM);\r | |
2504 | PktID = INPUT_PACKET_ID;\r | |
2505 | PtrTD = NULL;\r | |
2506 | PtrFirstTD = NULL;\r | |
2507 | PtrPreTD = NULL;\r | |
2508 | LinkTimes = 1;\r | |
2509 | DataLen = 0;\r | |
2510 | Ptr = NULL;\r | |
2511 | ShortPacketEnable = FALSE;\r | |
2512 | Mapping = NULL;\r | |
2513 | \r | |
2514 | //\r | |
2515 | // Parameters Checking\r | |
2516 | //\r | |
2517 | \r | |
2518 | if ((DataLength == NULL) ||\r | |
2519 | (Data == NULL) ||\r | |
2520 | (TransferResult == NULL)) {\r | |
2521 | return EFI_INVALID_PARAMETER;\r | |
2522 | }\r | |
2523 | \r | |
2524 | //\r | |
2525 | // if has errors that cause host controller halt,\r | |
2526 | // then return EFI_DEVICE_ERROR directly.\r | |
2527 | //\r | |
2528 | if (!IsStatusOK (HcDev->PciIo, StatusReg)) {\r | |
2529 | \r | |
2530 | ClearStatusReg (HcDev->PciIo, StatusReg);\r | |
2531 | *TransferResult = EFI_USB_ERR_SYSTEM;\r | |
2532 | return EFI_DEVICE_ERROR;\r | |
2533 | }\r | |
2534 | \r | |
2535 | if (*DataLength == 0) {\r | |
2536 | return EFI_INVALID_PARAMETER;\r | |
2537 | }\r | |
2538 | \r | |
2539 | if ((*DataToggle != 1) && (*DataToggle != 0)) {\r | |
2540 | return EFI_INVALID_PARAMETER;\r | |
2541 | }\r | |
2542 | \r | |
2543 | if (MaximumPacketLength != 8 &&\r | |
2544 | MaximumPacketLength != 16 &&\r | |
2545 | MaximumPacketLength != 32 &&\r | |
2546 | MaximumPacketLength != 64) {\r | |
2547 | return EFI_INVALID_PARAMETER;\r | |
2548 | }\r | |
2549 | \r | |
2550 | //\r | |
2551 | // Enable the maximum packet size (64bytes)\r | |
2552 | // that can be used for full speed bandwidth reclamation\r | |
2553 | // at the end of a frame.\r | |
2554 | //\r | |
2555 | EnableMaxPacketSize (HcDev);\r | |
2556 | \r | |
2557 | Status = ClearStatusReg (HcDev->PciIo, StatusReg);\r | |
2558 | if (EFI_ERROR (Status)) {\r | |
2559 | return EFI_DEVICE_ERROR;\r | |
2560 | }\r | |
2561 | \r | |
2562 | //\r | |
2563 | // construct QH and TD data structures,\r | |
2564 | // and link them together\r | |
2565 | //\r | |
2566 | if (EndPointAddress & 0x80) {\r | |
2567 | TransferDirection = EfiUsbDataIn;\r | |
2568 | } else {\r | |
2569 | TransferDirection = EfiUsbDataOut;\r | |
2570 | }\r | |
2571 | \r | |
2572 | switch (TransferDirection) {\r | |
2573 | \r | |
2574 | case EfiUsbDataIn:\r | |
2575 | ShortPacketEnable = TRUE;\r | |
2576 | PktID = INPUT_PACKET_ID;\r | |
2577 | PtrDataSource = Data;\r | |
2578 | DataLen = *DataLength;\r | |
2579 | \r | |
2580 | //\r | |
2581 | // BusMasterWrite means cpu read\r | |
2582 | //\r | |
2583 | Status = HcDev->PciIo->Map (\r | |
562d2849 | 2584 | HcDev->PciIo,\r |
2585 | EfiPciIoOperationBusMasterWrite,\r | |
2586 | PtrDataSource,\r | |
2587 | &DataLen,\r | |
2588 | &TempPtr,\r | |
2589 | &Mapping\r | |
2590 | );\r | |
878ddf1f | 2591 | if (EFI_ERROR (Status)) {\r |
2592 | return Status;\r | |
2593 | }\r | |
2594 | \r | |
2595 | Ptr = (UINT8 *) ((UINTN) TempPtr);\r | |
2596 | break;\r | |
2597 | \r | |
2598 | case EfiUsbDataOut:\r | |
2599 | PktID = OUTPUT_PACKET_ID;\r | |
2600 | PtrDataSource = Data;\r | |
2601 | DataLen = *DataLength;\r | |
2602 | \r | |
2603 | //\r | |
2604 | // BusMasterRead means cpu write\r | |
2605 | //\r | |
2606 | Status = HcDev->PciIo->Map (\r | |
562d2849 | 2607 | HcDev->PciIo,\r |
2608 | EfiPciIoOperationBusMasterRead,\r | |
2609 | PtrDataSource,\r | |
2610 | &DataLen,\r | |
2611 | &TempPtr,\r | |
2612 | &Mapping\r | |
2613 | );\r | |
878ddf1f | 2614 | if (EFI_ERROR (Status)) {\r |
2615 | return Status;\r | |
2616 | }\r | |
2617 | \r | |
2618 | Ptr = (UINT8 *) ((UINTN) TempPtr);\r | |
2619 | break;\r | |
2620 | \r | |
2621 | default:\r | |
2622 | return EFI_INVALID_PARAMETER;\r | |
2623 | }\r | |
2624 | \r | |
2625 | //\r | |
2626 | // create QH structure and init\r | |
2627 | //\r | |
2628 | Status = CreateQH (HcDev, &PtrQH);\r | |
2629 | if (EFI_ERROR (Status)) {\r | |
2630 | HcDev->PciIo->Unmap (HcDev->PciIo, Mapping);\r | |
2631 | return Status;\r | |
2632 | }\r | |
2633 | \r | |
2634 | //\r | |
2635 | // i is used to calculate the total number of TDs.\r | |
2636 | //\r | |
2637 | Index = 0;\r | |
2638 | \r | |
2639 | IsFirstTD = TRUE;\r | |
2640 | while (DataLen > 0) {\r | |
2641 | \r | |
2642 | //\r | |
2643 | // create TD structures and link together\r | |
2644 | //\r | |
2645 | \r | |
2646 | PktSize = (UINT8) DataLen;\r | |
2647 | if (DataLen > MaximumPacketLength) {\r | |
2648 | PktSize = MaximumPacketLength;\r | |
2649 | }\r | |
2650 | \r | |
2651 | Status = GenDataTD (\r | |
562d2849 | 2652 | HcDev,\r |
2653 | DeviceAddress,\r | |
2654 | EndPointAddress,\r | |
2655 | Ptr,\r | |
2656 | PktSize,\r | |
2657 | PktID,\r | |
2658 | *DataToggle,\r | |
2659 | FALSE,\r | |
2660 | &PtrTD\r | |
2661 | );\r | |
878ddf1f | 2662 | \r |
2663 | if (EFI_ERROR (Status)) {\r | |
2664 | HcDev->PciIo->Unmap (HcDev->PciIo, Mapping);\r | |
2665 | UhciFreePool (HcDev, (UINT8 *) PtrQH, sizeof (QH_STRUCT));\r | |
2666 | DeleteQueuedTDs (HcDev, PtrFirstTD);\r | |
2667 | return Status;\r | |
2668 | }\r | |
2669 | \r | |
2670 | //\r | |
2671 | // Enable short packet detection.\r | |
2672 | // (default action is disabling short packet detection)\r | |
2673 | //\r | |
2674 | if (ShortPacketEnable) {\r | |
2675 | EnableorDisableTDShortPacket (PtrTD, TRUE);\r | |
2676 | }\r | |
2677 | \r | |
2678 | if (IsFirstTD) {\r | |
2679 | PtrFirstTD = PtrTD;\r | |
2680 | PtrFirstTD->ptrNextTD = NULL;\r | |
2681 | IsFirstTD = FALSE;\r | |
2682 | } else {\r | |
2683 | //\r | |
2684 | // Link two TDs in vertical depth\r | |
2685 | //\r | |
2686 | LinkTDToTD (PtrPreTD, PtrTD);\r | |
2687 | }\r | |
2688 | \r | |
2689 | Index++;\r | |
2690 | \r | |
2691 | PtrPreTD = PtrTD;\r | |
2692 | \r | |
2693 | *DataToggle ^= 1;\r | |
2694 | Ptr += PktSize;\r | |
2695 | DataLen -= PktSize;\r | |
2696 | }\r | |
2697 | \r | |
2698 | //\r | |
2699 | // link TD structures to QH structure\r | |
2700 | //\r | |
2701 | LinkTDToQH (PtrQH, PtrFirstTD);\r | |
2702 | \r | |
2703 | //\r | |
2704 | // calculate how many entries are linked to the specified bulk transfer QH-TDs\r | |
2705 | // the below values are referred to the USB spec revision1.1.\r | |
2706 | //\r | |
2707 | switch (MaximumPacketLength) {\r | |
2708 | case 8:\r | |
2709 | LinkTimes = Index / 71 + 1;\r | |
2710 | break;\r | |
2711 | \r | |
2712 | case 16:\r | |
2713 | LinkTimes = Index / 51 + 1;\r | |
2714 | break;\r | |
2715 | \r | |
2716 | case 32:\r | |
2717 | LinkTimes = Index / 33 + 1;\r | |
2718 | break;\r | |
2719 | \r | |
2720 | case 64:\r | |
2721 | LinkTimes = Index / 19 + 1;\r | |
2722 | break;\r | |
2723 | }\r | |
2724 | \r | |
2725 | LinkTimes += 500;\r | |
2726 | \r | |
2727 | //\r | |
2728 | // put QH-TDs into Frame list\r | |
2729 | //\r | |
2730 | LoadFrameListIndex = (UINT16) ((GetCurrentFrameNumber (HcDev->PciIo, FrameNumReg)) & 0x3FF);\r | |
2731 | SavedFrameListIndex = LoadFrameListIndex;\r | |
2732 | \r | |
2733 | for (Index = 0; Index <= LinkTimes; Index++) {\r | |
2734 | \r | |
2735 | //\r | |
2736 | // put the QH-TD directly or indirectly into the proper place\r | |
2737 | // in the Frame List\r | |
2738 | //\r | |
2739 | LinkQHToFrameList (HcDev->FrameListEntry, LoadFrameListIndex, PtrQH);\r | |
2740 | \r | |
2741 | LoadFrameListIndex += 1;\r | |
2742 | LoadFrameListIndex &= 0x3FF;\r | |
2743 | }\r | |
2744 | \r | |
2745 | LoadFrameListIndex = SavedFrameListIndex;\r | |
2746 | \r | |
2747 | //\r | |
2748 | // Execute QH-TD and get result\r | |
2749 | //\r | |
2750 | //\r | |
2751 | // detail status is put into the Result field in the pIRP\r | |
2752 | // the Data Toggle value is also re-updated to the value\r | |
2753 | // of the last successful TD\r | |
2754 | //\r | |
2755 | Status = ExecBulkorSyncInterruptTransfer (\r | |
562d2849 | 2756 | HcDev,\r |
2757 | PtrFirstTD,\r | |
2758 | LoadFrameListIndex,\r | |
2759 | DataLength,\r | |
2760 | DataToggle,\r | |
2761 | TimeOut,\r | |
2762 | TransferResult\r | |
2763 | );\r | |
878ddf1f | 2764 | \r |
2765 | //\r | |
2766 | // Delete Bulk transfer QH-TD structure\r | |
2767 | // and maitain the pointers in the Frame List\r | |
2768 | // and other pointers in related QH structure\r | |
2769 | //\r | |
2770 | // TRUE means must search other framelistindex\r | |
2771 | //\r | |
2772 | for (Index = 0; Index <= LinkTimes; Index++) {\r | |
2773 | DelLinkSingleQH (\r | |
2774 | HcDev,\r | |
2775 | PtrQH,\r | |
2776 | LoadFrameListIndex,\r | |
2777 | FALSE,\r | |
2778 | FALSE\r | |
2779 | );\r | |
2780 | LoadFrameListIndex += 1;\r | |
2781 | LoadFrameListIndex &= 0x3FF;\r | |
2782 | }\r | |
2783 | \r | |
2784 | UhciFreePool (HcDev, (UINT8 *) PtrQH, sizeof (QH_STRUCT));\r | |
2785 | \r | |
2786 | DeleteQueuedTDs (HcDev, PtrFirstTD);\r | |
2787 | \r | |
2788 | if (Mapping != NULL) {\r | |
2789 | HcDev->PciIo->Unmap (HcDev->PciIo, Mapping);\r | |
2790 | }\r | |
2791 | \r | |
2792 | //\r | |
2793 | // if has errors that cause host controller halt,\r | |
2794 | // then return EFI_DEVICE_ERROR directly.\r | |
2795 | //\r | |
2796 | if (!IsStatusOK (HcDev->PciIo, StatusReg)) {\r | |
2797 | \r | |
2798 | ClearStatusReg (HcDev->PciIo, StatusReg);\r | |
2799 | *TransferResult |= EFI_USB_ERR_SYSTEM;\r | |
2800 | return EFI_DEVICE_ERROR;\r | |
2801 | }\r | |
2802 | \r | |
2803 | ClearStatusReg (HcDev->PciIo, StatusReg);\r | |
2804 | \r | |
2805 | HcDev->PciIo->Flush (HcDev->PciIo);\r | |
2806 | \r | |
2807 | return Status;\r | |
2808 | }\r | |
2809 | \r | |
2810 | EFI_STATUS\r | |
2811 | EFIAPI\r | |
2812 | UHCIAsyncInterruptTransfer (\r | |
2813 | IN EFI_USB_HC_PROTOCOL * This,\r | |
2814 | IN UINT8 DeviceAddress,\r | |
2815 | IN UINT8 EndPointAddress,\r | |
2816 | IN BOOLEAN IsSlowDevice,\r | |
562d2849 | 2817 | IN UINT8 MaximumPacketLength,\r |
878ddf1f | 2818 | IN BOOLEAN IsNewTransfer,\r |
2819 | IN OUT UINT8 *DataToggle,\r | |
2820 | IN UINTN PollingInterval, OPTIONAL\r | |
2821 | IN UINTN DataLength, OPTIONAL\r | |
2822 | IN EFI_ASYNC_USB_TRANSFER_CALLBACK CallBackFunction, OPTIONAL\r | |
2823 | IN VOID *Context OPTIONAL\r | |
2824 | )\r | |
2825 | /*++\r | |
2826 | \r | |
2827 | Routine Description:\r | |
2828 | Submits an asynchronous interrupt transfer to an \r | |
2829 | interrupt endpoint of a USB device.\r | |
2830 | \r | |
2831 | Arguments:\r | |
2832 | \r | |
2833 | This A pointer to the EFI_USB_HC_PROTOCOL instance.\r | |
2834 | \r | |
2835 | DeviceAddress Represents the address of the target device on the USB,\r | |
2836 | which is assigned during USB enumeration.\r | |
2837 | \r | |
2838 | EndPointAddress The combination of an endpoint number and an endpoint \r | |
2839 | direction of the target USB device. Each endpoint address \r | |
2840 | supports data transfer in one direction except the \r | |
2841 | control endpoint (whose default endpoint address is 0). \r | |
2842 | It is the caller's responsibility to make sure that \r | |
2843 | the EndPointAddress represents an interrupt endpoint.\r | |
2844 | \r | |
2845 | IsSlowDevice Indicates whether the target device is slow device \r | |
2846 | or full-speed device.\r | |
2847 | \r | |
562d2849 | 2848 | MaximumPacketLength Indicates the maximum packet size the target endpoint\r |
878ddf1f | 2849 | is capable of sending or receiving.\r |
2850 | \r | |
2851 | IsNewTransfer If TRUE, an asynchronous interrupt pipe is built between\r | |
2852 | the host and the target interrupt endpoint. \r | |
2853 | If FALSE, the specified asynchronous interrupt pipe \r | |
2854 | is canceled.\r | |
2855 | \r | |
2856 | DataToggle A pointer to the data toggle value. On input, it is valid \r | |
2857 | when IsNewTransfer is TRUE, and it indicates the initial \r | |
2858 | data toggle value the asynchronous interrupt transfer \r | |
2859 | should adopt. \r | |
2860 | On output, it is valid when IsNewTransfer is FALSE, \r | |
2861 | and it is updated to indicate the data toggle value of \r | |
2862 | the subsequent asynchronous interrupt transfer.\r | |
2863 | \r | |
2864 | PollingInterval Indicates the interval, in milliseconds, that the \r | |
2865 | asynchronous interrupt transfer is polled. \r | |
2866 | This parameter is required when IsNewTransfer is TRUE.\r | |
2867 | \r | |
2868 | DataLength Indicates the length of data to be received at the \r | |
2869 | rate specified by PollingInterval from the target \r | |
2870 | asynchronous interrupt endpoint. This parameter \r | |
2871 | is only required when IsNewTransfer is TRUE.\r | |
2872 | \r | |
2873 | CallBackFunction The Callback function.This function is called at the \r | |
2874 | rate specified by PollingInterval.This parameter is \r | |
2875 | only required when IsNewTransfer is TRUE.\r | |
2876 | \r | |
2877 | Context The context that is passed to the CallBackFunction.\r | |
2878 | This is an optional parameter and may be NULL.\r | |
2879 | \r | |
2880 | Returns:\r | |
2881 | EFI_SUCCESS \r | |
2882 | The asynchronous interrupt transfer request has been successfully \r | |
2883 | submitted or canceled.\r | |
2884 | EFI_INVALID_PARAMETER \r | |
2885 | Some parameters are invalid.\r | |
2886 | EFI_OUT_OF_RESOURCES \r | |
2887 | The request could not be completed due to a lack of resources. \r | |
2888 | EFI_DEVICE_ERROR\r | |
2889 | Can't read register\r | |
2890 | --*/\r | |
2891 | {\r | |
2892 | USB_HC_DEV *HcDev;\r | |
2893 | UINT32 StatusReg;\r | |
2894 | UINT32 FrameNumReg;\r | |
2895 | UINTN DataLen;\r | |
2896 | QH_STRUCT *ptrFirstQH;\r | |
2897 | QH_STRUCT *PtrQH;\r | |
2898 | QH_STRUCT *ptrPreQH;\r | |
2899 | TD_STRUCT *PtrFirstTD;\r | |
2900 | TD_STRUCT *PtrTD;\r | |
2901 | TD_STRUCT *PtrPreTD;\r | |
2902 | UINT16 LoadFrameListIndex;\r | |
2903 | UINT16 Index;\r | |
2904 | UINT8 PktID;\r | |
2905 | UINT8 *Ptr;\r | |
2906 | UINT8 *MappedPtr;\r | |
2907 | BOOLEAN IsFirstTD;\r | |
2908 | BOOLEAN IsFirstQH;\r | |
2909 | EFI_STATUS Status;\r | |
2910 | BOOLEAN ShortPacketEnable;\r | |
2911 | UINT8 CurrentDataToggle;\r | |
2912 | EFI_PHYSICAL_ADDRESS TempPtr;\r | |
2913 | VOID *Mapping;\r | |
2914 | UINT8 PktSize;\r | |
2915 | QH_STRUCT *TempQH;\r | |
2916 | EFI_TPL OldTpl;\r | |
2917 | \r | |
2918 | HcDev = USB_HC_DEV_FROM_THIS (This);\r | |
2919 | StatusReg = (UINT32) (USBSTS);\r | |
2920 | FrameNumReg = (UINT32) (USBFRNUM);\r | |
2921 | Mapping = NULL;\r | |
2922 | ShortPacketEnable = FALSE;\r | |
2923 | \r | |
2924 | PktID = INPUT_PACKET_ID;\r | |
2925 | PtrTD = NULL;\r | |
2926 | PtrFirstTD = NULL;\r | |
2927 | PtrPreTD = NULL;\r | |
2928 | Ptr = NULL;\r | |
2929 | PtrQH = NULL;\r | |
2930 | ptrPreQH = NULL;\r | |
2931 | ptrFirstQH = NULL;\r | |
2932 | \r | |
2933 | if ((EndPointAddress & 0x80) == 0) {\r | |
2934 | return EFI_INVALID_PARAMETER;\r | |
2935 | }\r | |
2936 | \r | |
2937 | //\r | |
2938 | // delete Async interrupt transfer request\r | |
2939 | //\r | |
2940 | if (!IsNewTransfer) {\r | |
2941 | \r | |
2942 | OldTpl = gBS->RaiseTPL (EFI_TPL_NOTIFY);\r | |
2943 | \r | |
2944 | Status = DeleteAsyncINTQHTDs (\r | |
562d2849 | 2945 | HcDev,\r |
2946 | DeviceAddress,\r | |
2947 | EndPointAddress,\r | |
2948 | DataToggle\r | |
2949 | );\r | |
878ddf1f | 2950 | \r |
2951 | gBS->RestoreTPL (OldTpl);\r | |
2952 | \r | |
2953 | return Status;\r | |
2954 | }\r | |
2955 | //\r | |
2956 | // if has errors that cause host controller halt,\r | |
2957 | // then return EFI_DEVICE_ERROR directly.\r | |
2958 | //\r | |
2959 | if (!IsStatusOK (HcDev->PciIo, StatusReg)) {\r | |
2960 | \r | |
2961 | ClearStatusReg (HcDev->PciIo, StatusReg);\r | |
2962 | return EFI_DEVICE_ERROR;\r | |
2963 | }\r | |
2964 | \r | |
2965 | ClearStatusReg (HcDev->PciIo, StatusReg);\r | |
2966 | \r | |
2967 | //\r | |
2968 | // submit Async interrupt transfer request\r | |
2969 | //\r | |
2970 | if (PollingInterval < 1 || PollingInterval > 255) {\r | |
2971 | return EFI_INVALID_PARAMETER;\r | |
2972 | }\r | |
2973 | \r | |
2974 | if (DataLength == 0) {\r | |
2975 | return EFI_INVALID_PARAMETER;\r | |
2976 | }\r | |
2977 | \r | |
2978 | if ((*DataToggle != 1) && (*DataToggle != 0)) {\r | |
2979 | return EFI_INVALID_PARAMETER;\r | |
2980 | }\r | |
2981 | \r | |
2982 | ShortPacketEnable = TRUE;\r | |
2983 | PktID = INPUT_PACKET_ID;\r | |
2984 | DataLen = DataLength;\r | |
2985 | Ptr = AllocatePool (DataLen);\r | |
2986 | if (Ptr == NULL) {\r | |
2987 | return EFI_OUT_OF_RESOURCES;\r | |
2988 | }\r | |
2989 | \r | |
2990 | //\r | |
2991 | // BusMasterWrite means cpu read\r | |
2992 | //\r | |
2993 | Status = HcDev->PciIo->Map (\r | |
562d2849 | 2994 | HcDev->PciIo,\r |
2995 | EfiPciIoOperationBusMasterWrite,\r | |
2996 | Ptr,\r | |
2997 | &DataLen,\r | |
2998 | &TempPtr,\r | |
2999 | &Mapping\r | |
3000 | );\r | |
878ddf1f | 3001 | if (EFI_ERROR (Status)) {\r |
3002 | gBS->FreePool (Ptr);\r | |
3003 | return Status;\r | |
3004 | }\r | |
3005 | \r | |
3006 | MappedPtr = (UINT8 *) ((UINTN) TempPtr);\r | |
3007 | \r | |
3008 | CurrentDataToggle = *DataToggle;\r | |
3009 | \r | |
3010 | IsFirstTD = TRUE;\r | |
3011 | \r | |
3012 | while (DataLen > 0) {\r | |
3013 | //\r | |
3014 | // create TD structures and link together\r | |
3015 | //\r | |
3016 | \r | |
3017 | PktSize = (UINT8) DataLen;\r | |
562d2849 | 3018 | if (DataLen > MaximumPacketLength) {\r |
3019 | PktSize = MaximumPacketLength;\r | |
878ddf1f | 3020 | }\r |
3021 | \r | |
3022 | Status = GenDataTD (\r | |
562d2849 | 3023 | HcDev,\r |
3024 | DeviceAddress,\r | |
3025 | EndPointAddress,\r | |
3026 | MappedPtr,\r | |
3027 | PktSize,\r | |
3028 | PktID,\r | |
3029 | CurrentDataToggle,\r | |
3030 | IsSlowDevice,\r | |
3031 | &PtrTD\r | |
3032 | );\r | |
3033 | if (EFI_ERROR (Status)) {\r | |
3034 | gBS->FreePool (Ptr);\r | |
878ddf1f | 3035 | HcDev->PciIo->Unmap (HcDev->PciIo, Mapping);\r |
3036 | DeleteQueuedTDs (HcDev, PtrFirstTD);\r | |
3037 | return Status;\r | |
3038 | }\r | |
3039 | //\r | |
3040 | // Enable short packet detection.\r | |
3041 | //\r | |
3042 | if (ShortPacketEnable) {\r | |
3043 | EnableorDisableTDShortPacket (PtrTD, TRUE);\r | |
3044 | }\r | |
3045 | \r | |
3046 | if (IsFirstTD) {\r | |
3047 | PtrFirstTD = PtrTD;\r | |
3048 | PtrFirstTD->ptrNextTD = NULL;\r | |
3049 | IsFirstTD = FALSE;\r | |
3050 | } else {\r | |
3051 | //\r | |
3052 | // Link two TDs in vertical depth\r | |
3053 | //\r | |
3054 | LinkTDToTD (PtrPreTD, PtrTD);\r | |
3055 | }\r | |
3056 | \r | |
3057 | PtrPreTD = PtrTD;\r | |
3058 | \r | |
3059 | CurrentDataToggle ^= 1;\r | |
3060 | MappedPtr += PktSize;\r | |
3061 | DataLen -= PktSize;\r | |
3062 | }\r | |
3063 | \r | |
3064 | //\r | |
3065 | // roll one value back\r | |
3066 | //\r | |
3067 | CurrentDataToggle ^= 1;\r | |
3068 | \r | |
3069 | //\r | |
3070 | // create a list of QH structures and init,\r | |
3071 | // link TDs to all the QHs, and link all the QHs together using internal\r | |
3072 | // defined pointer of the QH_STRUCT.\r | |
3073 | //\r | |
3074 | IsFirstQH = TRUE;\r | |
3075 | ptrPreQH = NULL;\r | |
3076 | for (Index = 0; Index < 1024;) {\r | |
3077 | \r | |
3078 | Status = CreateQH (HcDev, &PtrQH);\r | |
3079 | if (EFI_ERROR (Status)) {\r | |
3080 | gBS->FreePool (Ptr);\r | |
3081 | HcDev->PciIo->Unmap (HcDev->PciIo, Mapping);\r | |
3082 | DeleteQueuedTDs (HcDev, PtrFirstTD);\r | |
3083 | PtrQH = ptrFirstQH;\r | |
3084 | while (PtrQH) {\r | |
3085 | TempQH = PtrQH;\r | |
3086 | PtrQH = TempQH->ptrNextIntQH;\r | |
3087 | UhciFreePool (HcDev, (UINT8 *) TempQH, sizeof (QH_STRUCT));\r | |
3088 | }\r | |
3089 | \r | |
3090 | return Status;\r | |
3091 | }\r | |
3092 | \r | |
3093 | //\r | |
3094 | // link TD structures to QH structure\r | |
3095 | //\r | |
3096 | LinkTDToQH (PtrQH, PtrFirstTD);\r | |
3097 | \r | |
3098 | if (IsFirstQH) {\r | |
3099 | ptrFirstQH = PtrQH;\r | |
3100 | ptrFirstQH->ptrNextIntQH = NULL;\r | |
3101 | IsFirstQH = FALSE;\r | |
3102 | } else {\r | |
3103 | //\r | |
3104 | // link neighbor QH structures together\r | |
3105 | //\r | |
3106 | ptrPreQH->ptrNextIntQH = PtrQH;\r | |
3107 | }\r | |
3108 | \r | |
3109 | ptrPreQH = PtrQH;\r | |
3110 | \r | |
3111 | Index = (UINT16) (PollingInterval + Index);\r | |
3112 | }\r | |
3113 | //\r | |
3114 | // last QH in QH list should set its next QH pointer to NULL.\r | |
3115 | //\r | |
3116 | PtrQH->ptrNextIntQH = NULL;\r | |
3117 | \r | |
3118 | //\r | |
3119 | // Save QH-TD structures in Interrupt transfer list,\r | |
3120 | // for monitor interrupt transfer execution routine use.\r | |
3121 | //\r | |
3122 | InsertQHTDToINTList (\r | |
3123 | HcDev,\r | |
3124 | ptrFirstQH,\r | |
3125 | PtrFirstTD,\r | |
3126 | DeviceAddress,\r | |
3127 | EndPointAddress,\r | |
3128 | CurrentDataToggle,\r | |
3129 | DataLength,\r | |
3130 | PollingInterval,\r | |
3131 | Mapping,\r | |
3132 | Ptr,\r | |
3133 | CallBackFunction,\r | |
3134 | Context\r | |
3135 | );\r | |
3136 | \r | |
3137 | //\r | |
3138 | // put QHs-TDs into Frame list\r | |
3139 | //\r | |
3140 | LoadFrameListIndex = (UINT16) ((GetCurrentFrameNumber (HcDev->PciIo, FrameNumReg)) & 0x3FF);\r | |
3141 | \r | |
3142 | PtrQH = ptrFirstQH;\r | |
3143 | \r | |
3144 | for (Index = LoadFrameListIndex; Index < (1024 + LoadFrameListIndex);) {\r | |
3145 | \r | |
3146 | //\r | |
3147 | // put the QH-TD directly or indirectly into the proper place\r | |
3148 | // in the Frame List\r | |
3149 | //\r | |
3150 | LinkQHToFrameList (HcDev->FrameListEntry, (UINT16) (Index & 0x3FF), PtrQH);\r | |
3151 | \r | |
3152 | Index = (UINT16) (PollingInterval + Index);\r | |
3153 | \r | |
3154 | PtrQH = PtrQH->ptrNextIntQH;\r | |
3155 | }\r | |
3156 | \r | |
3157 | HcDev->PciIo->Flush (HcDev->PciIo);\r | |
3158 | \r | |
3159 | return EFI_SUCCESS;\r | |
3160 | }\r | |
3161 | \r | |
3162 | EFI_STATUS\r | |
3163 | EFIAPI\r | |
3164 | UHCISyncInterruptTransfer (\r | |
3165 | IN EFI_USB_HC_PROTOCOL *This,\r | |
3166 | IN UINT8 DeviceAddress,\r | |
3167 | IN UINT8 EndPointAddress,\r | |
3168 | IN BOOLEAN IsSlowDevice,\r | |
3169 | IN UINT8 MaximumPacketLength,\r | |
3170 | IN OUT VOID *Data,\r | |
3171 | IN OUT UINTN *DataLength,\r | |
3172 | IN OUT UINT8 *DataToggle,\r | |
3173 | IN UINTN TimeOut,\r | |
3174 | OUT UINT32 *TransferResult\r | |
3175 | )\r | |
3176 | /*++\r | |
3177 | \r | |
3178 | Routine Description:\r | |
3179 | Submits synchronous interrupt transfer to an interrupt endpoint \r | |
3180 | of a USB device.\r | |
3181 | \r | |
3182 | Arguments:\r | |
3183 | \r | |
3184 | This A pointer to the EFI_USB_HC_PROTOCOL instance.\r | |
3185 | \r | |
3186 | DeviceAddress Represents the address of the target device on the USB, \r | |
3187 | which is assigned during USB enumeration.\r | |
3188 | \r | |
3189 | EndPointAddress The combination of an endpoint number and an endpoint \r | |
3190 | direction of the target USB device. Each endpoint \r | |
3191 | address supports data transfer in one direction \r | |
3192 | except the control endpoint (whose default \r | |
3193 | endpoint address is 0). It is the caller's responsibility\r | |
3194 | to make sure that the EndPointAddress represents \r | |
3195 | an interrupt endpoint. \r | |
3196 | \r | |
3197 | IsSlowDevice Indicates whether the target device is slow device \r | |
3198 | or full-speed device.\r | |
3199 | \r | |
3200 | MaximumPacketLength Indicates the maximum packet size the target endpoint \r | |
3201 | is capable of sending or receiving.\r | |
3202 | \r | |
3203 | Data A pointer to the buffer of data that will be transmitted \r | |
3204 | to USB device or received from USB device.\r | |
3205 | \r | |
3206 | DataLength On input, the size, in bytes, of the data buffer specified \r | |
3207 | by Data. On output, the number of bytes transferred.\r | |
3208 | \r | |
3209 | DataToggle A pointer to the data toggle value. On input, it indicates\r | |
3210 | the initial data toggle value the synchronous interrupt \r | |
3211 | transfer should adopt; \r | |
3212 | on output, it is updated to indicate the data toggle value \r | |
3213 | of the subsequent synchronous interrupt transfer. \r | |
3214 | \r | |
3215 | TimeOut Indicates the maximum time, in microseconds, which the \r | |
3216 | transfer is allowed to complete.\r | |
3217 | \r | |
3218 | TransferResult A pointer to the detailed result information from \r | |
3219 | the synchronous interrupt transfer. \r | |
3220 | \r | |
3221 | Returns:\r | |
3222 | EFI_SUCCESS \r | |
3223 | The synchronous interrupt transfer was completed successfully.\r | |
3224 | EFI_OUT_OF_RESOURCES \r | |
3225 | The synchronous interrupt transfer could not be submitted due \r | |
3226 | to lack of resource.\r | |
3227 | EFI_INVALID_PARAMETER \r | |
3228 | Some parameters are invalid.\r | |
3229 | EFI_TIMEOUT \r | |
3230 | The synchronous interrupt transfer failed due to timeout.\r | |
3231 | EFI_DEVICE_ERROR \r | |
3232 | The synchronous interrupt transfer failed due to host controller \r | |
3233 | or device error. Caller should check TranferResult for detailed \r | |
3234 | error information. \r | |
3235 | --*/\r | |
3236 | {\r | |
3237 | USB_HC_DEV *HcDev;\r | |
3238 | UINT32 StatusReg;\r | |
3239 | UINT32 FrameNumReg;\r | |
3240 | UINTN DataLen;\r | |
3241 | QH_STRUCT *PtrQH;\r | |
3242 | TD_STRUCT *PtrFirstTD;\r | |
3243 | TD_STRUCT *PtrTD;\r | |
3244 | TD_STRUCT *PtrPreTD;\r | |
3245 | UINT16 LoadFrameListIndex;\r | |
3246 | UINT16 SavedFrameListIndex;\r | |
3247 | UINT32 Index;\r | |
3248 | UINT32 LinkTimes;\r | |
3249 | UINT8 PktID;\r | |
3250 | UINT8 *PtrDataSource;\r | |
3251 | UINT8 *Ptr;\r | |
3252 | BOOLEAN IsFirstTD;\r | |
3253 | EFI_STATUS Status;\r | |
3254 | BOOLEAN ShortPacketEnable;\r | |
3255 | EFI_PHYSICAL_ADDRESS TempPtr;\r | |
3256 | VOID *Mapping;\r | |
3257 | UINT8 PktSize;\r | |
3258 | \r | |
3259 | HcDev = USB_HC_DEV_FROM_THIS (This);\r | |
3260 | StatusReg = (UINT32) (USBSTS);\r | |
3261 | FrameNumReg = (UINT32) (USBFRNUM);\r | |
3262 | ShortPacketEnable = FALSE;\r | |
3263 | Mapping = NULL;\r | |
3264 | PktID = INPUT_PACKET_ID;\r | |
3265 | PtrTD = NULL;\r | |
3266 | PtrFirstTD = NULL;\r | |
3267 | PtrPreTD = NULL;\r | |
3268 | DataLen = 0;\r | |
3269 | Ptr = NULL;\r | |
3270 | Index = 0;\r | |
3271 | LinkTimes = 0;\r | |
3272 | \r | |
3273 | //\r | |
3274 | // Parameters Checking\r | |
3275 | //\r | |
3276 | \r | |
3277 | if ((DataLength == NULL) ||\r | |
3278 | (Data == NULL) ||\r | |
3279 | (TransferResult == NULL)) {\r | |
3280 | return EFI_INVALID_PARAMETER;\r | |
3281 | }\r | |
3282 | \r | |
3283 | //\r | |
3284 | // if has errors that cause host controller halt,\r | |
3285 | // then return EFI_DEVICE_ERROR directly.\r | |
3286 | //\r | |
3287 | if (!IsStatusOK (HcDev->PciIo, StatusReg)) {\r | |
3288 | \r | |
3289 | ClearStatusReg (HcDev->PciIo, StatusReg);\r | |
3290 | *TransferResult = EFI_USB_ERR_SYSTEM;\r | |
3291 | return EFI_DEVICE_ERROR;\r | |
3292 | }\r | |
3293 | \r | |
3294 | if ((EndPointAddress & 0x80) == 0) {\r | |
3295 | return EFI_INVALID_PARAMETER;\r | |
3296 | }\r | |
3297 | \r | |
3298 | if (*DataLength == 0) {\r | |
3299 | return EFI_INVALID_PARAMETER;\r | |
3300 | }\r | |
3301 | \r | |
3302 | if ((*DataToggle != 1) && (*DataToggle != 0)) {\r | |
3303 | return EFI_INVALID_PARAMETER;\r | |
3304 | }\r | |
3305 | \r | |
3306 | if (MaximumPacketLength > 64) {\r | |
3307 | return EFI_INVALID_PARAMETER;\r | |
3308 | }\r | |
3309 | \r | |
3310 | if (IsSlowDevice && (MaximumPacketLength > 8)) {\r | |
3311 | return EFI_INVALID_PARAMETER;\r | |
3312 | }\r | |
3313 | \r | |
562d2849 | 3314 | if (TransferResult == NULL) {\r |
3315 | return EFI_INVALID_PARAMETER;\r | |
3316 | }\r | |
3317 | \r | |
878ddf1f | 3318 | ClearStatusReg (HcDev->PciIo, StatusReg);\r |
3319 | \r | |
3320 | //\r | |
3321 | // submit Sync interrupt transfer request\r | |
3322 | //\r | |
3323 | ShortPacketEnable = TRUE;\r | |
3324 | PktID = INPUT_PACKET_ID;\r | |
3325 | DataLen = *DataLength;\r | |
3326 | PtrDataSource = Data;\r | |
3327 | \r | |
3328 | //\r | |
3329 | // create QH structure and init\r | |
3330 | //\r | |
3331 | Status = CreateQH (HcDev, &PtrQH);\r | |
3332 | if (EFI_ERROR (Status)) {\r | |
3333 | return Status;\r | |
3334 | }\r | |
3335 | \r | |
3336 | //\r | |
3337 | // BusMasterWrite means cpu read\r | |
3338 | //\r | |
3339 | Status = HcDev->PciIo->Map (\r | |
3340 | HcDev->PciIo,\r | |
3341 | EfiPciIoOperationBusMasterWrite,\r | |
3342 | PtrDataSource,\r | |
3343 | &DataLen,\r | |
3344 | &TempPtr,\r | |
3345 | &Mapping\r | |
3346 | );\r | |
3347 | if (EFI_ERROR (Status)) {\r | |
3348 | UhciFreePool (HcDev, (UINT8 *) PtrQH, sizeof (QH_STRUCT));\r | |
3349 | return Status;\r | |
3350 | }\r | |
3351 | \r | |
3352 | Ptr = (UINT8 *) ((UINTN) TempPtr);\r | |
3353 | \r | |
3354 | IsFirstTD = TRUE;\r | |
3355 | while (DataLen > 0) {\r | |
3356 | //\r | |
3357 | // create TD structures and link together\r | |
3358 | //\r | |
3359 | PktSize = (UINT8) DataLen;\r | |
3360 | if (DataLen > MaximumPacketLength) {\r | |
3361 | PktSize = MaximumPacketLength;\r | |
3362 | }\r | |
3363 | \r | |
3364 | Status = GenDataTD (\r | |
3365 | HcDev,\r | |
3366 | DeviceAddress,\r | |
3367 | EndPointAddress,\r | |
3368 | Ptr,\r | |
3369 | PktSize,\r | |
3370 | PktID,\r | |
3371 | *DataToggle,\r | |
3372 | IsSlowDevice,\r | |
3373 | &PtrTD\r | |
3374 | );\r | |
3375 | if (EFI_ERROR (Status)) {\r | |
3376 | UhciFreePool (HcDev, (UINT8 *) PtrQH, sizeof (QH_STRUCT));\r | |
3377 | HcDev->PciIo->Unmap (HcDev->PciIo, Mapping);\r | |
3378 | DeleteQueuedTDs (HcDev, PtrFirstTD);\r | |
3379 | return Status;\r | |
3380 | }\r | |
3381 | //\r | |
3382 | // Enable short packet detection.\r | |
3383 | //\r | |
3384 | if (ShortPacketEnable) {\r | |
3385 | EnableorDisableTDShortPacket (PtrTD, TRUE);\r | |
3386 | }\r | |
3387 | \r | |
3388 | if (IsFirstTD) {\r | |
3389 | PtrFirstTD = PtrTD;\r | |
3390 | PtrFirstTD->ptrNextTD = NULL;\r | |
3391 | IsFirstTD = FALSE;\r | |
3392 | } else {\r | |
3393 | //\r | |
3394 | // Link two TDs in vertical depth\r | |
3395 | //\r | |
3396 | LinkTDToTD (PtrPreTD, PtrTD);\r | |
3397 | }\r | |
3398 | \r | |
3399 | Index++;\r | |
3400 | \r | |
3401 | PtrPreTD = PtrTD;\r | |
3402 | \r | |
3403 | *DataToggle ^= 1;\r | |
3404 | Ptr += PktSize;\r | |
3405 | DataLen -= PktSize;\r | |
3406 | }\r | |
3407 | \r | |
3408 | //\r | |
3409 | // link TD structures to QH structure\r | |
3410 | //\r | |
3411 | LinkTDToQH (PtrQH, PtrFirstTD);\r | |
3412 | \r | |
3413 | switch (MaximumPacketLength) {\r | |
3414 | case 8:\r | |
3415 | LinkTimes = Index / 71 + 1;\r | |
3416 | break;\r | |
3417 | \r | |
3418 | case 16:\r | |
3419 | LinkTimes = Index / 51 + 1;\r | |
3420 | break;\r | |
3421 | \r | |
3422 | case 32:\r | |
3423 | LinkTimes = Index / 33 + 1;\r | |
3424 | break;\r | |
3425 | \r | |
3426 | case 64:\r | |
3427 | LinkTimes = Index / 19 + 1;\r | |
3428 | break;\r | |
3429 | }\r | |
3430 | \r | |
3431 | LinkTimes += 100;\r | |
3432 | \r | |
3433 | LoadFrameListIndex = (UINT16) ((GetCurrentFrameNumber (HcDev->PciIo, FrameNumReg)) & 0x3FF);\r | |
3434 | SavedFrameListIndex = LoadFrameListIndex;\r | |
3435 | \r | |
3436 | for (Index = 0; Index < LinkTimes; Index++) {\r | |
3437 | \r | |
3438 | //\r | |
3439 | // put the QH-TD directly or indirectly into the proper place\r | |
3440 | // in the Frame List\r | |
3441 | //\r | |
3442 | LinkQHToFrameList (HcDev->FrameListEntry, LoadFrameListIndex, PtrQH);\r | |
3443 | \r | |
3444 | LoadFrameListIndex += 1;\r | |
3445 | LoadFrameListIndex &= 0x3FF;\r | |
3446 | }\r | |
3447 | \r | |
3448 | LoadFrameListIndex = SavedFrameListIndex;\r | |
3449 | //\r | |
3450 | // detail status is put into the Result field in the pIRP\r | |
3451 | // the Data Toggle value is also re-updated to the value\r | |
3452 | // of the last successful TD\r | |
3453 | //\r | |
3454 | Status = ExecBulkorSyncInterruptTransfer (\r | |
3455 | HcDev,\r | |
3456 | PtrFirstTD,\r | |
3457 | LoadFrameListIndex,\r | |
3458 | DataLength,\r | |
3459 | DataToggle,\r | |
3460 | TimeOut,\r | |
3461 | TransferResult\r | |
3462 | );\r | |
3463 | //\r | |
3464 | // Delete Sync Interrupt transfer QH-TD structure\r | |
3465 | // and maintain the pointers in the Frame List\r | |
3466 | // and other pointers in related QH structure\r | |
3467 | //\r | |
3468 | // TRUE means must search other framelistindex\r | |
3469 | //\r | |
3470 | for (Index = 0; Index <= LinkTimes; Index++) {\r | |
3471 | DelLinkSingleQH (\r | |
3472 | HcDev,\r | |
3473 | PtrQH,\r | |
3474 | LoadFrameListIndex,\r | |
3475 | FALSE,\r | |
3476 | FALSE\r | |
3477 | );\r | |
3478 | LoadFrameListIndex += 1;\r | |
3479 | LoadFrameListIndex &= 0x3FF;\r | |
3480 | }\r | |
3481 | \r | |
3482 | UhciFreePool (HcDev, (UINT8 *) PtrQH, sizeof (QH_STRUCT));\r | |
3483 | \r | |
3484 | DeleteQueuedTDs (HcDev, PtrFirstTD);\r | |
3485 | \r | |
3486 | HcDev->PciIo->Unmap (HcDev->PciIo, Mapping);\r | |
3487 | \r | |
3488 | //\r | |
3489 | // if has errors that cause host controller halt,\r | |
3490 | // then return EFI_DEVICE_ERROR directly.\r | |
3491 | //\r | |
3492 | if (!IsStatusOK (HcDev->PciIo, StatusReg)) {\r | |
3493 | \r | |
3494 | ClearStatusReg (HcDev->PciIo, StatusReg);\r | |
3495 | *TransferResult |= EFI_USB_ERR_SYSTEM;\r | |
3496 | return EFI_DEVICE_ERROR;\r | |
3497 | }\r | |
3498 | \r | |
3499 | ClearStatusReg (HcDev->PciIo, StatusReg);\r | |
3500 | \r | |
3501 | HcDev->PciIo->Flush (HcDev->PciIo);\r | |
3502 | \r | |
3503 | return Status;\r | |
3504 | }\r | |
3505 | \r | |
3506 | EFI_STATUS\r | |
3507 | EFIAPI\r | |
3508 | UHCIIsochronousTransfer (\r | |
3509 | IN EFI_USB_HC_PROTOCOL *This,\r | |
3510 | IN UINT8 DeviceAddress,\r | |
3511 | IN UINT8 EndPointAddress,\r | |
3512 | IN UINT8 MaximumPacketLength,\r | |
3513 | IN OUT VOID *Data,\r | |
3514 | IN UINTN DataLength,\r | |
3515 | OUT UINT32 *TransferResult\r | |
3516 | )\r | |
3517 | /*++\r | |
3518 | \r | |
3519 | Routine Description:\r | |
3520 | Submits isochronous transfer to a target USB device.\r | |
3521 | \r | |
3522 | Arguments:\r | |
3523 | \r | |
3524 | This - A pointer to the EFI_USB_HC_PROTOCOL instance.\r | |
3525 | DeviceAddress - Represents the address of the target device on the USB,\r | |
3526 | which is assigned during USB enumeration.\r | |
3527 | EndPointAddress - End point address\r | |
3528 | MaximumPacketLength - Indicates the maximum packet size that the \r | |
3529 | default control transfer endpoint is capable of \r | |
3530 | sending or receiving.\r | |
3531 | Data - A pointer to the buffer of data that will be transmitted \r | |
3532 | to USB device or received from USB device.\r | |
3533 | DataLength - Indicates the size, in bytes, of the data buffer \r | |
3534 | specified by Data.\r | |
3535 | TransferResult - A pointer to the detailed result information generated \r | |
3536 | by this control transfer. \r | |
3537 | Returns:\r | |
3538 | EFI_UNSUPPORTED \r | |
3539 | \r | |
3540 | --*/\r | |
3541 | {\r | |
3542 | return EFI_UNSUPPORTED;\r | |
3543 | }\r | |
3544 | \r | |
3545 | \r | |
3546 | EFI_STATUS\r | |
3547 | EFIAPI\r | |
3548 | UHCIAsyncIsochronousTransfer (\r | |
3549 | IN EFI_USB_HC_PROTOCOL * This,\r | |
3550 | IN UINT8 DeviceAddress,\r | |
3551 | IN UINT8 EndPointAddress,\r | |
3552 | IN UINT8 MaximumPacketLength,\r | |
3553 | IN OUT VOID *Data,\r | |
3554 | IN UINTN DataLength,\r | |
3555 | IN EFI_ASYNC_USB_TRANSFER_CALLBACK IsochronousCallBack,\r | |
3556 | IN VOID *Context OPTIONAL\r | |
3557 | )\r | |
3558 | /*++\r | |
3559 | \r | |
3560 | Routine Description:\r | |
3561 | Submits Async isochronous transfer to a target USB device.\r | |
3562 | \r | |
3563 | Arguments:\r | |
3564 | \r | |
3565 | This - A pointer to the EFI_USB_HC_PROTOCOL instance.\r | |
3566 | \r | |
3567 | DeviceAddress - Represents the address of the target device on the USB,\r | |
3568 | which is assigned during USB enumeration.\r | |
3569 | \r | |
3570 | EndPointAddress - End point address\r | |
3571 | \r | |
3572 | MaximumPacketLength - Indicates the maximum packet size that the \r | |
3573 | default control transfer endpoint is capable of \r | |
3574 | sending or receiving.\r | |
3575 | \r | |
3576 | Data - A pointer to the buffer of data that will be transmitted \r | |
3577 | to USB device or received from USB device.\r | |
3578 | \r | |
3579 | IsochronousCallBack - When the transfer complete, the call back function will be called\r | |
3580 | \r | |
3581 | Context - Pass to the call back function as parameter\r | |
3582 | \r | |
3583 | Returns:\r | |
3584 | EFI_UNSUPPORTED \r | |
3585 | \r | |
3586 | --*/\r | |
3587 | {\r | |
3588 | return EFI_UNSUPPORTED;\r | |
3589 | }\r | |
3590 | \r | |
562d2849 | 3591 | //\r |
3592 | // UEFI 2.0 Protocol\r | |
3593 | //\r | |
3594 | EFI_STATUS\r | |
3595 | EFIAPI\r | |
3596 | UHCI2GetCapability(\r | |
3597 | IN EFI_USB2_HC_PROTOCOL * This,\r | |
3598 | OUT UINT8 *MaxSpeed,\r | |
3599 | OUT UINT8 *PortNumber,\r | |
3600 | OUT UINT8 *Is64BitCapable\r | |
3601 | )\r | |
3602 | /*++\r | |
3603 | \r | |
3604 | Routine Description:\r | |
3605 | Retrieves capabilities of USB host controller according to UEFI 2.0 spec.\r | |
3606 | \r | |
3607 | Arguments:\r | |
3608 | This - A pointer to the EFI_USB2_HC_PROTOCOL instance.\r | |
3609 | \r | |
3610 | MaxSpeed - A pointer to the max speed USB host controller supports.\r | |
3611 | \r | |
3612 | PortNumber - A pointer to the number of root hub ports.\r | |
3613 | \r | |
3614 | Is64BitCapable - A pointer to an integer to show whether USB host controller\r | |
3615 | supports 64-bit memory addressing.\r | |
3616 | Returns:\r | |
3617 | EFI_SUCCESS \r | |
3618 | The host controller capabilities were retrieved successfully.\r | |
3619 | EFI_INVALID_PARAMETER \r | |
3620 | MaxSpeed or PortNumber or Is64BitCapable is NULL.\r | |
3621 | EFI_DEVICE_ERROR \r | |
3622 | An error was encountered while attempting to retrieve the capabilities.\r | |
3623 | \r | |
3624 | --*/ \r | |
3625 | {\r | |
3626 | USB_HC_DEV *HcDev;\r | |
3627 | \r | |
3628 | HcDev = USB2_HC_DEV_FROM_THIS (This);\r | |
3629 | \r | |
3630 | if ((NULL == MaxSpeed) \r | |
3631 | ||(NULL == PortNumber)\r | |
3632 | || (NULL == Is64BitCapable))\r | |
3633 | {\r | |
3634 | return EFI_INVALID_PARAMETER;\r | |
3635 | }\r | |
3636 | \r | |
3637 | *MaxSpeed = EFI_USB_SPEED_FULL;\r | |
3638 | *Is64BitCapable = (UINT8)FALSE;\r | |
3639 | return UHCIGetRootHubPortNumber(&HcDev->UsbHc, PortNumber);\r | |
3640 | }\r | |
3641 | \r | |
3642 | EFI_STATUS\r | |
3643 | EFIAPI\r | |
3644 | UHCI2Reset (\r | |
3645 | IN EFI_USB2_HC_PROTOCOL * This,\r | |
3646 | IN UINT16 Attributes\r | |
3647 | )\r | |
3648 | /*++\r | |
3649 | \r | |
3650 | Routine Description:\r | |
3651 | Provides software reset for the USB host controller according to UEFI 2.0 spec.\r | |
3652 | \r | |
3653 | Arguments:\r | |
3654 | This - A pointer to the EFI_USB2_HC_PROTOCOL instance.\r | |
3655 | \r | |
3656 | Attributes - A bit mask of the reset operation to perform. \r | |
3657 | See below for a list of the supported bit mask values.\r | |
3658 | \r | |
3659 | #define EFI_USB_HC_RESET_GLOBAL 0x0001\r | |
3660 | #define EFI_USB_HC_RESET_HOST_CONTROLLER 0x0002\r | |
3661 | #define EFI_USB_HC_RESET_GLOBAL _WITH_DEBUG 0x0004\r | |
3662 | #define EFI_USB_HC_RESET_HOST_WITH_DEBUG 0x0008\r | |
3663 | \r | |
3664 | EFI_USB_HC_RESET_GLOBAL \r | |
3665 | If this bit is set, a global reset signal will be sent to the USB bus.\r | |
3666 | This resets all of the USB bus logic, including the USB host \r | |
3667 | controller hardware and all the devices attached on the USB bus.\r | |
3668 | EFI_USB_HC_RESET_HOST_CONTROLLER \r | |
3669 | If this bit is set, the USB host controller hardware will be reset. \r | |
3670 | No reset signal will be sent to the USB bus.\r | |
3671 | \r | |
3672 | Returns:\r | |
3673 | EFI_SUCCESS \r | |
3674 | The reset operation succeeded.\r | |
3675 | EFI_INVALID_PARAMETER \r | |
3676 | Attributes is not valid.\r | |
3677 | EFI_UNSUPPORTED\r | |
3678 | The type of reset specified by Attributes is not currently supported by the host controller hardware.\r | |
3679 | EFI_ACCESS_DENIED\r | |
3680 | Reset operation is rejected due to the debug port being configured and active.\r | |
3681 | EFI_DEVICE_ERROR \r | |
3682 | An error was encountered while attempting to perform \r | |
3683 | the reset operation.\r | |
3684 | --*/\r | |
3685 | {\r | |
3686 | USB_HC_DEV *HcDev;\r | |
3687 | \r | |
3688 | HcDev = USB2_HC_DEV_FROM_THIS (This);\r | |
3689 | \r | |
3690 | if (Attributes==EFI_USB_HC_RESET_GLOBAL_WITH_DEBUG || Attributes==EFI_USB_HC_RESET_HOST_WITH_DEBUG)\r | |
3691 | return EFI_UNSUPPORTED;\r | |
3692 | \r | |
3693 | return UHCIReset(\r | |
3694 | &HcDev->UsbHc, \r | |
3695 | Attributes\r | |
3696 | );\r | |
3697 | }\r | |
3698 | \r | |
3699 | EFI_STATUS\r | |
3700 | EFIAPI\r | |
3701 | UHCI2GetState (\r | |
3702 | IN EFI_USB2_HC_PROTOCOL * This,\r | |
3703 | OUT EFI_USB_HC_STATE * State\r | |
3704 | )\r | |
3705 | /*++\r | |
3706 | \r | |
3707 | Routine Description:\r | |
3708 | Retrieves current state of the USB host controller according to UEFI 2.0 spec.\r | |
3709 | \r | |
3710 | Arguments:\r | |
3711 | \r | |
3712 | This - A pointer to the EFI_USB_HC_PROTOCOL instance.\r | |
3713 | \r | |
3714 | State - A pointer to the EFI_USB_HC_STATE data structure that \r | |
3715 | indicates current state of the USB host controller. \r | |
3716 | Type EFI_USB_HC_STATE is defined below.\r | |
3717 | \r | |
3718 | typedef enum {\r | |
3719 | EfiUsbHcStateHalt,\r | |
3720 | EfiUsbHcStateOperational,\r | |
3721 | EfiUsbHcStateSuspend,\r | |
3722 | EfiUsbHcStateMaximum\r | |
3723 | } EFI_USB_HC_STATE;\r | |
3724 | \r | |
3725 | Returns:\r | |
3726 | EFI_SUCCESS \r | |
3727 | The state information of the host controller was returned in State.\r | |
3728 | EFI_INVALID_PARAMETER \r | |
3729 | State is NULL.\r | |
3730 | EFI_DEVICE_ERROR \r | |
3731 | An error was encountered while attempting to retrieve the \r | |
3732 | host controller's current state. \r | |
3733 | --*/ \r | |
3734 | {\r | |
3735 | USB_HC_DEV *HcDev;\r | |
3736 | \r | |
3737 | HcDev = USB2_HC_DEV_FROM_THIS (This);\r | |
3738 | return UHCIGetState(\r | |
3739 | &HcDev->UsbHc, \r | |
3740 | State\r | |
3741 | );\r | |
3742 | }\r | |
3743 | \r | |
3744 | EFI_STATUS\r | |
3745 | EFIAPI\r | |
3746 | UHCI2SetState (\r | |
3747 | IN EFI_USB2_HC_PROTOCOL * This,\r | |
3748 | IN EFI_USB_HC_STATE State\r | |
3749 | )\r | |
3750 | /*++\r | |
3751 | \r | |
3752 | Routine Description:\r | |
3753 | Sets the USB host controller to a specific state according to UEFI 2.0 spec.\r | |
3754 | \r | |
3755 | Arguments:\r | |
3756 | \r | |
3757 | This - A pointer to the EFI_USB_HC_PROTOCOL instance.\r | |
3758 | \r | |
3759 | State - Indicates the state of the host controller that will be set.\r | |
3760 | \r | |
3761 | Returns:\r | |
3762 | EFI_SUCCESS \r | |
3763 | The USB host controller was successfully placed in the state \r | |
3764 | specified by State.\r | |
3765 | EFI_INVALID_PARAMETER \r | |
3766 | State is invalid.\r | |
3767 | EFI_DEVICE_ERROR \r | |
3768 | Failed to set the state specified by State due to device error. \r | |
3769 | --*/\r | |
3770 | {\r | |
3771 | USB_HC_DEV *HcDev;\r | |
3772 | \r | |
3773 | HcDev = USB2_HC_DEV_FROM_THIS (This);\r | |
3774 | return UHCISetState(\r | |
3775 | &HcDev->UsbHc, \r | |
3776 | State\r | |
3777 | );\r | |
3778 | }\r | |
3779 | \r | |
3780 | EFI_STATUS\r | |
3781 | EFIAPI\r | |
3782 | UHCI2ControlTransfer (\r | |
3783 | IN EFI_USB2_HC_PROTOCOL * This,\r | |
3784 | IN UINT8 DeviceAddress,\r | |
3785 | IN UINT8 DeviceSpeed,\r | |
3786 | IN UINTN MaximumPacketLength,\r | |
3787 | IN EFI_USB_DEVICE_REQUEST * Request,\r | |
3788 | IN EFI_USB_DATA_DIRECTION TransferDirection,\r | |
3789 | IN OUT VOID *Data,\r | |
3790 | IN OUT UINTN *DataLength,\r | |
3791 | IN UINTN TimeOut,\r | |
3792 | IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Translator,\r | |
3793 | OUT UINT32 *TransferResult\r | |
3794 | )\r | |
3795 | /*++\r | |
3796 | \r | |
3797 | Routine Description:\r | |
3798 | Submits control transfer to a target USB device accroding to UEFI 2.0 spec..\r | |
3799 | \r | |
3800 | Arguments:\r | |
3801 | \r | |
3802 | This - A pointer to the EFI_USB_HC_PROTOCOL instance.\r | |
3803 | \r | |
3804 | DeviceAddress -Represents the address of the target device on the USB,\r | |
3805 | which is assigned during USB enumeration.\r | |
3806 | \r | |
3807 | DeviceSpeed - Indicates transfer speed of device.\r | |
3808 | \r | |
3809 | MaximumPacketLength - Indicates the maximum packet size that the \r | |
3810 | default control transfer endpoint is capable of \r | |
3811 | sending or receiving.\r | |
3812 | \r | |
3813 | Request - A pointer to the USB device request that will be sent \r | |
3814 | to the USB device. \r | |
3815 | \r | |
3816 | TransferDirection - Specifies the data direction for the transfer.\r | |
3817 | There are three values available, DataIn, DataOut \r | |
3818 | and NoData.\r | |
3819 | \r | |
3820 | Data -A pointer to the buffer of data that will be transmitted \r | |
3821 | to USB device or received from USB device.\r | |
3822 | \r | |
3823 | DataLength - Indicates the size, in bytes, of the data buffer \r | |
3824 | specified by Data.\r | |
3825 | \r | |
3826 | TimeOut - Indicates the maximum time, in microseconds, \r | |
3827 | which the transfer is allowed to complete.\r | |
3828 | \r | |
3829 | TransferResult - A pointer to the detailed result information generated \r | |
3830 | by this control transfer.\r | |
3831 | \r | |
3832 | Returns:\r | |
3833 | EFI_SUCCESS \r | |
3834 | The control transfer was completed successfully.\r | |
3835 | EFI_OUT_OF_RESOURCES \r | |
3836 | The control transfer could not be completed due to a lack of resources.\r | |
3837 | EFI_INVALID_PARAMETER \r | |
3838 | Some parameters are invalid.\r | |
3839 | EFI_TIMEOUT \r | |
3840 | The control transfer failed due to timeout.\r | |
3841 | EFI_DEVICE_ERROR \r | |
3842 | The control transfer failed due to host controller or device error. \r | |
3843 | Caller should check TranferResult for detailed error information.\r | |
3844 | \r | |
3845 | --*/\r | |
3846 | {\r | |
3847 | USB_HC_DEV *HcDev;\r | |
3848 | BOOLEAN IsSlowDevice = (EFI_USB_SPEED_LOW == DeviceSpeed) ? TRUE : FALSE;\r | |
3849 | \r | |
3850 | HcDev = USB2_HC_DEV_FROM_THIS (This);\r | |
3851 | \r | |
3852 | return UHCIControlTransfer(\r | |
3853 | &HcDev->UsbHc, \r | |
3854 | DeviceAddress, \r | |
3855 | IsSlowDevice, \r | |
3856 | (UINT8) MaximumPacketLength, \r | |
3857 | Request, \r | |
3858 | TransferDirection, \r | |
3859 | Data, \r | |
3860 | DataLength,\r | |
3861 | TimeOut,\r | |
3862 | TransferResult\r | |
3863 | ); \r | |
3864 | }\r | |
3865 | \r | |
3866 | EFI_STATUS\r | |
3867 | EFIAPI\r | |
3868 | UHCI2BulkTransfer (\r | |
3869 | IN EFI_USB2_HC_PROTOCOL * This,\r | |
3870 | IN UINT8 DeviceAddress,\r | |
3871 | IN UINT8 EndPointAddress,\r | |
3872 | IN UINT8 DeviceSpeed,\r | |
3873 | IN UINTN MaximumPacketLength,\r | |
3874 | IN UINT8 DataBuffersNumber,\r | |
3875 | IN OUT VOID *Data[EFI_USB_MAX_BULK_BUFFER_NUM],\r | |
3876 | IN OUT UINTN *DataLength,\r | |
3877 | IN OUT UINT8 *DataToggle,\r | |
3878 | IN UINTN TimeOut,\r | |
3879 | IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Translator,\r | |
3880 | OUT UINT32 *TransferResult\r | |
3881 | ) \r | |
3882 | /*++\r | |
3883 | \r | |
3884 | Routine Description:\r | |
3885 | Submits bulk transfer to a bulk endpoint of a USB device according to UEFI 2.0 spec.\r | |
3886 | \r | |
3887 | Arguments:\r | |
3888 | \r | |
3889 | This A pointer to the EFI_USB2_HC_PROTOCOL instance.\r | |
3890 | \r | |
3891 | DeviceAddress Represents the address of the target device on the USB,\r | |
3892 | which is assigned during USB enumeration.\r | |
3893 | \r | |
3894 | EndPointAddress The combination of an endpoint number and an \r | |
3895 | endpoint direction of the target USB device. \r | |
3896 | Each endpoint address supports data transfer in \r | |
3897 | one direction except the control endpoint \r | |
3898 | (whose default endpoint address is 0). \r | |
3899 | It is the caller's responsibility to make sure that \r | |
3900 | the EndPointAddress represents a bulk endpoint. \r | |
3901 | \r | |
3902 | DeviceSpeed Indicates device speed. The supported values are EFI_USB_SPEED_FULL\r | |
3903 | and EFI_USB_SPEED_HIGH.\r | |
3904 | \r | |
3905 | MaximumPacketLength Indicates the maximum packet size the target endpoint\r | |
3906 | is capable of sending or receiving.\r | |
3907 | \r | |
3908 | DataBuffersNumber Number of data buffers prepared for the transfer.\r | |
3909 | \r | |
3910 | Data Array of pointers to the buffers of data that will be transmitted \r | |
3911 | to USB device or received from USB device.\r | |
3912 | \r | |
3913 | DataLength When input, indicates the size, in bytes, of the data buffer\r | |
3914 | specified by Data. When output, indicates the actually \r | |
3915 | transferred data size.\r | |
3916 | \r | |
3917 | DataToggle A pointer to the data toggle value. On input, it indicates \r | |
3918 | the initial data toggle value the bulk transfer should adopt;\r | |
3919 | on output, it is updated to indicate the data toggle value \r | |
3920 | of the subsequent bulk transfer. \r | |
3921 | \r | |
3922 | Translator A pointr to the transaction translator data.\r | |
3923 | \r | |
3924 | TimeOut Indicates the maximum time, in microseconds, which the \r | |
3925 | transfer is allowed to complete.\r | |
3926 | \r | |
3927 | TransferResult A pointer to the detailed result information of the \r | |
3928 | bulk transfer.\r | |
3929 | \r | |
3930 | Returns:\r | |
3931 | EFI_SUCCESS \r | |
3932 | The bulk transfer was completed successfully.\r | |
3933 | \r | |
3934 | EFI_OUT_OF_RESOURCES \r | |
3935 | The bulk transfer could not be submitted due to lack of resource.\r | |
3936 | \r | |
3937 | EFI_INVALID_PARAMETER \r | |
3938 | Some parameters are invalid.\r | |
3939 | \r | |
3940 | EFI_TIMEOUT \r | |
3941 | The bulk transfer failed due to timeout.\r | |
3942 | \r | |
3943 | EFI_DEVICE_ERROR \r | |
3944 | The bulk transfer failed due to host controller or device error.\r | |
3945 | Caller should check TranferResult for detailed error information.\r | |
3946 | \r | |
3947 | --*/ \r | |
3948 | {\r | |
3949 | USB_HC_DEV *HcDev;\r | |
3950 | \r | |
3951 | HcDev = USB2_HC_DEV_FROM_THIS (This);\r | |
3952 | \r | |
3953 | if( Data == NULL || DeviceSpeed==EFI_USB_SPEED_LOW)\r | |
3954 | return EFI_INVALID_PARAMETER;\r | |
3955 | /* For full-speed bulk transfers only the data pointed by Data[0] shall be used */\r | |
3956 | \r | |
3957 | return UHCIBulkTransfer (\r | |
3958 | &HcDev->UsbHc, \r | |
3959 | DeviceAddress, \r | |
3960 | EndPointAddress, \r | |
3961 | (UINT8) MaximumPacketLength, \r | |
3962 | *Data, \r | |
3963 | DataLength, \r | |
3964 | DataToggle, \r | |
3965 | TimeOut, \r | |
3966 | TransferResult\r | |
3967 | );\r | |
3968 | }\r | |
3969 | \r | |
3970 | EFI_STATUS\r | |
3971 | EFIAPI\r | |
3972 | UHCI2AsyncInterruptTransfer (\r | |
3973 | IN EFI_USB2_HC_PROTOCOL * This,\r | |
3974 | IN UINT8 DeviceAddress,\r | |
3975 | IN UINT8 EndPointAddress,\r | |
3976 | IN UINT8 DeviceSpeed,\r | |
3977 | IN UINTN MaximumPacketLength,\r | |
3978 | IN BOOLEAN IsNewTransfer,\r | |
3979 | IN OUT UINT8 *DataToggle,\r | |
3980 | IN UINTN PollingInterval,\r | |
3981 | IN UINTN DataLength,\r | |
3982 | IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Translator,\r | |
3983 | IN EFI_ASYNC_USB_TRANSFER_CALLBACK CallBackFunction,\r | |
3984 | IN VOID *Context\r | |
3985 | )\r | |
3986 | /*++\r | |
3987 | \r | |
3988 | Routine Description:\r | |
3989 | Submits an asynchronous interrupt transfer to an \r | |
3990 | interrupt endpoint of a USB device according to UEFI 2.0 spec.\r | |
3991 | \r | |
3992 | Arguments:\r | |
3993 | \r | |
3994 | This A pointer to the EFI_USB2_HC_PROTOCOL instance.\r | |
3995 | \r | |
3996 | DeviceAddress Represents the address of the target device on the USB,\r | |
3997 | which is assigned during USB enumeration.\r | |
3998 | \r | |
3999 | EndPointAddress The combination of an endpoint number and an endpoint \r | |
4000 | direction of the target USB device. Each endpoint address \r | |
4001 | supports data transfer in one direction except the \r | |
4002 | control endpoint (whose default endpoint address is 0). \r | |
4003 | It is the caller's responsibility to make sure that \r | |
4004 | the EndPointAddress represents an interrupt endpoint.\r | |
4005 | \r | |
4006 | DeviceSpeed Indicates device speed.\r | |
4007 | \r | |
4008 | MaximumPacketLength Indicates the maximum packet size the target endpoint\r | |
4009 | is capable of sending or receiving.\r | |
4010 | \r | |
4011 | IsNewTransfer If TRUE, an asynchronous interrupt pipe is built between\r | |
4012 | the host and the target interrupt endpoint. \r | |
4013 | If FALSE, the specified asynchronous interrupt pipe \r | |
4014 | is canceled.\r | |
4015 | \r | |
4016 | DataToggle A pointer to the data toggle value. On input, it is valid \r | |
4017 | when IsNewTransfer is TRUE, and it indicates the initial \r | |
4018 | data toggle value the asynchronous interrupt transfer \r | |
4019 | should adopt. \r | |
4020 | On output, it is valid when IsNewTransfer is FALSE, \r | |
4021 | and it is updated to indicate the data toggle value of \r | |
4022 | the subsequent asynchronous interrupt transfer.\r | |
4023 | \r | |
4024 | PollingInterval Indicates the interval, in milliseconds, that the \r | |
4025 | asynchronous interrupt transfer is polled. \r | |
4026 | This parameter is required when IsNewTransfer is TRUE.\r | |
4027 | \r | |
4028 | DataLength Indicates the length of data to be received at the \r | |
4029 | rate specified by PollingInterval from the target \r | |
4030 | asynchronous interrupt endpoint. This parameter \r | |
4031 | is only required when IsNewTransfer is TRUE.\r | |
4032 | \r | |
4033 | Translator A pointr to the transaction translator data.\r | |
4034 | \r | |
4035 | CallBackFunction The Callback function.This function is called at the \r | |
4036 | rate specified by PollingInterval.This parameter is \r | |
4037 | only required when IsNewTransfer is TRUE.\r | |
4038 | \r | |
4039 | Context The context that is passed to the CallBackFunction.\r | |
4040 | This is an optional parameter and may be NULL.\r | |
4041 | \r | |
4042 | Returns:\r | |
4043 | \r | |
4044 | EFI_SUCCESS \r | |
4045 | The asynchronous interrupt transfer request has been successfully \r | |
4046 | submitted or canceled.\r | |
4047 | \r | |
4048 | EFI_INVALID_PARAMETER \r | |
4049 | Some parameters are invalid.\r | |
4050 | \r | |
4051 | EFI_OUT_OF_RESOURCES \r | |
4052 | The request could not be completed due to a lack of resources. \r | |
4053 | \r | |
4054 | EFI_DEVICE_ERROR\r | |
4055 | Can't read register\r | |
4056 | --*/ \r | |
4057 | {\r | |
4058 | USB_HC_DEV *HcDev;\r | |
4059 | BOOLEAN IsSlowDevice = (EFI_USB_SPEED_LOW == DeviceSpeed) ? TRUE : FALSE;\r | |
4060 | \r | |
4061 | HcDev = USB2_HC_DEV_FROM_THIS (This);\r | |
4062 | return UHCIAsyncInterruptTransfer(\r | |
4063 | &HcDev->UsbHc, \r | |
4064 | DeviceAddress, \r | |
4065 | EndPointAddress, \r | |
4066 | IsSlowDevice, \r | |
4067 | (UINT8) MaximumPacketLength, \r | |
4068 | IsNewTransfer, \r | |
4069 | DataToggle, \r | |
4070 | PollingInterval,\r | |
4071 | DataLength, \r | |
4072 | CallBackFunction,\r | |
4073 | Context\r | |
4074 | );\r | |
4075 | }\r | |
4076 | \r | |
4077 | EFI_STATUS\r | |
4078 | EFIAPI\r | |
4079 | UHCI2SyncInterruptTransfer (\r | |
4080 | IN EFI_USB2_HC_PROTOCOL * This,\r | |
4081 | IN UINT8 DeviceAddress,\r | |
4082 | IN UINT8 EndPointAddress,\r | |
4083 | IN UINT8 DeviceSpeed,\r | |
4084 | IN UINTN MaximumPacketLength,\r | |
4085 | IN OUT VOID *Data,\r | |
4086 | IN OUT UINTN *DataLength,\r | |
4087 | IN OUT UINT8 *DataToggle,\r | |
4088 | IN UINTN TimeOut,\r | |
4089 | IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Translator,\r | |
4090 | OUT UINT32 *TransferResult\r | |
4091 | )\r | |
4092 | /*++\r | |
4093 | \r | |
4094 | Routine Description:\r | |
4095 | Submits synchronous interrupt transfer to an interrupt endpoint \r | |
4096 | of a USB device according to UEFI 2.0 spec.\r | |
4097 | \r | |
4098 | Arguments:\r | |
4099 | \r | |
4100 | This A pointer to the EFI_USB2_HC_PROTOCOL instance.\r | |
4101 | \r | |
4102 | DeviceAddress Represents the address of the target device on the USB, \r | |
4103 | which is assigned during USB enumeration.\r | |
4104 | \r | |
4105 | EndPointAddress The combination of an endpoint number and an endpoint \r | |
4106 | direction of the target USB device. Each endpoint \r | |
4107 | address supports data transfer in one direction \r | |
4108 | except the control endpoint (whose default \r | |
4109 | endpoint address is 0). It is the caller's responsibility\r | |
4110 | to make sure that the EndPointAddress represents \r | |
4111 | an interrupt endpoint. \r | |
4112 | \r | |
4113 | DeviceSpeed Indicates device speed.\r | |
4114 | \r | |
4115 | MaximumPacketLength Indicates the maximum packet size the target endpoint \r | |
4116 | is capable of sending or receiving.\r | |
4117 | \r | |
4118 | Data A pointer to the buffer of data that will be transmitted \r | |
4119 | to USB device or received from USB device.\r | |
4120 | \r | |
4121 | DataLength On input, the size, in bytes, of the data buffer specified \r | |
4122 | by Data. On output, the number of bytes transferred.\r | |
4123 | \r | |
4124 | DataToggle A pointer to the data toggle value. On input, it indicates\r | |
4125 | the initial data toggle value the synchronous interrupt \r | |
4126 | transfer should adopt; \r | |
4127 | on output, it is updated to indicate the data toggle value \r | |
4128 | of the subsequent synchronous interrupt transfer. \r | |
4129 | \r | |
4130 | TimeOut Indicates the maximum time, in microseconds, which the \r | |
4131 | transfer is allowed to complete.\r | |
4132 | Translator A pointr to the transaction translator data.\r | |
4133 | TransferResult A pointer to the detailed result information from \r | |
4134 | the synchronous interrupt transfer. \r | |
4135 | \r | |
4136 | Returns:\r | |
4137 | EFI_SUCCESS \r | |
4138 | The synchronous interrupt transfer was completed successfully.\r | |
4139 | EFI_OUT_OF_RESOURCES \r | |
4140 | The synchronous interrupt transfer could not be submitted due \r | |
4141 | to lack of resource.\r | |
4142 | EFI_INVALID_PARAMETER \r | |
4143 | Some parameters are invalid.\r | |
4144 | EFI_TIMEOUT \r | |
4145 | The synchronous interrupt transfer failed due to timeout.\r | |
4146 | EFI_DEVICE_ERROR \r | |
4147 | The synchronous interrupt transfer failed due to host controller \r | |
4148 | or device error. Caller should check TranferResult for detailed \r | |
4149 | error information. \r | |
4150 | --*/ \r | |
4151 | {\r | |
4152 | USB_HC_DEV *HcDev;\r | |
4153 | BOOLEAN IsSlowDevice;\r | |
4154 | \r | |
4155 | if(DeviceSpeed==EFI_USB_SPEED_HIGH)\r | |
4156 | return EFI_INVALID_PARAMETER;\r | |
4157 | \r | |
4158 | IsSlowDevice = (EFI_USB_SPEED_LOW == DeviceSpeed) ? TRUE : FALSE; \r | |
4159 | HcDev = USB2_HC_DEV_FROM_THIS (This);\r | |
4160 | \r | |
4161 | return UHCISyncInterruptTransfer(\r | |
4162 | &HcDev->UsbHc, \r | |
4163 | DeviceAddress, \r | |
4164 | EndPointAddress, \r | |
4165 | IsSlowDevice, \r | |
4166 | (UINT8) MaximumPacketLength, \r | |
4167 | Data, \r | |
4168 | DataLength, \r | |
4169 | DataToggle,\r | |
4170 | TimeOut,\r | |
4171 | TransferResult\r | |
4172 | );\r | |
4173 | }\r | |
4174 | \r | |
4175 | EFI_STATUS\r | |
4176 | EFIAPI\r | |
4177 | UHCI2IsochronousTransfer (\r | |
4178 | IN EFI_USB2_HC_PROTOCOL * This,\r | |
4179 | IN UINT8 DeviceAddress,\r | |
4180 | IN UINT8 EndPointAddress,\r | |
4181 | IN UINT8 DeviceSpeed,\r | |
4182 | IN UINTN MaximumPacketLength,\r | |
4183 | IN UINT8 DataBuffersNumber,\r | |
4184 | IN OUT VOID *Data[EFI_USB_MAX_ISO_BUFFER_NUM],\r | |
4185 | IN UINTN DataLength,\r | |
4186 | IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Translator,\r | |
4187 | OUT UINT32 *TransferResult\r | |
4188 | )\r | |
4189 | /*++\r | |
4190 | \r | |
4191 | Routine Description:\r | |
4192 | \r | |
4193 | Submits isochronous transfer to a target USB device according to UEFI 2.0 spec.\r | |
4194 | \r | |
4195 | Arguments:\r | |
4196 | \r | |
4197 | This A pointer to the EFI_USB2_HC_PROTOCOL instance.\r | |
4198 | \r | |
4199 | DeviceAddress Represents the address of the target device on the USB,\r | |
4200 | which is assigned during USB enumeration.\r | |
4201 | \r | |
4202 | EndPointAddress End point address\r | |
4203 | \r | |
4204 | DeviceSpeed Indicates device speed.\r | |
4205 | \r | |
4206 | MaximumPacketLength Indicates the maximum packet size that the \r | |
4207 | default control transfer endpoint is capable of \r | |
4208 | sending or receiving.\r | |
4209 | \r | |
4210 | DataBuffersNumber Number of data buffers prepared for the transfer.\r | |
4211 | \r | |
4212 | Data Array of pointers to the buffers of data that will be \r | |
4213 | transmitted to USB device or received from USB device.\r | |
4214 | \r | |
4215 | DataLength Indicates the size, in bytes, of the data buffer \r | |
4216 | specified by Data.\r | |
4217 | \r | |
4218 | Translator A pointr to the transaction translator data.\r | |
4219 | \r | |
4220 | TransferResult A pointer to the detailed result information generated \r | |
4221 | by this control transfer. \r | |
4222 | Returns:\r | |
4223 | \r | |
4224 | EFI_UNSUPPORTED \r | |
4225 | \r | |
4226 | --*/ \r | |
4227 | {\r | |
4228 | return EFI_UNSUPPORTED;\r | |
4229 | }\r | |
4230 | \r | |
4231 | EFI_STATUS\r | |
4232 | EFIAPI\r | |
4233 | UHCI2AsyncIsochronousTransfer (\r | |
4234 | IN EFI_USB2_HC_PROTOCOL * This,\r | |
4235 | IN UINT8 DeviceAddress,\r | |
4236 | IN UINT8 EndPointAddress,\r | |
4237 | IN UINT8 DeviceSpeed,\r | |
4238 | IN UINTN MaximumPacketLength,\r | |
4239 | IN UINT8 DataBuffersNumber,\r | |
4240 | IN OUT VOID *Data[EFI_USB_MAX_ISO_BUFFER_NUM],\r | |
4241 | IN UINTN DataLength,\r | |
4242 | IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Translator,\r | |
4243 | IN EFI_ASYNC_USB_TRANSFER_CALLBACK IsochronousCallBack,\r | |
4244 | IN VOID *Context\r | |
4245 | )\r | |
4246 | /*++\r | |
4247 | \r | |
4248 | Routine Description:\r | |
4249 | \r | |
4250 | Submits Async isochronous transfer to a target USB device according to UEFI 2.0 spec.\r | |
4251 | \r | |
4252 | Arguments:\r | |
4253 | \r | |
4254 | This A pointer to the EFI_USB2_HC_PROTOCOL instance.\r | |
4255 | \r | |
4256 | DeviceAddress Represents the address of the target device on the USB,\r | |
4257 | which is assigned during USB enumeration.\r | |
4258 | \r | |
4259 | EndPointAddress End point address\r | |
4260 | \r | |
4261 | DeviceSpeed Indicates device speed.\r | |
4262 | \r | |
4263 | MaximumPacketLength Indicates the maximum packet size that the \r | |
4264 | default control transfer endpoint is capable of \r | |
4265 | sending or receiving.\r | |
4266 | \r | |
4267 | DataBuffersNumber Number of data buffers prepared for the transfer.\r | |
4268 | \r | |
4269 | Data Array of pointers to the buffers of data that will be transmitted \r | |
4270 | to USB device or received from USB device.\r | |
4271 | \r | |
4272 | Translator A pointr to the transaction translator data.\r | |
4273 | \r | |
4274 | IsochronousCallBack When the transfer complete, the call back function will be called\r | |
4275 | \r | |
4276 | Context Pass to the call back function as parameter\r | |
4277 | \r | |
4278 | Returns:\r | |
4279 | \r | |
4280 | EFI_UNSUPPORTED \r | |
4281 | \r | |
4282 | --*/ \r | |
4283 | {\r | |
4284 | return EFI_UNSUPPORTED;\r | |
4285 | }\r | |
4286 | \r | |
4287 | EFI_STATUS\r | |
4288 | EFIAPI\r | |
4289 | UHCI2GetRootHubPortStatus (\r | |
4290 | IN EFI_USB2_HC_PROTOCOL * This,\r | |
4291 | IN UINT8 PortNumber,\r | |
4292 | OUT EFI_USB_PORT_STATUS * PortStatus\r | |
4293 | )\r | |
4294 | /*++\r | |
4295 | \r | |
4296 | Routine Description:\r | |
4297 | Retrieves the current status of a USB root hub port according to UEFI 2.0 spec.\r | |
4298 | \r | |
4299 | Arguments:\r | |
4300 | \r | |
4301 | This A pointer to the EFI_USB2_HC_PROTOCOL.\r | |
4302 | \r | |
4303 | PortNumber Specifies the root hub port from which the status \r | |
4304 | is to be retrieved. This value is zero-based. For example, \r | |
4305 | if a root hub has two ports, then the first port is numbered 0,\r | |
4306 | and the second port is numbered 1.\r | |
4307 | \r | |
4308 | PortStatus A pointer to the current port status bits and \r | |
4309 | port status change bits. \r | |
4310 | \r | |
4311 | Returns:\r | |
4312 | EFI_SUCCESS \r | |
4313 | The status of the USB root hub port specified by PortNumber \r | |
4314 | was returned in PortStatus.\r | |
4315 | EFI_INVALID_PARAMETER \r | |
4316 | PortNumber is invalid. \r | |
4317 | EFI_DEVICE_ERROR - Can't read register \r | |
4318 | --*/ \r | |
4319 | {\r | |
4320 | USB_HC_DEV *HcDev;\r | |
4321 | \r | |
4322 | HcDev = USB2_HC_DEV_FROM_THIS (This);\r | |
4323 | \r | |
4324 | return UHCIGetRootHubPortStatus(\r | |
4325 | &HcDev->UsbHc, \r | |
4326 | PortNumber, \r | |
4327 | PortStatus\r | |
4328 | );\r | |
4329 | }\r | |
4330 | \r | |
4331 | EFI_STATUS\r | |
4332 | EFIAPI\r | |
4333 | UHCI2SetRootHubPortFeature (\r | |
4334 | IN EFI_USB2_HC_PROTOCOL * This,\r | |
4335 | IN UINT8 PortNumber,\r | |
4336 | IN EFI_USB_PORT_FEATURE PortFeature\r | |
4337 | )\r | |
4338 | /*++\r | |
4339 | \r | |
4340 | Routine Description:\r | |
4341 | Sets a feature for the specified root hub port according to UEFI 2.0 spec.\r | |
4342 | \r | |
4343 | Arguments:\r | |
4344 | \r | |
4345 | This A pointer to the EFI_USB2_HC_PROTOCOL.\r | |
4346 | \r | |
4347 | PortNumber Specifies the root hub port whose feature \r | |
4348 | is requested to be set.\r | |
4349 | \r | |
4350 | PortFeature Indicates the feature selector associated \r | |
4351 | with the feature set request. \r | |
4352 | \r | |
4353 | Returns:\r | |
4354 | EFI_SUCCESS \r | |
4355 | The feature specified by PortFeature was set for the \r | |
4356 | USB root hub port specified by PortNumber.\r | |
4357 | EFI_INVALID_PARAMETER \r | |
4358 | PortNumber is invalid or PortFeature is invalid.\r | |
4359 | EFI_DEVICE_ERROR\r | |
4360 | Can't read register\r | |
4361 | --*/ \r | |
4362 | {\r | |
4363 | USB_HC_DEV *HcDev;\r | |
4364 | \r | |
4365 | HcDev = USB2_HC_DEV_FROM_THIS (This);\r | |
4366 | return UHCISetRootHubPortFeature(\r | |
4367 | &HcDev->UsbHc, \r | |
4368 | PortNumber, \r | |
4369 | PortFeature\r | |
4370 | );\r | |
4371 | }\r | |
4372 | \r | |
4373 | EFI_STATUS\r | |
4374 | EFIAPI\r | |
4375 | UHCI2ClearRootHubPortFeature (\r | |
4376 | IN EFI_USB2_HC_PROTOCOL * This,\r | |
4377 | IN UINT8 PortNumber,\r | |
4378 | IN EFI_USB_PORT_FEATURE PortFeature\r | |
4379 | )\r | |
4380 | /*++\r | |
4381 | \r | |
4382 | Routine Description:\r | |
4383 | Clears a feature for the specified root hub port according to Uefi 2.0 spec.\r | |
4384 | \r | |
4385 | Arguments:\r | |
4386 | \r | |
4387 | This A pointer to the EFI_USB2_HC_PROTOCOL instance.\r | |
4388 | \r | |
4389 | PortNumber Specifies the root hub port whose feature \r | |
4390 | is requested to be cleared.\r | |
4391 | \r | |
4392 | PortFeature Indicates the feature selector associated with the \r | |
4393 | feature clear request.\r | |
4394 | \r | |
4395 | Returns:\r | |
4396 | EFI_SUCCESS \r | |
4397 | The feature specified by PortFeature was cleared for the \r | |
4398 | USB root hub port specified by PortNumber.\r | |
4399 | EFI_INVALID_PARAMETER \r | |
4400 | PortNumber is invalid or PortFeature is invalid.\r | |
4401 | EFI_DEVICE_ERROR\r | |
4402 | Can't read register\r | |
4403 | --*/ \r | |
4404 | {\r | |
4405 | USB_HC_DEV *HcDev;\r | |
4406 | \r | |
4407 | HcDev = USB2_HC_DEV_FROM_THIS (This);\r | |
4408 | return UHCIClearRootHubPortFeature(\r | |
4409 | &HcDev->UsbHc, \r | |
4410 | PortNumber, \r | |
4411 | PortFeature\r | |
4412 | );\r | |
4413 | }\r | |
4414 | \r | |
878ddf1f | 4415 | VOID\r |
4416 | EFIAPI\r | |
4417 | MonitorInterruptTrans (\r | |
4418 | IN EFI_EVENT Event,\r | |
4419 | IN VOID *Context\r | |
4420 | )\r | |
4421 | /*++\r | |
4422 | Routine Description:\r | |
4423 | Interrupt transfer periodic check handler\r | |
4424 | Arguments:\r | |
4425 | Event - Interrupt event\r | |
4426 | Contex - Pointer to USB_HC_DEV\r | |
4427 | Returns:\r | |
4428 | None\r | |
4429 | --*/ \r | |
4430 | {\r | |
4431 | \r | |
4432 | USB_HC_DEV *HcDev;\r | |
4433 | INTERRUPT_LIST *PtrList;\r | |
4434 | LIST_ENTRY *Link;\r | |
4435 | UINT32 Result;\r | |
4436 | VOID *DataBuffer;\r | |
4437 | UINTN DataLen;\r | |
4438 | UINTN ActualLen;\r | |
4439 | UINTN ErrTDPos;\r | |
4440 | UINT32 StatusAddr;\r | |
4441 | LIST_ENTRY *NextLink;\r | |
4442 | \r | |
4443 | HcDev = (USB_HC_DEV *) Context;\r | |
4444 | StatusAddr = (UINT32) (USBSTS);\r | |
4445 | \r | |
4446 | //\r | |
4447 | // interrupt transfer list is empty, means that no interrupt transfer\r | |
4448 | // is submitted by far.\r | |
4449 | //\r | |
4450 | if (IsListEmpty (&(HcDev->InterruptListHead))) {\r | |
4451 | return ;\r | |
4452 | }\r | |
4453 | \r | |
4454 | NextLink = HcDev->InterruptListHead.ForwardLink;\r | |
4455 | do {\r | |
4456 | \r | |
4457 | Link = NextLink;\r | |
4458 | NextLink = Link->ForwardLink;\r | |
4459 | \r | |
4460 | PtrList = INTERRUPT_LIST_FROM_LINK (Link);\r | |
4461 | \r | |
4462 | //\r | |
4463 | // get TD execution results.\r | |
4464 | // ErrTDPos is zero-based value indicating the first error TD's position\r | |
4465 | // in the TDs' list.\r | |
4466 | // This value is only valid when Result not equal NOERROR.\r | |
4467 | //\r | |
4468 | ExecuteAsyncINTTDs (\r | |
4469 | HcDev,\r | |
4470 | PtrList,\r | |
4471 | &Result,\r | |
4472 | &ErrTDPos,\r | |
4473 | &ActualLen\r | |
4474 | );\r | |
4475 | \r | |
4476 | //\r | |
4477 | // interrupt transfer has not been executed yet.\r | |
4478 | //\r | |
4479 | if (((Result & EFI_USB_ERR_NAK) == EFI_USB_ERR_NAK) ||\r | |
4480 | ((Result & EFI_USB_ERR_NOTEXECUTE) == EFI_USB_ERR_NOTEXECUTE)) {\r | |
4481 | continue;\r | |
4482 | }\r | |
4483 | //\r | |
4484 | // get actual data length transferred data and its data length.\r | |
4485 | //\r | |
4486 | DataLen = ActualLen;\r | |
4487 | DataBuffer = AllocatePool (DataLen);\r | |
4488 | if (DataBuffer == NULL) {\r | |
4489 | return ;\r | |
4490 | }\r | |
4491 | \r | |
4492 | CopyMem (\r | |
4493 | DataBuffer,\r | |
4494 | PtrList->PtrFirstTD->pTDBuffer,\r | |
4495 | DataLen\r | |
4496 | );\r | |
4497 | \r | |
4498 | //\r | |
4499 | // only if interrupt endpoint responds\r | |
4500 | // and the interrupt transfer stops because of completion\r | |
4501 | // or error, then we will call callback function.\r | |
4502 | //\r | |
4503 | if (Result == EFI_USB_NOERROR) {\r | |
4504 | //\r | |
4505 | // add for real platform debug\r | |
4506 | //\r | |
4507 | if (PtrList->InterruptCallBack != NULL) {\r | |
4508 | (PtrList->InterruptCallBack) (\r | |
4509 | DataBuffer,\r | |
4510 | DataLen,\r | |
4511 | PtrList->InterruptContext,\r | |
4512 | Result\r | |
4513 | );\r | |
4514 | }\r | |
4515 | \r | |
4516 | if (DataBuffer) {\r | |
4517 | gBS->FreePool (DataBuffer);\r | |
4518 | }\r | |
4519 | \r | |
4520 | //\r | |
4521 | // update should done after data buffer got.\r | |
4522 | //\r | |
4523 | UpdateAsyncINTQHTDs (PtrList, Result, (UINT32) ErrTDPos);\r | |
4524 | \r | |
4525 | } else {\r | |
4526 | \r | |
4527 | DEBUG ((EFI_D_ERROR, "interrupt transfer error code is %x\n", Result));\r | |
4528 | \r | |
4529 | if (DataBuffer) {\r | |
4530 | gBS->FreePool (DataBuffer);\r | |
4531 | }\r | |
4532 | //\r | |
4533 | // leave error recovery to its related device driver.\r | |
4534 | // A common case of the error recovery is to re-submit the interrupt\r | |
4535 | // transfer.\r | |
4536 | // When an interrupt transfer is re-submitted, its position in the linked\r | |
4537 | // list is changed. It is inserted to the head of the linked list, while\r | |
4538 | // this function scans the whole list from head to tail. Thus, the\r | |
4539 | // re-submitted interrupt transfer's callback function will not be called\r | |
4540 | // again in this round.\r | |
4541 | //\r | |
4542 | if (PtrList->InterruptCallBack != NULL) {\r | |
4543 | (PtrList->InterruptCallBack) (\r | |
4544 | NULL,\r | |
4545 | 0,\r | |
4546 | PtrList->InterruptContext,\r | |
4547 | Result\r | |
4548 | );\r | |
4549 | }\r | |
4550 | }\r | |
4551 | } while (NextLink != &(HcDev->InterruptListHead));\r | |
4552 | \r | |
4553 | }\r |