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878ddf1f | 1 | /*++\r |
2 | \r | |
3 | Copyright (c) 2006, Intel Corporation \r | |
4 | All rights reserved. This program and the accompanying materials \r | |
5 | are licensed and made available under the terms and conditions of the BSD License \r | |
6 | which accompanies this distribution. The full text of the license may be found at \r | |
7 | http://opensource.org/licenses/bsd-license.php \r | |
8 | \r | |
9 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r | |
10 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r | |
11 | \r | |
12 | Module Name:\r | |
13 | \r | |
14 | Uhci.h\r | |
15 | \r | |
16 | Abstract: \r | |
17 | \r | |
18 | \r | |
19 | Revision History\r | |
20 | --*/\r | |
21 | \r | |
22 | #ifndef _UHCI_H\r | |
23 | #define _UHCI_H\r | |
24 | \r | |
25 | /*\r | |
26 | * Universal Host Controller Interface data structures and defines\r | |
27 | */\r | |
28 | \r | |
f0ec738d | 29 | #include <IndustryStandard/pci22.h>\r |
878ddf1f | 30 | \r |
31 | #define EFI_D_UHCI EFI_D_INFO\r | |
32 | \r | |
33 | //\r | |
34 | // stall time\r | |
35 | //\r | |
36 | #define STALL_1_MILLI_SECOND 1000\r | |
37 | #define STALL_1_SECOND 1000 * STALL_1_MILLI_SECOND\r | |
38 | \r | |
39 | #define FORCE_GLOBAL_RESUME_TIME 20 * STALL_1_MILLI_SECOND\r | |
40 | \r | |
41 | #define ROOT_PORT_REST_TIME 50 * STALL_1_MILLI_SECOND\r | |
42 | \r | |
43 | #define PORT_RESET_RECOVERY_TIME 10 * STALL_1_MILLI_SECOND\r | |
44 | \r | |
45 | //\r | |
46 | // 50 ms\r | |
47 | //\r | |
48 | #define INTERRUPT_POLLING_TIME 50 * 1000 * 10\r | |
49 | \r | |
50 | //\r | |
51 | // UHCI IO Space Address Register Register locates at\r | |
52 | // offset 20 ~ 23h of PCI Configuration Space (UHCI spec, Revision 1.1),\r | |
53 | // so, its BAR Index is 4.\r | |
54 | //\r | |
55 | #define USB_BAR_INDEX 4\r | |
56 | \r | |
57 | //\r | |
58 | // One memory block uses 1 page (common buffer for QH,TD use.)\r | |
59 | //\r | |
60 | #define NORMAL_MEMORY_BLOCK_UNIT_IN_PAGES 1\r | |
61 | \r | |
62 | \r | |
63 | #define bit(a) 1 << (a)\r | |
64 | \r | |
65 | //\r | |
66 | // ////////////////////////////////////////////////////////////////////////\r | |
67 | //\r | |
68 | // Universal Host Controller Registers Definitions\r | |
69 | //\r | |
70 | //////////////////////////////////////////////////////////////////////////\r | |
71 | extern UINT16 USBBaseAddr;\r | |
72 | \r | |
73 | /* Command register */\r | |
74 | #define USBCMD 0 /* Command Register Offset 00-01h */\r | |
75 | #define USBCMD_RS bit (0) /* Run/Stop */\r | |
76 | #define USBCMD_HCRESET bit (1) /* Host reset */\r | |
77 | #define USBCMD_GRESET bit (2) /* Global reset */\r | |
78 | #define USBCMD_EGSM bit (3) /* Global Suspend Mode */\r | |
79 | #define USBCMD_FGR bit (4) /* Force Global Resume */\r | |
80 | #define USBCMD_SWDBG bit (5) /* SW Debug mode */\r | |
81 | #define USBCMD_CF bit (6) /* Config Flag (sw only) */\r | |
82 | #define USBCMD_MAXP bit (7) /* Max Packet (0 = 32, 1 = 64) */\r | |
83 | \r | |
84 | /* Status register */\r | |
85 | #define USBSTS 2 /* Status Register Offset 02-03h */\r | |
86 | #define USBSTS_USBINT bit (0) /* Interrupt due to IOC */\r | |
87 | #define USBSTS_ERROR bit (1) /* Interrupt due to error */\r | |
88 | #define USBSTS_RD bit (2) /* Resume Detect */\r | |
89 | #define USBSTS_HSE bit (3) /* Host System Error*/\r | |
90 | #define USBSTS_HCPE bit (4) /* Host Controller Process Error*/\r | |
91 | #define USBSTS_HCH bit (5) /* HC Halted */\r | |
92 | \r | |
93 | /* Interrupt enable register */\r | |
94 | #define USBINTR 4 /* Interrupt Enable Register 04-05h */\r | |
95 | #define USBINTR_TIMEOUT bit (0) /* Timeout/CRC error enable */\r | |
96 | #define USBINTR_RESUME bit (1) /* Resume interrupt enable */\r | |
97 | #define USBINTR_IOC bit (2) /* Interrupt On Complete enable */\r | |
98 | #define USBINTR_SP bit (3) /* Short packet interrupt enable */\r | |
99 | \r | |
100 | /* Frame Number Register Offset 06-08h */\r | |
101 | #define USBFRNUM 6\r | |
102 | \r | |
103 | /* Frame List Base Address Register Offset 08-0Bh */\r | |
104 | #define USBFLBASEADD 8\r | |
105 | \r | |
106 | /* Start of Frame Modify Register Offset 0Ch */\r | |
107 | #define USBSOF 0x0c\r | |
108 | \r | |
109 | /* USB port status and control registers */\r | |
110 | #define USBPORTSC1 0x10 /*Port 1 offset 10-11h */\r | |
111 | #define USBPORTSC2 0x12 /*Port 2 offset 12-13h */\r | |
112 | \r | |
113 | #define USBPORTSC_CCS bit (0) /* Current Connect Status*/\r | |
114 | #define USBPORTSC_CSC bit (1) /* Connect Status Change */\r | |
115 | #define USBPORTSC_PED bit (2) /* Port Enable / Disable */\r | |
116 | #define USBPORTSC_PEDC bit (3) /* Port Enable / Disable Change */\r | |
117 | #define USBPORTSC_LSL bit (4) /* Line Status Low bit*/\r | |
118 | #define USBPORTSC_LSH bit (5) /* Line Status High bit*/\r | |
119 | #define USBPORTSC_RD bit (6) /* Resume Detect */\r | |
120 | #define USBPORTSC_LSDA bit (8) /* Low Speed Device Attached */\r | |
121 | #define USBPORTSC_PR bit (9) /* Port Reset */\r | |
122 | #define USBPORTSC_SUSP bit (12) /* Suspend */\r | |
123 | \r | |
124 | /* PCI Configuration Registers for USB */\r | |
125 | \r | |
126 | //\r | |
127 | // Class Code Register offset\r | |
128 | //\r | |
129 | #define CLASSC 0x09\r | |
130 | //\r | |
131 | // USB IO Space Base Address Register offset\r | |
132 | //\r | |
133 | #define USBBASE 0x20\r | |
134 | \r | |
135 | //\r | |
136 | // USB legacy Support\r | |
137 | //\r | |
138 | #define USB_EMULATION 0xc0\r | |
139 | \r | |
140 | //\r | |
141 | // USB Base Class Code,Sub-Class Code and Programming Interface.\r | |
142 | //\r | |
143 | #define PCI_CLASSC_PI_UHCI 0x00\r | |
144 | \r | |
145 | #define SETUP_PACKET_ID 0x2D\r | |
146 | #define INPUT_PACKET_ID 0x69\r | |
147 | #define OUTPUT_PACKET_ID 0xE1\r | |
148 | #define ERROR_PACKET_ID 0x55\r | |
149 | \r | |
150 | //\r | |
151 | // ////////////////////////////////////////////////////////////////////////\r | |
152 | //\r | |
153 | // USB Transfer Mechanism Data Structures\r | |
154 | //\r | |
155 | //////////////////////////////////////////////////////////////////////////\r | |
156 | #pragma pack(1)\r | |
157 | //\r | |
158 | // USB Class Code structure\r | |
159 | //\r | |
160 | typedef struct {\r | |
161 | UINT8 PI;\r | |
162 | UINT8 SubClassCode;\r | |
163 | UINT8 BaseCode;\r | |
164 | } USB_CLASSC;\r | |
165 | \r | |
166 | typedef struct {\r | |
167 | UINT32 QHHorizontalTerminate : 1;\r | |
168 | UINT32 QHHorizontalQSelect : 1;\r | |
169 | UINT32 QHHorizontalRsvd : 2;\r | |
170 | UINT32 QHHorizontalPtr : 28;\r | |
171 | UINT32 QHVerticalTerminate : 1;\r | |
172 | UINT32 QHVerticalQSelect : 1;\r | |
173 | UINT32 QHVerticalRsvd : 2;\r | |
174 | UINT32 QHVerticalPtr : 28;\r | |
175 | } QUEUE_HEAD;\r | |
176 | \r | |
177 | typedef struct {\r | |
178 | UINT32 TDLinkPtrTerminate : 1;\r | |
179 | UINT32 TDLinkPtrQSelect : 1;\r | |
180 | UINT32 TDLinkPtrDepthSelect : 1;\r | |
181 | UINT32 TDLinkPtrRsvd : 1;\r | |
182 | UINT32 TDLinkPtr : 28;\r | |
183 | UINT32 TDStatusActualLength : 11;\r | |
184 | UINT32 TDStatusRsvd : 5;\r | |
185 | UINT32 TDStatus : 8;\r | |
186 | UINT32 TDStatusIOC : 1;\r | |
187 | UINT32 TDStatusIOS : 1;\r | |
188 | UINT32 TDStatusLS : 1;\r | |
189 | UINT32 TDStatusErr : 2;\r | |
190 | UINT32 TDStatusSPD : 1;\r | |
191 | UINT32 TDStatusRsvd2 : 2;\r | |
192 | UINT32 TDTokenPID : 8;\r | |
193 | UINT32 TDTokenDevAddr : 7;\r | |
194 | UINT32 TDTokenEndPt : 4;\r | |
195 | UINT32 TDTokenDataToggle : 1;\r | |
196 | UINT32 TDTokenRsvd : 1;\r | |
197 | UINT32 TDTokenMaxLen : 11;\r | |
198 | UINT32 TDBufferPtr;\r | |
199 | } TD;\r | |
200 | \r | |
201 | #pragma pack()\r | |
202 | \r | |
203 | typedef struct {\r | |
204 | QUEUE_HEAD QH;\r | |
205 | VOID *ptrNext;\r | |
206 | VOID *ptrDown;\r | |
207 | VOID *ptrNextIntQH; // for interrupt transfer's special use\r | |
208 | VOID *LoopPtr;\r | |
209 | } QH_STRUCT;\r | |
210 | \r | |
211 | typedef struct {\r | |
212 | TD TDData;\r | |
213 | UINT8 *pTDBuffer;\r | |
214 | VOID *ptrNextTD;\r | |
215 | VOID *ptrNextQH;\r | |
216 | UINT16 TDBufferLength;\r | |
217 | UINT16 reserved;\r | |
218 | } TD_STRUCT;\r | |
219 | \r | |
220 | //\r | |
221 | // ////////////////////////////////////////////////////////////////////////\r | |
222 | //\r | |
223 | // Universal Host Controller Device Data Structure\r | |
224 | //\r | |
225 | //////////////////////////////////////////////////////////////////////////\r | |
226 | #define USB_HC_DEV_FROM_THIS(a) CR (a, USB_HC_DEV, UsbHc, USB_HC_DEV_SIGNATURE)\r | |
227 | \r | |
228 | #define USB_HC_DEV_SIGNATURE EFI_SIGNATURE_32 ('u', 'h', 'c', 'i')\r | |
229 | #define INTERRUPT_LIST_SIGNATURE EFI_SIGNATURE_32 ('i', 'n', 't', 's')\r | |
230 | typedef struct {\r | |
231 | UINTN Signature;\r | |
232 | \r | |
233 | LIST_ENTRY Link;\r | |
234 | UINT8 DevAddr;\r | |
235 | UINT8 EndPoint;\r | |
236 | UINT8 DataToggle;\r | |
237 | UINT8 Reserved[5];\r | |
238 | TD_STRUCT *PtrFirstTD;\r | |
239 | QH_STRUCT *PtrQH;\r | |
240 | UINTN DataLen;\r | |
241 | UINTN PollInterval;\r | |
242 | VOID *Mapping;\r | |
243 | UINT8 *DataBuffer; // allocated host memory, not mapped memory\r | |
244 | EFI_ASYNC_USB_TRANSFER_CALLBACK InterruptCallBack;\r | |
245 | VOID *InterruptContext;\r | |
246 | } INTERRUPT_LIST;\r | |
247 | \r | |
248 | #define INTERRUPT_LIST_FROM_LINK(a) CR (a, INTERRUPT_LIST, Link, INTERRUPT_LIST_SIGNATURE)\r | |
249 | \r | |
250 | typedef struct {\r | |
251 | UINT32 FrameListPtrTerminate : 1;\r | |
252 | UINT32 FrameListPtrQSelect : 1;\r | |
253 | UINT32 FrameListRsvd : 2;\r | |
254 | UINT32 FrameListPtr : 28;\r | |
255 | \r | |
256 | } FRAMELIST_ENTRY;\r | |
257 | \r | |
258 | typedef struct _MEMORY_MANAGE_HEADER {\r | |
259 | UINT8 *BitArrayPtr;\r | |
260 | UINTN BitArraySizeInBytes;\r | |
261 | UINT8 *MemoryBlockPtr;\r | |
262 | UINTN MemoryBlockSizeInBytes;\r | |
263 | VOID *Mapping;\r | |
264 | struct _MEMORY_MANAGE_HEADER *Next;\r | |
265 | } MEMORY_MANAGE_HEADER;\r | |
266 | \r | |
267 | typedef struct {\r | |
268 | UINTN Signature;\r | |
269 | EFI_USB_HC_PROTOCOL UsbHc;\r | |
270 | EFI_PCI_IO_PROTOCOL *PciIo;\r | |
271 | \r | |
272 | //\r | |
273 | // local data\r | |
274 | //\r | |
275 | LIST_ENTRY InterruptListHead;\r | |
276 | FRAMELIST_ENTRY *FrameListEntry;\r | |
277 | VOID *FrameListMapping;\r | |
278 | MEMORY_MANAGE_HEADER *MemoryHeader;\r | |
279 | EFI_EVENT InterruptTransTimer;\r | |
280 | EFI_UNICODE_STRING_TABLE *ControllerNameTable;\r | |
281 | \r | |
282 | } USB_HC_DEV;\r | |
283 | \r | |
284 | extern EFI_DRIVER_BINDING_PROTOCOL gUhciDriverBinding;\r | |
285 | extern EFI_COMPONENT_NAME_PROTOCOL gUhciComponentName;\r | |
286 | \r | |
287 | EFI_STATUS\r | |
288 | WriteUHCCommandReg (\r | |
289 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
290 | IN UINT32 CmdAddrOffset,\r | |
291 | IN UINT16 UsbCmd\r | |
292 | );\r | |
293 | \r | |
294 | EFI_STATUS\r | |
295 | ReadUHCCommandReg (\r | |
296 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
297 | IN UINT32 CmdAddrOffset,\r | |
298 | IN OUT UINT16 *Data\r | |
299 | );\r | |
300 | \r | |
301 | EFI_STATUS\r | |
302 | WriteUHCStatusReg (\r | |
303 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
304 | IN UINT32 StatusAddrOffset,\r | |
305 | IN UINT16 UsbSts\r | |
306 | );\r | |
307 | \r | |
308 | EFI_STATUS\r | |
309 | ReadUHCStatusReg (\r | |
310 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
311 | IN UINT32 StatusAddrOffset,\r | |
312 | IN OUT UINT16 *Data\r | |
313 | );\r | |
314 | \r | |
315 | EFI_STATUS\r | |
316 | ClearStatusReg (\r | |
317 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
318 | IN UINT32 StatusAddrOffset\r | |
319 | );\r | |
320 | \r | |
321 | EFI_STATUS\r | |
322 | ReadUHCFrameNumberReg (\r | |
323 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
324 | IN UINT32 FrameNumAddrOffset,\r | |
325 | IN OUT UINT16 *Data\r | |
326 | );\r | |
327 | \r | |
328 | EFI_STATUS\r | |
329 | WriteUHCFrameListBaseReg (\r | |
330 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
331 | IN UINT32 FlBaseAddrOffset,\r | |
332 | IN UINT32 UsbFrameListBaseAddr\r | |
333 | );\r | |
334 | \r | |
335 | EFI_STATUS\r | |
336 | ReadRootPortReg (\r | |
337 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
338 | IN UINT32 PortAddrOffset,\r | |
339 | IN OUT UINT16 *Data\r | |
340 | );\r | |
341 | \r | |
342 | EFI_STATUS\r | |
343 | WriteRootPortReg (\r | |
344 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
345 | IN UINT32 PortAddrOffset,\r | |
346 | IN UINT16 ControlBits\r | |
347 | );\r | |
348 | \r | |
349 | EFI_STATUS\r | |
350 | WaitForUHCHalt (\r | |
351 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
352 | IN UINT32 StatusRegAddr,\r | |
353 | IN UINTN Timeout\r | |
354 | );\r | |
355 | \r | |
356 | BOOLEAN\r | |
357 | IsStatusOK (\r | |
358 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
359 | IN UINT32 StatusRegAddr\r | |
360 | );\r | |
361 | \r | |
362 | BOOLEAN\r | |
363 | IsHostSysOrProcessErr (\r | |
364 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
365 | IN UINT32 StatusRegAddr\r | |
366 | );\r | |
367 | \r | |
368 | //\r | |
369 | // This routine programs the USB frame number register. We assume that the\r | |
370 | // HC schedule execution is stopped.\r | |
371 | //\r | |
372 | EFI_STATUS\r | |
373 | SetFrameNumberReg (\r | |
374 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
375 | IN UINT32 FRNUMAddr,\r | |
376 | IN UINT16 Index\r | |
377 | );\r | |
378 | \r | |
379 | UINT16\r | |
380 | GetCurrentFrameNumber (\r | |
381 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
382 | IN UINT32 FRNUMAddr\r | |
383 | );\r | |
384 | \r | |
385 | EFI_STATUS\r | |
386 | SetFrameListBaseAddress (\r | |
387 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
388 | IN UINT32 FLBASEADDRReg,\r | |
389 | IN UINT32 Addr\r | |
390 | );\r | |
391 | \r | |
392 | UINT32\r | |
393 | GetFrameListBaseAddress (\r | |
394 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
395 | IN UINT32 FLBAddr\r | |
396 | );\r | |
397 | \r | |
398 | EFI_STATUS\r | |
399 | CreateFrameList (\r | |
400 | IN USB_HC_DEV *HcDev,\r | |
401 | IN UINT32 FLBASEADDRReg\r | |
402 | );\r | |
403 | \r | |
404 | EFI_STATUS\r | |
405 | FreeFrameListEntry (\r | |
406 | IN USB_HC_DEV *UhcDev\r | |
407 | );\r | |
408 | \r | |
409 | VOID\r | |
410 | InitFrameList (\r | |
411 | IN USB_HC_DEV *HcDev\r | |
412 | );\r | |
413 | \r | |
414 | \r | |
415 | EFI_STATUS\r | |
416 | CreateQH (\r | |
417 | IN USB_HC_DEV *HcDev,\r | |
418 | OUT QH_STRUCT **pptrQH\r | |
419 | );\r | |
420 | \r | |
421 | VOID\r | |
422 | SetQHHorizontalLinkPtr (\r | |
423 | IN QH_STRUCT *ptrQH,\r | |
424 | IN VOID *ptrNext\r | |
425 | );\r | |
426 | \r | |
427 | VOID *\r | |
428 | GetQHHorizontalLinkPtr (\r | |
429 | IN QH_STRUCT *ptrQH\r | |
430 | );\r | |
431 | \r | |
432 | VOID\r | |
433 | SetQHHorizontalQHorTDSelect (\r | |
434 | IN QH_STRUCT *ptrQH,\r | |
435 | IN BOOLEAN bQH\r | |
436 | );\r | |
437 | \r | |
438 | VOID\r | |
439 | SetQHHorizontalValidorInvalid (\r | |
440 | IN QH_STRUCT *ptrQH,\r | |
441 | IN BOOLEAN bValid\r | |
442 | );\r | |
443 | \r | |
444 | VOID\r | |
445 | SetQHVerticalLinkPtr (\r | |
446 | IN QH_STRUCT *ptrQH,\r | |
447 | IN VOID *ptrNext\r | |
448 | );\r | |
449 | \r | |
450 | VOID * \r | |
451 | GetQHVerticalLinkPtr (\r | |
452 | IN QH_STRUCT *ptrQH\r | |
453 | );\r | |
454 | \r | |
455 | VOID\r | |
456 | SetQHVerticalQHorTDSelect (\r | |
457 | IN QH_STRUCT *ptrQH,\r | |
458 | IN BOOLEAN bQH\r | |
459 | );\r | |
460 | \r | |
461 | BOOLEAN\r | |
462 | IsQHHorizontalQHSelect (\r | |
463 | IN QH_STRUCT *ptrQH\r | |
464 | );\r | |
465 | \r | |
466 | VOID\r | |
467 | SetQHVerticalValidorInvalid (\r | |
468 | IN QH_STRUCT *ptrQH,\r | |
469 | IN BOOLEAN bValid\r | |
470 | );\r | |
471 | \r | |
472 | BOOLEAN\r | |
473 | GetQHVerticalValidorInvalid (\r | |
474 | IN QH_STRUCT *ptrQH\r | |
475 | );\r | |
476 | \r | |
477 | EFI_STATUS\r | |
478 | AllocateTDStruct (\r | |
479 | IN USB_HC_DEV *HcDev,\r | |
480 | OUT TD_STRUCT **ppTDStruct\r | |
481 | );\r | |
482 | /*++\r | |
483 | \r | |
484 | Routine Description:\r | |
485 | \r | |
486 | Allocate TD Struct\r | |
487 | \r | |
488 | Arguments:\r | |
489 | \r | |
490 | HcDev - USB_HC_DEV\r | |
491 | ppTDStruct - place to store TD_STRUCT pointer\r | |
492 | Returns:\r | |
493 | \r | |
494 | EFI_SUCCESS\r | |
495 | \r | |
496 | --*/\r | |
497 | \r | |
498 | EFI_STATUS\r | |
499 | CreateTD (\r | |
500 | IN USB_HC_DEV *HcDev,\r | |
501 | OUT TD_STRUCT **pptrTD\r | |
502 | );\r | |
503 | /*++\r | |
504 | \r | |
505 | Routine Description:\r | |
506 | \r | |
507 | Create TD\r | |
508 | \r | |
509 | Arguments:\r | |
510 | \r | |
511 | HcDev - USB_HC_DEV\r | |
512 | pptrTD - TD_STRUCT pointer to store\r | |
513 | \r | |
514 | Returns:\r | |
515 | \r | |
516 | EFI_OUT_OF_RESOURCES - Can't allocate resources\r | |
517 | EFI_SUCCESS - Success\r | |
518 | \r | |
519 | --*/\r | |
520 | \r | |
521 | \r | |
522 | EFI_STATUS\r | |
523 | GenSetupStageTD (\r | |
524 | IN USB_HC_DEV *HcDev,\r | |
525 | IN UINT8 DevAddr,\r | |
526 | IN UINT8 Endpoint,\r | |
527 | IN BOOLEAN bSlow,\r | |
528 | IN UINT8 *pDevReq,\r | |
529 | IN UINT8 RequestLen,\r | |
530 | OUT TD_STRUCT **ppTD\r | |
531 | );\r | |
532 | /*++\r | |
533 | \r | |
534 | Routine Description:\r | |
535 | \r | |
536 | Generate Setup Stage TD\r | |
537 | \r | |
538 | Arguments:\r | |
539 | \r | |
540 | HcDev - USB_HC_DEV\r | |
541 | DevAddr - Device address\r | |
542 | Endpoint - Endpoint number \r | |
543 | bSlow - Full speed or low speed\r | |
544 | pDevReq - Device request\r | |
545 | RequestLen - Request length\r | |
546 | ppTD - TD_STRUCT to return\r | |
547 | Returns:\r | |
548 | \r | |
549 | EFI_OUT_OF_RESOURCES - Can't allocate memory\r | |
550 | EFI_SUCCESS - Success\r | |
551 | \r | |
552 | --*/\r | |
553 | \r | |
554 | EFI_STATUS\r | |
555 | GenDataTD (\r | |
556 | IN USB_HC_DEV *HcDev,\r | |
557 | IN UINT8 DevAddr,\r | |
558 | IN UINT8 Endpoint,\r | |
559 | IN UINT8 *pData,\r | |
560 | IN UINT8 Len,\r | |
561 | IN UINT8 PktID,\r | |
562 | IN UINT8 Toggle,\r | |
563 | IN BOOLEAN bSlow,\r | |
564 | OUT TD_STRUCT **ppTD\r | |
565 | );\r | |
566 | /*++\r | |
567 | \r | |
568 | Routine Description:\r | |
569 | \r | |
570 | Generate Data Stage TD\r | |
571 | \r | |
572 | Arguments:\r | |
573 | \r | |
574 | HcDev - USB_HC_DEV\r | |
575 | DevAddr - Device address\r | |
576 | Endpoint - Endpoint number \r | |
577 | pData - Data buffer \r | |
578 | Len - Data length\r | |
579 | PktID - Packet ID\r | |
580 | Toggle - Data toggle value\r | |
581 | bSlow - Full speed or low speed\r | |
582 | ppTD - TD_STRUCT to return\r | |
583 | Returns:\r | |
584 | \r | |
585 | EFI_OUT_OF_RESOURCES - Can't allocate memory\r | |
586 | EFI_SUCCESS - Success\r | |
587 | \r | |
588 | --*/\r | |
589 | \r | |
590 | EFI_STATUS\r | |
591 | CreateStatusTD (\r | |
592 | IN USB_HC_DEV *HcDev,\r | |
593 | IN UINT8 DevAddr,\r | |
594 | IN UINT8 Endpoint,\r | |
595 | IN UINT8 PktID,\r | |
596 | IN BOOLEAN bSlow,\r | |
597 | OUT TD_STRUCT **ppTD\r | |
598 | );\r | |
599 | /*++\r | |
600 | \r | |
601 | Routine Description:\r | |
602 | \r | |
603 | Generate Setup Stage TD\r | |
604 | \r | |
605 | Arguments:\r | |
606 | \r | |
607 | HcDev - USB_HC_DEV\r | |
608 | DevAddr - Device address\r | |
609 | Endpoint - Endpoint number \r | |
610 | bSlow - Full speed or low speed\r | |
611 | pDevReq - Device request\r | |
612 | RequestLen - Request length\r | |
613 | ppTD - TD_STRUCT to return\r | |
614 | Returns:\r | |
615 | \r | |
616 | EFI_OUT_OF_RESOURCES - Can't allocate memory\r | |
617 | EFI_SUCCESS - Success\r | |
618 | \r | |
619 | --*/\r | |
620 | \r | |
621 | VOID\r | |
622 | SetTDLinkPtrValidorInvalid (\r | |
623 | IN TD_STRUCT *ptrTDStruct,\r | |
624 | IN BOOLEAN bValid\r | |
625 | );\r | |
626 | \r | |
627 | VOID\r | |
628 | SetTDLinkPtrQHorTDSelect (\r | |
629 | IN TD_STRUCT *ptrTDStruct,\r | |
630 | IN BOOLEAN bQH\r | |
631 | );\r | |
632 | \r | |
633 | VOID\r | |
634 | SetTDLinkPtrDepthorBreadth (\r | |
635 | IN TD_STRUCT *ptrTDStruct,\r | |
636 | IN BOOLEAN bDepth\r | |
637 | );\r | |
638 | \r | |
639 | VOID\r | |
640 | SetTDLinkPtr (\r | |
641 | IN TD_STRUCT *ptrTDStruct,\r | |
642 | IN VOID *ptrNext\r | |
643 | );\r | |
644 | \r | |
645 | VOID *\r | |
646 | GetTDLinkPtr (\r | |
647 | IN TD_STRUCT *ptrTDStruct\r | |
648 | );\r | |
649 | \r | |
650 | VOID\r | |
651 | EnableorDisableTDShortPacket (\r | |
652 | IN TD_STRUCT *ptrTDStruct,\r | |
653 | IN BOOLEAN bEnable\r | |
654 | );\r | |
655 | \r | |
656 | VOID\r | |
657 | SetTDControlErrorCounter (\r | |
658 | IN TD_STRUCT *ptrTDStruct,\r | |
659 | IN UINT8 nMaxErrors\r | |
660 | );\r | |
661 | \r | |
662 | VOID\r | |
663 | SetTDLoworFullSpeedDevice (\r | |
664 | IN TD_STRUCT *ptrTDStruct,\r | |
665 | IN BOOLEAN bLowSpeedDevice\r | |
666 | );\r | |
667 | \r | |
668 | VOID\r | |
669 | SetTDControlIsochronousorNot (\r | |
670 | IN TD_STRUCT *ptrTDStruct,\r | |
671 | IN BOOLEAN bIsochronous\r | |
672 | );\r | |
673 | \r | |
674 | VOID\r | |
675 | SetorClearTDControlIOC (\r | |
676 | IN TD_STRUCT *ptrTDStruct,\r | |
677 | IN BOOLEAN bSet\r | |
678 | );\r | |
679 | \r | |
680 | VOID\r | |
681 | SetTDStatusActiveorInactive (\r | |
682 | IN TD_STRUCT *ptrTDStruct,\r | |
683 | IN BOOLEAN bActive\r | |
684 | );\r | |
685 | \r | |
686 | UINT16\r | |
687 | SetTDTokenMaxLength (\r | |
688 | IN TD_STRUCT *ptrTDStruct,\r | |
689 | IN UINT16 nMaxLen\r | |
690 | );\r | |
691 | \r | |
692 | VOID\r | |
693 | SetTDTokenDataToggle1 (\r | |
694 | IN TD_STRUCT *ptrTDStruct\r | |
695 | );\r | |
696 | \r | |
697 | VOID\r | |
698 | SetTDTokenDataToggle0 (\r | |
699 | IN TD_STRUCT *ptrTDStruct\r | |
700 | );\r | |
701 | \r | |
702 | UINT8\r | |
703 | GetTDTokenDataToggle (\r | |
704 | IN TD_STRUCT *ptrTDStruct\r | |
705 | );\r | |
706 | \r | |
707 | VOID\r | |
708 | SetTDTokenEndPoint (\r | |
709 | IN TD_STRUCT *ptrTDStruct,\r | |
710 | IN UINTN nEndPoint\r | |
711 | );\r | |
712 | \r | |
713 | VOID\r | |
714 | SetTDTokenDeviceAddress (\r | |
715 | IN TD_STRUCT *ptrTDStruct,\r | |
716 | IN UINTN nDevAddr\r | |
717 | );\r | |
718 | \r | |
719 | VOID\r | |
720 | SetTDTokenPacketID (\r | |
721 | IN TD_STRUCT *ptrTDStruct,\r | |
722 | IN UINT8 nPID\r | |
723 | );\r | |
724 | \r | |
725 | VOID\r | |
726 | SetTDDataBuffer (\r | |
727 | IN TD_STRUCT *ptrTDStruct\r | |
728 | );\r | |
729 | \r | |
730 | BOOLEAN\r | |
731 | IsTDStatusActive (\r | |
732 | IN TD_STRUCT *ptrTDStruct\r | |
733 | );\r | |
734 | \r | |
735 | BOOLEAN\r | |
736 | IsTDStatusStalled (\r | |
737 | IN TD_STRUCT *ptrTDStruct\r | |
738 | );\r | |
739 | \r | |
740 | BOOLEAN\r | |
741 | IsTDStatusBufferError (\r | |
742 | IN TD_STRUCT *ptrTDStruct\r | |
743 | );\r | |
744 | \r | |
745 | BOOLEAN\r | |
746 | IsTDStatusBabbleError (\r | |
747 | IN TD_STRUCT *ptrTDStruct\r | |
748 | );\r | |
749 | \r | |
750 | BOOLEAN\r | |
751 | IsTDStatusNAKReceived (\r | |
752 | IN TD_STRUCT *ptrTDStruct\r | |
753 | );\r | |
754 | \r | |
755 | BOOLEAN\r | |
756 | IsTDStatusCRCTimeOutError (\r | |
757 | IN TD_STRUCT *ptrTDStruct\r | |
758 | );\r | |
759 | \r | |
760 | BOOLEAN\r | |
761 | IsTDStatusBitStuffError (\r | |
762 | IN TD_STRUCT *ptrTDStruct\r | |
763 | );\r | |
764 | \r | |
765 | UINT16\r | |
766 | GetTDStatusActualLength (\r | |
767 | IN TD_STRUCT *ptrTDStruct\r | |
768 | );\r | |
769 | \r | |
770 | UINT16\r | |
771 | GetTDTokenMaxLength (\r | |
772 | IN TD_STRUCT *ptrTDStruct\r | |
773 | );\r | |
774 | \r | |
775 | UINT8\r | |
776 | GetTDTokenEndPoint (\r | |
777 | IN TD_STRUCT *ptrTDStruct\r | |
778 | );\r | |
779 | \r | |
780 | UINT8\r | |
781 | GetTDTokenDeviceAddress (\r | |
782 | IN TD_STRUCT *ptrTDStruct\r | |
783 | );\r | |
784 | \r | |
785 | UINT8\r | |
786 | GetTDTokenPacketID (\r | |
787 | IN TD_STRUCT *ptrTDStruct\r | |
788 | );\r | |
789 | \r | |
790 | UINT8 *\r | |
791 | GetTDDataBuffer (\r | |
792 | IN TD_STRUCT *ptrTDStruct\r | |
793 | );\r | |
794 | \r | |
795 | BOOLEAN\r | |
796 | GetTDLinkPtrValidorInvalid (\r | |
797 | IN TD_STRUCT *ptrTDStruct\r | |
798 | );\r | |
799 | \r | |
800 | UINTN\r | |
801 | CountTDsNumber (\r | |
802 | IN TD_STRUCT *ptrFirstTD\r | |
803 | );\r | |
804 | \r | |
805 | VOID\r | |
806 | LinkTDToQH (\r | |
807 | IN QH_STRUCT *ptrQH,\r | |
808 | IN TD_STRUCT *ptrTD\r | |
809 | );\r | |
810 | \r | |
811 | VOID\r | |
812 | LinkTDToTD (\r | |
813 | IN TD_STRUCT *ptrPreTD,\r | |
814 | IN TD_STRUCT *ptrTD\r | |
815 | );\r | |
816 | \r | |
817 | VOID\r | |
818 | SetorClearCurFrameListTerminate (\r | |
819 | IN FRAMELIST_ENTRY *pCurEntry,\r | |
820 | IN BOOLEAN bSet\r | |
821 | );\r | |
822 | \r | |
823 | VOID\r | |
824 | SetCurFrameListQHorTD (\r | |
825 | IN FRAMELIST_ENTRY *pCurEntry,\r | |
826 | IN BOOLEAN bQH\r | |
827 | );\r | |
828 | \r | |
829 | BOOLEAN\r | |
830 | GetCurFrameListTerminate (\r | |
831 | IN FRAMELIST_ENTRY *pCurEntry\r | |
832 | );\r | |
833 | \r | |
834 | VOID\r | |
835 | SetCurFrameListPointer (\r | |
836 | IN FRAMELIST_ENTRY *pCurEntry,\r | |
837 | IN UINT8 *ptr\r | |
838 | );\r | |
839 | \r | |
840 | VOID *\r | |
841 | GetCurFrameListPointer (\r | |
842 | IN FRAMELIST_ENTRY *pCurEntry\r | |
843 | );\r | |
844 | \r | |
845 | VOID\r | |
846 | LinkQHToFrameList (\r | |
847 | IN FRAMELIST_ENTRY *pEntry,\r | |
848 | IN UINT16 FrameListIndex,\r | |
849 | IN QH_STRUCT *ptrQH\r | |
850 | );\r | |
851 | /*++\r | |
852 | \r | |
853 | Routine Description:\r | |
854 | \r | |
855 | Link QH To Frame List\r | |
856 | \r | |
857 | Arguments:\r | |
858 | \r | |
859 | pEntry - FRAMELIST_ENTRY\r | |
860 | FrameListIndex - Frame List Index\r | |
861 | PtrQH - QH to link \r | |
862 | Returns:\r | |
863 | \r | |
864 | VOID\r | |
865 | \r | |
866 | --*/\r | |
867 | VOID\r | |
868 | DeleteQHTDs (\r | |
869 | IN FRAMELIST_ENTRY *pEntry,\r | |
870 | IN QH_STRUCT *ptrQH,\r | |
871 | IN TD_STRUCT *ptrFirstTD,\r | |
872 | IN UINT16 FrameListIndex,\r | |
873 | IN BOOLEAN SearchOther\r | |
874 | );\r | |
875 | \r | |
876 | VOID\r | |
877 | DelLinkSingleQH (\r | |
878 | IN USB_HC_DEV *HcDev,\r | |
879 | IN QH_STRUCT *ptrQH,\r | |
880 | IN UINT16 FrameListIndex,\r | |
881 | IN BOOLEAN SearchOther,\r | |
882 | IN BOOLEAN Delete\r | |
883 | );\r | |
884 | \r | |
885 | VOID\r | |
886 | DeleteQueuedTDs (\r | |
887 | IN USB_HC_DEV *HcDev,\r | |
888 | IN TD_STRUCT *ptrFirstTD\r | |
889 | );\r | |
890 | \r | |
891 | VOID\r | |
892 | InsertQHTDToINTList (\r | |
893 | IN USB_HC_DEV *HcDev,\r | |
894 | IN QH_STRUCT *ptrQH,\r | |
895 | IN TD_STRUCT *ptrFirstTD,\r | |
896 | IN UINT8 DeviceAddress,\r | |
897 | IN UINT8 EndPointAddress,\r | |
898 | IN UINT8 DataToggle,\r | |
899 | IN UINTN DataLength,\r | |
900 | IN UINTN PollingInterval,\r | |
901 | IN VOID *Mapping,\r | |
902 | IN UINT8 *DataBuffer,\r | |
903 | IN EFI_ASYNC_USB_TRANSFER_CALLBACK CallBackFunction,\r | |
904 | IN VOID *Context\r | |
905 | );\r | |
906 | /*++\r | |
907 | Routine Description:\r | |
908 | Insert QH and TD To Interrupt List\r | |
909 | Arguments:\r | |
910 | \r | |
911 | HcDev - USB_HC_DEV\r | |
912 | PtrQH - QH_STRUCT\r | |
913 | PtrFirstTD - First TD_STRUCT\r | |
914 | DeviceAddress - Device Address\r | |
915 | EndPointAddress - EndPoint Address\r | |
916 | DataToggle - Data Toggle\r | |
917 | DataLength - Data length \r | |
918 | PollingInterval - Polling Interval when inserted to frame list\r | |
919 | Mapping - Mapping alue \r | |
920 | DataBuffer - Data buffer\r | |
921 | CallBackFunction- CallBackFunction after interrupt transfeer\r | |
922 | Context - CallBackFunction Context passed as function parameter\r | |
923 | Returns:\r | |
924 | EFI_SUCCESS - Sucess\r | |
925 | EFI_INVALID_PARAMETER - Paremeter is error \r | |
926 | \r | |
927 | --*/\r | |
928 | \r | |
929 | EFI_STATUS\r | |
930 | DeleteAsyncINTQHTDs (\r | |
931 | IN USB_HC_DEV *HcDev,\r | |
932 | IN UINT8 DeviceAddress,\r | |
933 | IN UINT8 EndPointAddress,\r | |
934 | OUT UINT8 *DataToggle\r | |
935 | );\r | |
936 | /*++\r | |
937 | Routine Description:\r | |
938 | \r | |
939 | Delete Async INT QH and TDs\r | |
940 | Arguments:\r | |
941 | \r | |
942 | HcDev - USB_HC_DEV\r | |
943 | DeviceAddress - Device Address\r | |
944 | EndPointAddress - EndPoint Address\r | |
945 | DataToggle - Data Toggle\r | |
946 | \r | |
947 | Returns:\r | |
948 | EFI_SUCCESS - Sucess\r | |
949 | EFI_INVALID_PARAMETER - Paremeter is error \r | |
950 | \r | |
951 | --*/\r | |
952 | BOOLEAN\r | |
953 | CheckTDsResults (\r | |
954 | IN TD_STRUCT *ptrTD,\r | |
955 | IN UINTN RequiredLen,\r | |
956 | OUT UINT32 *Result,\r | |
957 | OUT UINTN *ErrTDPos,\r | |
958 | OUT UINTN *ActualTransferSize\r | |
959 | );\r | |
960 | /*++\r | |
961 | \r | |
962 | Routine Description:\r | |
963 | \r | |
964 | Check TDs Results\r | |
965 | \r | |
966 | Arguments:\r | |
967 | \r | |
968 | PtrTD - TD_STRUCT to check\r | |
969 | RequiredLen - Required Len\r | |
970 | Result - Transfer result\r | |
971 | ErrTDPos - Error TD Position\r | |
972 | ActualTransferSize - Actual Transfer Size\r | |
973 | \r | |
974 | Returns:\r | |
975 | \r | |
976 | TRUE - Sucess\r | |
977 | FALSE - Fail\r | |
978 | \r | |
979 | --*/\r | |
980 | VOID\r | |
981 | ExecuteAsyncINTTDs (\r | |
982 | IN USB_HC_DEV *HcDev,\r | |
983 | IN INTERRUPT_LIST *ptrList,\r | |
984 | OUT UINT32 *Result,\r | |
985 | OUT UINTN *ErrTDPos,\r | |
986 | OUT UINTN *ActualLen\r | |
987 | ) ;\r | |
988 | /*++\r | |
989 | \r | |
990 | Routine Description:\r | |
991 | \r | |
992 | Execute Async Interrupt TDs\r | |
993 | \r | |
994 | Arguments:\r | |
995 | \r | |
996 | HcDev - USB_HC_DEV\r | |
997 | PtrList - INTERRUPT_LIST\r | |
998 | Result - Transfer result\r | |
999 | ErrTDPos - Error TD Position\r | |
1000 | ActualTransferSize - Actual Transfer Size\r | |
1001 | \r | |
1002 | Returns:\r | |
1003 | \r | |
1004 | VOID\r | |
1005 | \r | |
1006 | --*/\r | |
1007 | VOID\r | |
1008 | UpdateAsyncINTQHTDs (\r | |
1009 | IN INTERRUPT_LIST *ptrList,\r | |
1010 | IN UINT32 Result,\r | |
1011 | IN UINT32 ErrTDPos\r | |
1012 | );\r | |
1013 | /*++\r | |
1014 | \r | |
1015 | Routine Description:\r | |
1016 | \r | |
1017 | Update Async Interrupt QH and TDs\r | |
1018 | \r | |
1019 | Arguments:\r | |
1020 | \r | |
1021 | PtrList - INTERRUPT_LIST\r | |
1022 | Result - Transfer reslut\r | |
1023 | ErrTDPos - Error TD Position\r | |
1024 | \r | |
1025 | Returns:\r | |
1026 | \r | |
1027 | VOID\r | |
1028 | \r | |
1029 | --*/\r | |
1030 | VOID\r | |
1031 | ReleaseInterruptList (\r | |
1032 | IN USB_HC_DEV *HcDev,\r | |
1033 | IN LIST_ENTRY *ListHead\r | |
1034 | );\r | |
1035 | /*++\r | |
1036 | \r | |
1037 | Routine Description:\r | |
1038 | \r | |
1039 | Release Interrupt List\r | |
1040 | Arguments:\r | |
1041 | \r | |
1042 | HcDev - USB_HC_DEV\r | |
1043 | ListHead - List head\r | |
1044 | \r | |
1045 | Returns:\r | |
1046 | \r | |
1047 | VOID\r | |
1048 | \r | |
1049 | --*/\r | |
1050 | EFI_STATUS\r | |
1051 | ExecuteControlTransfer (\r | |
1052 | IN USB_HC_DEV *HcDev,\r | |
1053 | IN TD_STRUCT *ptrTD,\r | |
1054 | IN UINT32 wIndex,\r | |
1055 | OUT UINTN *ActualLen,\r | |
1056 | IN UINTN TimeOut,\r | |
1057 | OUT UINT32 *TransferResult\r | |
1058 | );\r | |
1059 | /*++\r | |
1060 | \r | |
1061 | Routine Description:\r | |
1062 | \r | |
1063 | Execute Control Transfer\r | |
1064 | \r | |
1065 | Arguments:\r | |
1066 | \r | |
1067 | HcDev - USB_HC_DEV\r | |
1068 | PtrTD - TD_STRUCT\r | |
1069 | wIndex - No use\r | |
1070 | ActualLen - Actual transfered Len \r | |
1071 | TimeOut - TimeOut value in milliseconds\r | |
1072 | TransferResult - Transfer result\r | |
1073 | Returns:\r | |
1074 | \r | |
1075 | EFI_SUCCESS - Sucess\r | |
1076 | EFI_DEVICE_ERROR - Error\r | |
1077 | \r | |
1078 | \r | |
1079 | --*/\r | |
1080 | EFI_STATUS\r | |
1081 | ExecBulkorSyncInterruptTransfer (\r | |
1082 | IN USB_HC_DEV *HcDev,\r | |
1083 | IN TD_STRUCT *ptrTD,\r | |
1084 | IN UINT32 wIndex,\r | |
1085 | OUT UINTN *ActualLen,\r | |
1086 | OUT UINT8 *DataToggle,\r | |
1087 | IN UINTN TimeOut,\r | |
1088 | OUT UINT32 *TransferResult\r | |
1089 | );\r | |
1090 | /*++\r | |
1091 | \r | |
1092 | Routine Description:\r | |
1093 | \r | |
1094 | Execute Bulk or SyncInterrupt Transfer\r | |
1095 | \r | |
1096 | Arguments:\r | |
1097 | \r | |
1098 | HcDev - USB_HC_DEV\r | |
1099 | PtrTD - TD_STRUCT\r | |
1100 | wIndex - No use\r | |
1101 | ActualLen - Actual transfered Len \r | |
1102 | DataToggle - Data Toggle\r | |
1103 | TimeOut - TimeOut value in milliseconds\r | |
1104 | TransferResult - Transfer result\r | |
1105 | Returns:\r | |
1106 | \r | |
1107 | EFI_SUCCESS - Sucess\r | |
1108 | EFI_DEVICE_ERROR - Error\r | |
1109 | --*/\r | |
1110 | \r | |
1111 | EFI_STATUS\r | |
1112 | InitializeMemoryManagement (\r | |
1113 | IN USB_HC_DEV *HcDev\r | |
1114 | );\r | |
1115 | \r | |
1116 | EFI_STATUS\r | |
1117 | CreateMemoryBlock (\r | |
1118 | IN USB_HC_DEV *HcDev,\r | |
1119 | IN MEMORY_MANAGE_HEADER **MemoryHeader,\r | |
1120 | IN UINTN MemoryBlockSizeInPages\r | |
1121 | );\r | |
1122 | \r | |
1123 | EFI_STATUS\r | |
1124 | FreeMemoryHeader (\r | |
1125 | IN USB_HC_DEV *HcDev,\r | |
1126 | IN MEMORY_MANAGE_HEADER *MemoryHeader\r | |
1127 | );\r | |
1128 | \r | |
1129 | EFI_STATUS\r | |
1130 | UhciAllocatePool (\r | |
1131 | IN USB_HC_DEV *UhcDev,\r | |
1132 | IN UINT8 **Pool,\r | |
1133 | IN UINTN AllocSize\r | |
1134 | );\r | |
1135 | \r | |
1136 | VOID\r | |
1137 | UhciFreePool (\r | |
1138 | IN USB_HC_DEV *HcDev,\r | |
1139 | IN UINT8 *Pool,\r | |
1140 | IN UINTN AllocSize\r | |
1141 | );\r | |
1142 | \r | |
1143 | VOID\r | |
1144 | InsertMemoryHeaderToList (\r | |
1145 | IN MEMORY_MANAGE_HEADER *MemoryHeader,\r | |
1146 | IN MEMORY_MANAGE_HEADER *NewMemoryHeader\r | |
1147 | );\r | |
1148 | \r | |
1149 | EFI_STATUS\r | |
1150 | AllocMemInMemoryBlock (\r | |
1151 | IN MEMORY_MANAGE_HEADER *MemoryHeader,\r | |
1152 | IN VOID **Pool,\r | |
1153 | IN UINTN NumberOfMemoryUnit\r | |
1154 | );\r | |
1155 | \r | |
1156 | BOOLEAN\r | |
1157 | IsMemoryBlockEmptied (\r | |
1158 | IN MEMORY_MANAGE_HEADER *MemoryHeaderPtr\r | |
1159 | );\r | |
1160 | \r | |
1161 | VOID\r | |
1162 | DelinkMemoryBlock (\r | |
1163 | IN MEMORY_MANAGE_HEADER *FirstMemoryHeader,\r | |
1164 | IN MEMORY_MANAGE_HEADER *FreeMemoryHeader\r | |
1165 | );\r | |
1166 | \r | |
1167 | EFI_STATUS\r | |
1168 | DelMemoryManagement (\r | |
1169 | IN USB_HC_DEV *HcDev\r | |
1170 | );\r | |
1171 | \r | |
1172 | VOID\r | |
1173 | EnableMaxPacketSize (\r | |
1174 | IN USB_HC_DEV *HcDev\r | |
1175 | );\r | |
1176 | \r | |
1177 | VOID\r | |
1178 | CleanUsbTransactions (\r | |
1179 | IN USB_HC_DEV *HcDev\r | |
1180 | );\r | |
1181 | \r | |
1182 | VOID\r | |
1183 | TurnOffUSBEmulation (\r | |
1184 | IN EFI_PCI_IO_PROTOCOL *PciIo\r | |
1185 | );\r | |
1186 | \r | |
1187 | #endif\r |