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878ddf1f | 1 | /*++\r |
2 | \r | |
3 | Copyright (c) 2006, Intel Corporation \r | |
4 | All rights reserved. This program and the accompanying materials \r | |
5 | are licensed and made available under the terms and conditions of the BSD License \r | |
6 | which accompanies this distribution. The full text of the license may be found at \r | |
7 | http://opensource.org/licenses/bsd-license.php \r | |
8 | \r | |
9 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r | |
10 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r | |
11 | \r | |
12 | Module Name:\r | |
13 | \r | |
14 | tpl.c\r | |
15 | \r | |
16 | Abstract:\r | |
17 | \r | |
18 | Task priority function \r | |
19 | \r | |
20 | --*/\r | |
21 | \r | |
22 | #include <DxeMain.h>\r | |
23 | \r | |
24 | STATIC\r | |
25 | VOID\r | |
26 | CoreSetInterruptState (\r | |
27 | IN BOOLEAN Enable\r | |
28 | )\r | |
29 | /*++\r | |
30 | \r | |
31 | Routine Description:\r | |
32 | \r | |
33 | Set Interrupt State\r | |
34 | \r | |
35 | Arguments:\r | |
36 | \r | |
37 | Enable - The state of enable or disable interrupt\r | |
38 | \r | |
39 | Returns:\r | |
40 | \r | |
41 | None\r | |
42 | \r | |
43 | --*/\r | |
44 | \r | |
45 | {\r | |
46 | if (gCpu != NULL) {\r | |
47 | if (Enable) {\r | |
48 | gCpu->EnableInterrupt(gCpu);\r | |
49 | } else {\r | |
50 | gCpu->DisableInterrupt(gCpu);\r | |
51 | }\r | |
52 | }\r | |
53 | }\r | |
54 | \r | |
55 | //\r | |
56 | // Return the highest set bit\r | |
57 | //\r | |
58 | UINTN\r | |
59 | CoreHighestSetBit (\r | |
60 | IN UINTN Number\r | |
61 | )\r | |
62 | /*++\r | |
63 | \r | |
64 | Routine Description:\r | |
65 | \r | |
66 | Return the highest set bit\r | |
67 | \r | |
68 | Arguments:\r | |
69 | \r | |
70 | Number - The value to check\r | |
71 | \r | |
72 | Returns:\r | |
73 | \r | |
74 | Bit position of the highest set bit\r | |
75 | \r | |
76 | --*/\r | |
77 | {\r | |
78 | UINTN msb;\r | |
79 | \r | |
80 | msb = 31;\r | |
81 | while ((msb > 0) && ((Number & (UINTN)(1 << msb)) == 0)) {\r | |
82 | msb--;\r | |
83 | }\r | |
84 | \r | |
85 | return msb;\r | |
86 | }\r | |
87 | \r | |
88 | \r | |
89 | \r | |
90 | EFI_TPL\r | |
91 | EFIAPI\r | |
92 | CoreRaiseTpl (\r | |
93 | IN EFI_TPL NewTpl\r | |
94 | )\r | |
95 | /*++\r | |
96 | \r | |
97 | Routine Description:\r | |
98 | \r | |
99 | Raise the task priority level to the new level.\r | |
100 | High level is implemented by disabling processor interrupts.\r | |
101 | \r | |
102 | Arguments:\r | |
103 | \r | |
104 | NewTpl - New task priority level\r | |
105 | \r | |
106 | Returns:\r | |
107 | \r | |
108 | The previous task priority level\r | |
109 | \r | |
110 | --*/\r | |
111 | {\r | |
112 | EFI_TPL OldTpl;\r | |
113 | \r | |
114 | OldTpl = gEfiCurrentTpl;\r | |
115 | ASSERT (OldTpl <= NewTpl);\r | |
116 | ASSERT (VALID_TPL (NewTpl));\r | |
117 | \r | |
118 | //\r | |
119 | // If raising to high level, disable interrupts\r | |
120 | //\r | |
121 | if (NewTpl >= EFI_TPL_HIGH_LEVEL && OldTpl < EFI_TPL_HIGH_LEVEL) {\r | |
122 | CoreSetInterruptState (FALSE);\r | |
123 | }\r | |
124 | \r | |
125 | //\r | |
126 | // Set the new value\r | |
127 | //\r | |
128 | gEfiCurrentTpl = NewTpl;\r | |
129 | \r | |
130 | return OldTpl;\r | |
131 | }\r | |
132 | \r | |
133 | \r | |
134 | \r | |
135 | VOID\r | |
136 | EFIAPI\r | |
137 | CoreRestoreTpl (\r | |
138 | IN EFI_TPL NewTpl\r | |
139 | )\r | |
140 | /*++\r | |
141 | \r | |
142 | Routine Description:\r | |
143 | \r | |
144 | Lowers the task priority to the previous value. If the new \r | |
145 | priority unmasks events at a higher priority, they are dispatched.\r | |
146 | \r | |
147 | Arguments:\r | |
148 | \r | |
149 | NewTpl - New, lower, task priority\r | |
150 | \r | |
151 | Returns:\r | |
152 | \r | |
153 | None\r | |
154 | \r | |
155 | --*/\r | |
156 | {\r | |
157 | EFI_TPL OldTpl;\r | |
158 | \r | |
159 | OldTpl = gEfiCurrentTpl;\r | |
160 | ASSERT (NewTpl <= OldTpl);\r | |
161 | ASSERT (VALID_TPL (NewTpl));\r | |
162 | \r | |
163 | //\r | |
164 | // If lowering below HIGH_LEVEL, make sure\r | |
165 | // interrupts are enabled\r | |
166 | //\r | |
167 | \r | |
168 | if (OldTpl >= EFI_TPL_HIGH_LEVEL && NewTpl < EFI_TPL_HIGH_LEVEL) {\r | |
169 | gEfiCurrentTpl = EFI_TPL_HIGH_LEVEL; \r | |
170 | }\r | |
171 | \r | |
172 | //\r | |
173 | // Dispatch any pending events\r | |
174 | //\r | |
175 | \r | |
176 | while ((-2 << NewTpl) & gEventPending) {\r | |
177 | gEfiCurrentTpl = CoreHighestSetBit (gEventPending);\r | |
178 | if (gEfiCurrentTpl < EFI_TPL_HIGH_LEVEL) {\r | |
179 | CoreSetInterruptState (TRUE);\r | |
180 | }\r | |
181 | CoreDispatchEventNotifies (gEfiCurrentTpl);\r | |
182 | }\r | |
183 | \r | |
184 | //\r | |
185 | // Set the new value\r | |
186 | //\r | |
187 | \r | |
188 | gEfiCurrentTpl = NewTpl;\r | |
189 | \r | |
190 | //\r | |
191 | // If lowering below HIGH_LEVEL, make sure\r | |
192 | // interrupts are enabled\r | |
193 | //\r | |
194 | if (gEfiCurrentTpl < EFI_TPL_HIGH_LEVEL) {\r | |
195 | CoreSetInterruptState (TRUE);\r | |
196 | }\r | |
197 | \r | |
198 | }\r |