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1 | /** @file\r |
2 | *\r | |
3 | * Copyright (c) 2012-2014, ARM Limited. All rights reserved.\r | |
4 | *\r | |
5 | * This program and the accompanying materials\r | |
6 | * are licensed and made available under the terms and conditions of the BSD License\r | |
7 | * which accompanies this distribution. The full text of the license may be found at\r | |
8 | * http://opensource.org/licenses/bsd-license.php\r | |
9 | *\r | |
10 | * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
12 | *\r | |
13 | **/\r | |
14 | \r | |
15 | #ifndef __LAN9118_DXE_HW_H__\r | |
16 | #define __LAN9118_DXE_HW_H__\r | |
17 | \r | |
18 | /*------------------------------------------------------------------------------\r | |
19 | LAN9118 SMCS Registers\r | |
20 | ------------------------------------------------------------------------------*/\r | |
21 | \r | |
22 | // Base address as on the VE board\r | |
23 | #define LAN9118_BA ((UINT32) PcdGet32(PcdLan9118DxeBaseAddress))\r | |
24 | \r | |
25 | /* ------------- Tx and Rx Data and Status Memory Locations ------------------*/\r | |
26 | #define LAN9118_RX_DATA (0x00000000 + LAN9118_BA)\r | |
27 | #define LAN9118_RX_STATUS (0x00000040 + LAN9118_BA)\r | |
28 | #define LAN9118_RX_STATUS_PEEK (0x00000044 + LAN9118_BA)\r | |
29 | #define LAN9118_TX_DATA (0x00000020 + LAN9118_BA)\r | |
30 | #define LAN9118_TX_STATUS (0x00000048 + LAN9118_BA)\r | |
31 | #define LAN9118_TX_STATUS_PEEK (0x0000004C + LAN9118_BA)\r | |
32 | \r | |
33 | /* ------------- System Control and Status Registers -------------------------*/\r | |
34 | #define LAN9118_ID_REV (0x00000050 + LAN9118_BA) // Chip ID and Revision\r | |
35 | #define LAN9118_IRQ_CFG (0x00000054 + LAN9118_BA) // Interrupt Configuration\r | |
36 | #define LAN9118_INT_STS (0x00000058 + LAN9118_BA) // Interrupt Status\r | |
37 | #define LAN9118_INT_EN (0x0000005C + LAN9118_BA) // Interrupt Enable\r | |
38 | //#define LAN9118_RESERVED (0x00000060)\r | |
39 | #define LAN9118_BYTE_TEST (0x00000064 + LAN9118_BA) // Byte Order Test\r | |
40 | #define LAN9118_FIFO_INT (0x00000068 + LAN9118_BA) // FIFO Level Interrupts\r | |
41 | #define LAN9118_RX_CFG (0x0000006C + LAN9118_BA) // Receive Configuration\r | |
42 | #define LAN9118_TX_CFG (0x00000070 + LAN9118_BA) // Transmit Configuration\r | |
43 | #define LAN9118_HW_CFG (0x00000074 + LAN9118_BA) // Hardware Configuration\r | |
44 | #define LAN9118_RX_DP_CTL (0x00000078 + LAN9118_BA) // Receive Data-Path Configuration\r | |
45 | #define LAN9118_RX_FIFO_INF (0x0000007C + LAN9118_BA) // Receive FIFO Information\r | |
46 | #define LAN9118_TX_FIFO_INF (0x00000080 + LAN9118_BA) // Transmit FIFO Information\r | |
47 | #define LAN9118_PMT_CTRL (0x00000084 + LAN9118_BA) // Power Management Control\r | |
48 | #define LAN9118_GPIO_CFG (0x00000088 + LAN9118_BA) // General Purpose IO Configuration\r | |
49 | #define LAN9118_GPT_CFG (0x0000008C + LAN9118_BA) // General Purpose Timer Configuration\r | |
50 | #define LAN9118_GPT_CNT (0x00000090 + LAN9118_BA) // General Purpose Timer Current Count\r | |
51 | #define LAN9118_WORD_SWAP (0x00000098 + LAN9118_BA) // Word Swap Control\r | |
52 | #define LAN9118_FREE_RUN (0x0000009C + LAN9118_BA) // Free-Run 25MHz Counter\r | |
53 | #define LAN9118_RX_DROP (0x000000A0 + LAN9118_BA) // Receiver Dropped Frames Counter\r | |
54 | #define LAN9118_MAC_CSR_CMD (0x000000A4 + LAN9118_BA) // MAC CSR Synchronizer Command\r | |
55 | #define LAN9118_MAC_CSR_DATA (0x000000A8 + LAN9118_BA) // MAC CSR Synchronizer Data\r | |
56 | #define LAN9118_AFC_CFG (0x000000AC + LAN9118_BA) // Automatic Flow Control Configuration\r | |
57 | #define LAN9118_E2P_CMD (0x000000B0 + LAN9118_BA) // EEPROM Command\r | |
58 | #define LAN9118_E2P_DATA (0x000000B4 + LAN9118_BA) // EEPROM Data\r | |
59 | \r | |
73683a24 MR |
60 | /*\r |
61 | * Required delays following write cycles (number of BYTE_TEST reads)\r | |
62 | * Taken from Table 6.1 in Revision 1.5 (07-11-08) of the LAN9118 datasheet.\r | |
63 | * Where no delay listed, 0 has been assumed.\r | |
64 | */\r | |
65 | #define LAN9118_RX_DATA_WR_DELAY 0\r | |
66 | #define LAN9118_RX_STATUS_WR_DELAY 0\r | |
67 | #define LAN9118_RX_STATUS_PEEK_WR_DELAY 0\r | |
68 | #define LAN9118_TX_DATA_WR_DELAY 0\r | |
69 | #define LAN9118_TX_STATUS_WR_DELAY 0\r | |
70 | #define LAN9118_TX_STATUS_PEEK_WR_DELAY 0\r | |
71 | #define LAN9118_ID_REV_WR_DELAY 0\r | |
72 | #define LAN9118_IRQ_CFG_WR_DELAY 3\r | |
73 | #define LAN9118_INT_STS_WR_DELAY 2\r | |
74 | #define LAN9118_INT_EN_WR_DELAY 1\r | |
75 | #define LAN9118_BYTE_TEST_WR_DELAY 0\r | |
76 | #define LAN9118_FIFO_INT_WR_DELAY 1\r | |
77 | #define LAN9118_RX_CFG_WR_DELAY 1\r | |
78 | #define LAN9118_TX_CFG_WR_DELAY 1\r | |
79 | #define LAN9118_HW_CFG_WR_DELAY 1\r | |
80 | #define LAN9118_RX_DP_CTL_WR_DELAY 1\r | |
81 | #define LAN9118_RX_FIFO_INF_WR_DELAY 0\r | |
82 | #define LAN9118_TX_FIFO_INF_WR_DELAY 3\r | |
83 | #define LAN9118_PMT_CTRL_WR_DELAY 7\r | |
84 | #define LAN9118_GPIO_CFG_WR_DELAY 1\r | |
85 | #define LAN9118_GPT_CFG_WR_DELAY 1\r | |
86 | #define LAN9118_GPT_CNT_WR_DELAY 3\r | |
87 | #define LAN9118_WORD_SWAP_WR_DELAY 1\r | |
88 | #define LAN9118_FREE_RUN_WR_DELAY 4\r | |
89 | #define LAN9118_RX_DROP_WR_DELAY 0\r | |
90 | #define LAN9118_MAC_CSR_CMD_WR_DELAY 1\r | |
91 | #define LAN9118_MAC_CSR_DATA_WR_DELAY 1\r | |
92 | #define LAN9118_AFC_CFG_WR_DELAY 1\r | |
93 | #define LAN9118_E2P_CMD_WR_DELAY 1\r | |
94 | #define LAN9118_E2P_DATA_WR_DELAY 1\r | |
95 | \r | |
96 | /*\r | |
97 | * Required delays following read cycles (number of BYTE_TEST reads)\r | |
98 | * Taken from Table 6.2 in Revision 1.5 (07-11-08) of the LAN9118 datasheet.\r | |
99 | * Where no delay listed, 0 has been assumed.\r | |
100 | */\r | |
101 | #define LAN9118_RX_DATA_RD_DELAY 3\r | |
102 | #define LAN9118_RX_STATUS_RD_DELAY 3\r | |
103 | #define LAN9118_RX_STATUS_PEEK_RD_DELAY 0\r | |
104 | #define LAN9118_TX_DATA_RD_DELAY 0\r | |
105 | #define LAN9118_TX_STATUS_RD_DELAY 3\r | |
106 | #define LAN9118_TX_STATUS_PEEK_RD_DELAY 0\r | |
107 | #define LAN9118_ID_REV_RD_DELAY 0\r | |
108 | #define LAN9118_IRQ_CFG_RD_DELAY 0\r | |
109 | #define LAN9118_INT_STS_RD_DELAY 0\r | |
110 | #define LAN9118_INT_EN_RD_DELAY 0\r | |
111 | #define LAN9118_BYTE_TEST_RD_DELAY 0\r | |
112 | #define LAN9118_FIFO_INT_RD_DELAY 0\r | |
113 | #define LAN9118_RX_CFG_RD_DELAY 0\r | |
114 | #define LAN9118_TX_CFG_RD_DELAY 0\r | |
115 | #define LAN9118_HW_CFG_RD_DELAY 0\r | |
116 | #define LAN9118_RX_DP_CTL_RD_DELAY 0\r | |
117 | #define LAN9118_RX_FIFO_INF_RD_DELAY 0\r | |
118 | #define LAN9118_TX_FIFO_INF_RD_DELAY 0\r | |
119 | #define LAN9118_PMT_CTRL_RD_DELAY 0\r | |
120 | #define LAN9118_GPIO_CFG_RD_DELAY 0\r | |
121 | #define LAN9118_GPT_CFG_RD_DELAY 0\r | |
122 | #define LAN9118_GPT_CNT_RD_DELAY 0\r | |
123 | #define LAN9118_WORD_SWAP_RD_DELAY 0\r | |
124 | #define LAN9118_FREE_RUN_RD_DELAY 0\r | |
125 | #define LAN9118_RX_DROP_RD_DELAY 4\r | |
126 | #define LAN9118_MAC_CSR_CMD_RD_DELAY 0\r | |
127 | #define LAN9118_MAC_CSR_DATA_RD_DELAY 0\r | |
128 | #define LAN9118_AFC_CFG_RD_DELAY 0\r | |
129 | #define LAN9118_E2P_CMD_RD_DELAY 0\r | |
130 | #define LAN9118_E2P_DATA_RD_DELAY 0\r | |
46f2c53b OM |
131 | \r |
132 | // Receiver Status bits\r | |
133 | #define RXSTATUS_CRC_ERROR BIT1 // Cyclic Redundancy Check Error\r | |
134 | #define RXSTATUS_DB BIT2 // Dribbling bit: Frame had non-integer multiple of 8bits\r | |
135 | #define RXSTATUS_MII_ERROR BIT3 // Receive error during interception\r | |
136 | #define RXSTATUS_RXW_TO BIT4 // Incomming frame larger than 2kb\r | |
137 | #define RXSTATUS_FT BIT5 // 1: Ether type / 0: 802.3 type frame\r | |
138 | #define RXSTATUS_LCOLL BIT6 // Late collision detected\r | |
139 | #define RXSTATUS_FTL BIT7 // Frame longer than Ether type\r | |
140 | #define RXSTATUS_MCF BIT10 // Frame has Multicast Address\r | |
141 | #define RXSTATUS_RUNT BIT11 // Bad frame\r | |
142 | #define RXSTATUS_LE BIT12 // Actual length of frame different than it claims\r | |
143 | #define RXSTATUS_BCF BIT13 // Frame has Broadcast Address\r | |
144 | #define RXSTATUS_ES BIT15 // Reports any error from bits 1,6,7 and 11\r | |
145 | #define RXSTATUS_PL_MASK (0x3FFF0000) // Packet length bit mask\r | |
146 | #define GET_RXSTATUS_PACKET_LENGTH(RxStatus) (((RxStatus) >> 16) & 0x3FFF) // Packet length bit mask\r | |
147 | #define RXSTATUS_FILT_FAIL BIT30 // The frame failed filtering test\r | |
148 | \r | |
149 | // Transmitter Status bits\r | |
150 | #define TXSTATUS_DEF BIT0 // Packet tx was deferred\r | |
151 | #define TXSTATUS_EDEF BIT2 // Tx ended because of excessive deferral (> 24288 bit times)\r | |
152 | #define TXSTATUS_CC_MASK (0x00000078) // Collision Count (before Tx) bit mask\r | |
153 | #define TXSTATUS_ECOLL BIT8 // Tx ended because of Excessive Collisions (makes CC_MASK invalid after 16 collisions)\r | |
154 | #define TXSTATUS_LCOLL BIT9 // Packet Tx aborted after coll window of 64 bytes\r | |
155 | #define TXSTATUS_NO_CA BIT10 // Carrier signal not present during Tx (bad?)\r | |
156 | #define TXSTATUS_LOST_CA BIT11 // Lost carrier during Tx\r | |
157 | #define TXSTATUS_ES BIT15 // Reports any errors from bits 1,2,8,9,10 and 11\r | |
158 | #define TXSTATUS_PTAG_MASK (0xFFFF0000) // Mask for Unique ID of packets (So we know who the packets are for)\r | |
159 | \r | |
160 | // ID_REV register bits\r | |
e68449c9 MR |
161 | #define IDREV_ID ((Lan9118MmioRead32(LAN9118_ID_REV) & 0xFFFF0000) >> 16)\r |
162 | #define IDREV_REV (Lan9118MmioRead32(LAN9118_ID_REV) & 0x0000FFFF)\r | |
46f2c53b OM |
163 | \r |
164 | // Interrupt Config Register bits\r | |
165 | #define IRQCFG_IRQ_TYPE BIT0 // IRQ Buffer type\r | |
166 | #define IRQCFG_IRQ_POL BIT4 // IRQ Polarity\r | |
167 | #define IRQCFG_IRQ_EN BIT8 // Enable external interrupt\r | |
168 | #define IRQCFG_IRQ_INT BIT12 // State of internal interrupts line\r | |
169 | #define IRQCFG_INT_DEAS_STS BIT13 // State of deassertion interval\r | |
170 | #define IRQCFG_INT_DEAS_CLR BIT14 // Clear the deassertion counter\r | |
171 | #define IRQCFG_INT_DEAS_MASK (0xFF000000) // Interrupt deassertion interval value mask\r | |
172 | \r | |
173 | // Interrupt Status Register bits\r | |
174 | #define INSTS_GPIO_MASK (0x7) // GPIO interrupts mask\r | |
175 | #define INSTS_RSFL (0x8) // Rx Status FIFO Level reached\r | |
176 | #define INSTS_RSFF BIT4 // Rx Status FIFO full\r | |
177 | #define INSTS_RXDF_INT BIT6 // Rx Frame dropped\r | |
178 | #define INSTS_TSFL BIT7 // Tx Status FIFO Level reached\r | |
179 | #define INSTS_TSFF BIT8 // Tx Status FIFO full\r | |
180 | #define INSTS_TDFA BIT9 // Tx Data FIFO Level exceeded\r | |
181 | #define INSTS_TDFO BIT10 // Tx Data FIFO full\r | |
182 | #define INSTS_TXE BIT13 // Transmitter Error\r | |
183 | #define INSTS_RXE BIT14 // Receiver Error\r | |
184 | #define INSTS_RWT BIT15 // Packet > 2048 bytes received\r | |
185 | #define INSTS_TXSO BIT16 // Tx Status FIFO Overflow\r | |
186 | #define INSTS_PME_INT BIT17 // PME Signal detected\r | |
187 | #define INSTS_PHY_INT BIT18 // Indicates PHY Interrupt\r | |
188 | #define INSTS_GPT_INT BIT19 // GP Timer wrapped past 0xFFFF\r | |
189 | #define INSTS_RXD_INT BIT20 // Indicates that amount of data written to RX_CFG was cleared\r | |
190 | #define INSTS_TX_IOC BIT21 // Finished loading IOC flagged buffer to Tx FIFO\r | |
191 | #define INSTS_RXDFH_INT BIT23 // Rx Dropped frames went past 0x7FFFFFFF\r | |
192 | #define INSTS_RXSTOP_INT BIT24 // Rx was stopped\r | |
193 | #define INSTS_TXSTOP_INT BIT25 // Tx was stopped\r | |
194 | #define INSTS_SW_INT BIT31 // Software Interrupt occurred\r | |
195 | \r | |
196 | // Interrupt Enable Register bits\r | |
197 | \r | |
198 | \r | |
199 | // Hardware Config Register bits\r | |
200 | #define HWCFG_SRST BIT0 // Software Reset bit (SC)\r | |
201 | #define HWCFG_SRST_TO BIT1 // Software Reset Timeout bit (RO)\r | |
202 | #define HWCFG_BMODE BIT2 // 32/16 bit Mode bit (RO)\r | |
203 | #define HWCFG_TX_FIFO_SIZE_MASK (~ (UINT32)0xF0000) // Mask to Clear FIFO Size\r | |
204 | #define HWCFG_MBO BIT20 // Must Be One bit\r | |
205 | \r | |
206 | // Power Management Control Register\r | |
207 | #define MPTCTRL_READY BIT0 // Device ready indicator\r | |
208 | #define MPTCTRL_PME_EN BIT1 // Enable external PME signals\r | |
209 | #define MPTCTRL_PME_POL BIT2 // Set polarity of PME signals\r | |
210 | #define MPTCTRL_PME_IND BIT3 // Signal type of PME (refer to Spec)\r | |
211 | #define MPTCTRL_WUPS_MASK (0x18) // Wake up status indicator mask\r | |
212 | #define MPTCTRL_PME_TYPE BIT6 // PME Buffer type (Open Drain or Push-Pull)\r | |
213 | #define MPTCTRL_ED_EN BIT8 // Energy-detect enable\r | |
214 | #define MPTCTRL_WOL_EN BIT9 // Enable wake-on-lan\r | |
215 | #define MPTCTRL_PHY_RST BIT10 // Reset the PHY\r | |
216 | #define MPTCTRL_PM_MODE_MASK (BIT12 | BIT13) // Set the power mode\r | |
217 | \r | |
218 | // PHY control register bits\r | |
219 | #define PHYCR_COLL_TEST BIT7 // Collision test enable\r | |
220 | #define PHYCR_DUPLEX_MODE BIT8 // Set Duplex Mode\r | |
221 | #define PHYCR_RST_AUTO BIT9 // Restart Auto-Negotiation of Link abilities\r | |
222 | #define PHYCR_PD BIT11 // Power-Down switch\r | |
223 | #define PHYCR_AUTO_EN BIT12 // Auto-Negotiation Enable\r | |
224 | #define PHYCR_SPEED_SEL BIT13 // Link Speed Selection\r | |
225 | #define PHYCR_LOOPBK BIT14 // Set loopback mode\r | |
226 | #define PHYCR_RESET BIT15 // Do a PHY reset\r | |
227 | \r | |
228 | // PHY status register bits\r | |
229 | #define PHYSTS_EXT_CAP BIT0 // Extended Capabilities Register capability\r | |
230 | #define PHYSTS_JABBER BIT1 // Jabber condition detected\r | |
231 | #define PHYSTS_LINK_STS BIT2 // Link Status\r | |
232 | #define PHYSTS_AUTO_CAP BIT3 // Auto-Negotiation Capability\r | |
233 | #define PHYSTS_REMOTE_FAULT BIT4 // Remote fault detected\r | |
234 | #define PHYSTS_AUTO_COMP BIT5 // Auto-Negotiation Completed\r | |
235 | #define PHYSTS_10BASET_HDPLX BIT11 // 10Mbps Half-Duplex ability\r | |
236 | #define PHYSTS_10BASET_FDPLX BIT12 // 10Mbps Full-Duplex ability\r | |
237 | #define PHYSTS_100BASETX_HDPLX BIT13 // 100Mbps Half-Duplex ability\r | |
238 | #define PHYSTS_100BASETX_FDPLX BIT14 // 100Mbps Full-Duplex ability\r | |
239 | #define PHYSTS_100BASE_T4 BIT15 // Base T4 ability\r | |
240 | \r | |
241 | // PHY Auto-Negotiation advertisement\r | |
242 | #define PHYANA_SEL_MASK ((UINT32)0x1F) // Link type selector\r | |
243 | #define PHYANA_10BASET BIT5 // Advertise 10BASET capability\r | |
244 | #define PHYANA_10BASETFD BIT6 // Advertise 10BASET Full duplex capability\r | |
245 | #define PHYANA_100BASETX BIT7 // Advertise 100BASETX capability\r | |
246 | #define PHYANA_100BASETXFD BIT8 // Advertise 100 BASETX Full duplex capability\r | |
247 | #define PHYANA_PAUSE_OP_MASK (3 << 10) // Advertise PAUSE frame capability\r | |
248 | #define PHYANA_REMOTE_FAULT BIT13 // Remote fault detected\r | |
249 | \r | |
250 | \r | |
251 | // PHY Auto-Negotiation Link Partner Ability\r | |
252 | \r | |
253 | // PHY Auto-Negotiation Expansion\r | |
254 | \r | |
255 | // PHY Mode control/status\r | |
256 | \r | |
257 | // PHY Special Modes\r | |
258 | \r | |
259 | // PHY Special control/status\r | |
260 | \r | |
261 | // PHY Interrupt Source Flags\r | |
262 | \r | |
263 | // PHY Interrupt Mask\r | |
264 | \r | |
265 | // PHY Super Special control/status\r | |
266 | #define PHYSSCS_HCDSPEED_MASK (7 << 2) // Speed indication\r | |
267 | #define PHYSSCS_AUTODONE BIT12 // Auto-Negotiation Done\r | |
268 | \r | |
269 | \r | |
270 | // MAC control register bits\r | |
271 | #define MACCR_RX_EN BIT2 // Enable Receiver bit\r | |
272 | #define MACCR_TX_EN BIT3 // Enable Transmitter bit\r | |
273 | #define MACCR_DFCHK BIT5 // Deferral Check bit\r | |
274 | #define MACCR_PADSTR BIT8 // Automatic Pad Stripping bit\r | |
275 | #define MACCR_BOLMT_MASK (0xC0) // Back-Off limit mask\r | |
276 | #define MACCR_DISRTY BIT10 // Disable Transmit Retry bit\r | |
277 | #define MACCR_BCAST BIT11 // Disable Broadcast Frames bit\r | |
278 | #define MACCR_LCOLL BIT12 // Late Collision Control bit\r | |
279 | #define MACCR_HPFILT BIT13 // Hash/Perfect Filtering Mode bit\r | |
280 | #define MACCR_HO BIT15 // Hash Only Filtering Mode\r | |
281 | #define MACCR_PASSBAD BIT16 // Receive all frames that passed filter bit\r | |
282 | #define MACCR_INVFILT BIT17 // Enable Inverse Filtering bit\r | |
283 | #define MACCR_PRMS BIT18 // Promiscuous Mode bit\r | |
284 | #define MACCR_MCPAS BIT19 // Pass all Multicast packets bit\r | |
285 | #define MACCR_FDPX BIT20 // Full Duplex Mode bit\r | |
286 | #define MACCR_LOOPBK BIT21 // Loopback operation mode bit\r | |
287 | #define MACCR_RCVOWN BIT23 // Disable Receive Own frames bit\r | |
288 | #define MACCR_RX_ALL BIT31 // Receive all Packets and route to Filter\r | |
289 | \r | |
290 | // Wake-Up Control and Status Register\r | |
291 | #define WUCSR_MPEN BIT1 // Magic Packet enable (allow wake from Magic P)\r | |
292 | #define WUCSR_WUEN BIT2 // Allow remote wake up using Wake-Up Frames\r | |
293 | #define WUCSR_MPR_MASK (0x10) // Received Magic Packet\r | |
294 | #define WUCSR_WUFR_MASK (0x20) // Received Wake-Up Frame\r | |
295 | #define WUCSR_GUE BIT9 // Enable wake on global unicast frames\r | |
296 | \r | |
297 | // RX Configuration Register bits\r | |
298 | #define RXCFG_RXDOFF_MASK (0x1F00) // Rx Data Offset in Bytes\r | |
299 | #define RXCFG_RX_DUMP BIT15 // Clear Rx data and status FIFOs\r | |
300 | #define RXCFG_RX_DMA_CNT_MASK (0x0FFF0000) // Amount of data to be read from Rx FIFO\r | |
301 | #define RXCFG_RX_DMA_CNT(cnt) (((cnt) & 0xFFF) << 16) // Amount of data to be read from Rx FIFO\r | |
302 | #define RXCFG_RX_END_ALIGN_MASK (0xC0000000) // Alignment to preserve\r | |
303 | \r | |
304 | // TX Configuration Register bits\r | |
305 | #define TXCFG_STOP_TX BIT0 // Stop the transmitter\r | |
306 | #define TXCFG_TX_ON BIT1 // Start the transmitter\r | |
307 | #define TXCFG_TXSAO BIT2 // Tx Status FIFO full\r | |
308 | #define TXCFG_TXD_DUMP BIT14 // Clear Tx Data FIFO\r | |
309 | #define TXCFG_TXS_DUMP BIT15 // Clear Tx Status FIFO\r | |
310 | \r | |
311 | // Rx FIFO Information Register bits\r | |
312 | #define RXFIFOINF_RXDUSED_MASK (0xFFFF) // Rx Data FIFO Used Space\r | |
313 | #define RXFIFOINF_RXSUSED_MASK (0xFF0000) // Rx Status FIFO Used Space\r | |
314 | \r | |
315 | // Tx FIFO Information Register bits\r | |
316 | #define TXFIFOINF_TDFREE_MASK (0xFFFF) // Tx Data FIFO Free Space\r | |
317 | #define TXFIFOINF_TXSUSED_MASK (0xFF0000) // Tx Status FIFO Used Space\r | |
318 | \r | |
319 | // E2P Register\r | |
320 | #define E2P_EPC_BUSY BIT31\r | |
321 | #define E2P_EPC_CMD_READ (0)\r | |
322 | #define E2P_EPC_TIMEOUT BIT9\r | |
323 | #define E2P_EPC_MAC_ADDRESS_LOADED BIT8\r | |
324 | #define E2P_EPC_ADDRESS(address) ((address) & 0xFFFF)\r | |
325 | \r | |
326 | // GPIO Configuration register\r | |
327 | #define GPIO_GPIO0_PUSH_PULL BIT16\r | |
328 | #define GPIO_GPIO1_PUSH_PULL BIT17\r | |
329 | #define GPIO_GPIO2_PUSH_PULL BIT18\r | |
330 | #define GPIO_LED1_ENABLE BIT28\r | |
331 | #define GPIO_LED2_ENABLE BIT29\r | |
332 | #define GPIO_LED3_ENABLE BIT30\r | |
333 | \r | |
334 | // MII_ACC bits\r | |
335 | #define MII_ACC_MII_BUSY BIT0\r | |
336 | #define MII_ACC_MII_WRITE BIT1\r | |
337 | #define MII_ACC_MII_READ 0\r | |
338 | \r | |
339 | #define MII_ACC_PHY_VALUE BIT11\r | |
340 | #define MII_ACC_MII_REG_INDEX(index) (((index) & 0x1F) << 6)\r | |
341 | \r | |
342 | //\r | |
343 | // PHY Control Indexes\r | |
344 | //\r | |
345 | #define PHY_INDEX_BASIC_CTRL 0\r | |
346 | #define PHY_INDEX_BASIC_STATUS 1\r | |
347 | #define PHY_INDEX_ID1 2\r | |
348 | #define PHY_INDEX_ID2 3\r | |
349 | #define PHY_INDEX_AUTO_NEG_ADVERT 4\r | |
350 | #define PHY_INDEX_AUTO_NEG_LINK_ABILITY 5\r | |
351 | #define PHY_INDEX_AUTO_NEG_EXP 6\r | |
352 | #define PHY_INDEX_MODE 17\r | |
353 | #define PHY_INDEX_SPECIAL_MODES 18\r | |
354 | #define PHY_INDEX_SPECIAL_CTLR 27\r | |
355 | #define PHY_INDEX_INT_SRC 29\r | |
356 | #define PHY_INDEX_INT_MASK 30\r | |
357 | #define PHY_INDEX_SPECIAL_PHY_CTLR 31\r | |
358 | \r | |
359 | // Indirect MAC Indexes\r | |
360 | #define INDIRECT_MAC_INDEX_CR 1\r | |
361 | #define INDIRECT_MAC_INDEX_ADDRH 2\r | |
362 | #define INDIRECT_MAC_INDEX_ADDRL 3\r | |
363 | #define INDIRECT_MAC_INDEX_HASHH 4\r | |
364 | #define INDIRECT_MAC_INDEX_HASHL 5\r | |
365 | #define INDIRECT_MAC_INDEX_MII_ACC 6\r | |
366 | #define INDIRECT_MAC_INDEX_MII_DATA 7\r | |
367 | \r | |
368 | //\r | |
369 | // MAC CSR Synchronizer Command register\r | |
370 | //\r | |
371 | #define MAC_CSR_BUSY BIT31\r | |
372 | #define MAC_CSR_READ BIT30\r | |
373 | #define MAC_CSR_WRITE 0\r | |
374 | #define MAC_CSR_ADDR(Addr) ((Addr) & 0xFF)\r | |
375 | \r | |
376 | //\r | |
377 | // TX Packet Format\r | |
378 | //\r | |
379 | #define TX_CMD_A_COMPLETION_INT BIT31\r | |
380 | #define TX_CMD_A_FIRST_SEGMENT BIT13\r | |
381 | #define TX_CMD_A_LAST_SEGMENT BIT12\r | |
382 | #define TX_CMD_A_BUFF_SIZE(size) ((size) & 0x000003FF)\r | |
383 | #define TX_CMD_A_DATA_START_OFFSET(offset) (((offset) & 0x1F) << 16)\r | |
384 | #define TX_CMD_B_PACKET_LENGTH(size) ((size) & 0x000003FF)\r | |
385 | #define TX_CMD_B_PACKET_TAG(tag) (((tag) & 0x3FF) << 16)\r | |
386 | \r | |
387 | // Hardware Configuration Register\r | |
388 | #define HW_CFG_TX_FIFO_SIZE_MASK (0xF << 16)\r | |
389 | #define HW_CFG_TX_FIFO_SIZE(size) (((size) & 0xF) << 16)\r | |
390 | \r | |
391 | // EEPROM Definition\r | |
392 | #define EEPROM_EXTERNAL_SERIAL_EEPROM 0xA5\r | |
393 | \r | |
394 | //\r | |
395 | // Conditional compilation flags\r | |
396 | //\r | |
397 | //#define EVAL_PERFORMANCE\r | |
398 | \r | |
399 | \r | |
400 | #endif /* __LAN9118_DXE_HDR_H__ */\r |