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46f2c53b OM |
1 | /** @file\r |
2 | *\r | |
3 | * Copyright (c) 2012-2014, ARM Limited. All rights reserved.\r | |
4 | *\r | |
5 | * This program and the accompanying materials\r | |
6 | * are licensed and made available under the terms and conditions of the BSD License\r | |
7 | * which accompanies this distribution. The full text of the license may be found at\r | |
8 | * http://opensource.org/licenses/bsd-license.php\r | |
9 | *\r | |
10 | * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
12 | *\r | |
13 | **/\r | |
14 | \r | |
15 | #include "Lan9118Dxe.h"\r | |
16 | \r | |
b0fdce95 | 17 | STATIC EFI_MAC_ADDRESS mZeroMac = { { 0 } };\r |
46f2c53b OM |
18 | \r |
19 | /**\r | |
20 | This internal function reverses bits for 32bit data.\r | |
21 | \r | |
22 | @param Value The data to be reversed.\r | |
23 | \r | |
24 | @return Data reversed.\r | |
25 | \r | |
26 | **/\r | |
27 | UINT32\r | |
28 | ReverseBits (\r | |
29 | UINT32 Value\r | |
30 | )\r | |
31 | {\r | |
32 | UINTN Index;\r | |
33 | UINT32 NewValue;\r | |
34 | \r | |
35 | NewValue = 0;\r | |
36 | for (Index = 0; Index < 32; Index++) {\r | |
37 | if ((Value & (1 << Index)) != 0) {\r | |
38 | NewValue = NewValue | (1 << (31 - Index));\r | |
39 | }\r | |
40 | }\r | |
41 | \r | |
42 | return NewValue;\r | |
43 | }\r | |
44 | \r | |
45 | /*\r | |
46 | ** Create Ethernet CRC\r | |
47 | **\r | |
48 | ** INFO USED:\r | |
49 | ** 1: http://en.wikipedia.org/wiki/Cyclic_redundancy_check\r | |
50 | **\r | |
51 | ** 2: http://www.erg.abdn.ac.uk/~gorry/eg3567/dl-pages/crc.html\r | |
52 | **\r | |
53 | ** 3: http://en.wikipedia.org/wiki/Computation_of_CRC\r | |
54 | */\r | |
55 | UINT32\r | |
56 | GenEtherCrc32 (\r | |
57 | IN EFI_MAC_ADDRESS *Mac,\r | |
58 | IN UINT32 AddrLen\r | |
59 | )\r | |
60 | {\r | |
61 | INT32 Iter;\r | |
62 | UINT32 Remainder;\r | |
63 | UINT8 *Ptr;\r | |
64 | \r | |
65 | Iter = 0;\r | |
66 | Remainder = 0xFFFFFFFF; // 0xFFFFFFFF is standard seed for Ethernet\r | |
67 | \r | |
68 | // Convert Mac Address to array of bytes\r | |
69 | Ptr = (UINT8*)Mac;\r | |
70 | \r | |
71 | // Generate the Crc bit-by-bit (LSB first)\r | |
72 | while (AddrLen--) {\r | |
73 | Remainder ^= *Ptr++;\r | |
74 | for (Iter = 0;Iter < 8;Iter++) {\r | |
75 | // Check if exponent is set\r | |
76 | if (Remainder & 1) {\r | |
77 | Remainder = (Remainder >> 1) ^ CRC_POLYNOMIAL;\r | |
78 | } else {\r | |
79 | Remainder = (Remainder >> 1) ^ 0;\r | |
80 | }\r | |
81 | }\r | |
82 | }\r | |
83 | \r | |
84 | // Reverse the bits before returning (to Big Endian)\r | |
85 | //TODO: Need to be reviewed. Do we want to do a bit reverse or a byte reverse (in this case use SwapBytes32())\r | |
86 | return ReverseBits (Remainder);\r | |
87 | }\r | |
88 | \r | |
89 | // Function to read from MAC indirect registers\r | |
90 | UINT32\r | |
91 | IndirectMACRead32 (\r | |
92 | UINT32 Index\r | |
93 | )\r | |
94 | {\r | |
95 | UINT32 MacCSR;\r | |
96 | \r | |
97 | // Check index is in the range\r | |
98 | ASSERT(Index <= 12);\r | |
99 | \r | |
100 | // Wait until CSR busy bit is cleared\r | |
101 | while ((MmioRead32 (LAN9118_MAC_CSR_CMD) & MAC_CSR_BUSY) == MAC_CSR_BUSY);\r | |
102 | \r | |
103 | // Set CSR busy bit to ensure read will occur\r | |
104 | // Set the R/W bit to indicate we are reading\r | |
105 | // Set the index of CSR Address to access desired register\r | |
106 | MacCSR = MAC_CSR_BUSY | MAC_CSR_READ | MAC_CSR_ADDR(Index);\r | |
107 | \r | |
108 | // Write to the register\r | |
109 | MmioWrite32 (LAN9118_MAC_CSR_CMD, MacCSR);\r | |
110 | \r | |
111 | // Wait until CSR busy bit is cleared\r | |
112 | while ((MmioRead32 (LAN9118_MAC_CSR_CMD) & MAC_CSR_BUSY) == MAC_CSR_BUSY);\r | |
113 | \r | |
114 | // Now read from data register to get read value\r | |
115 | return MmioRead32 (LAN9118_MAC_CSR_DATA);\r | |
116 | }\r | |
117 | \r | |
118 | // Function to write to MAC indirect registers\r | |
119 | UINT32\r | |
120 | IndirectMACWrite32 (\r | |
121 | UINT32 Index,\r | |
122 | UINT32 Value\r | |
123 | )\r | |
124 | {\r | |
125 | UINT32 ValueWritten;\r | |
126 | UINT32 MacCSR;\r | |
127 | \r | |
128 | // Check index is in the range\r | |
129 | ASSERT(Index <= 12);\r | |
130 | \r | |
131 | // Wait until CSR busy bit is cleared\r | |
132 | while ((MmioRead32 (LAN9118_MAC_CSR_CMD) & MAC_CSR_BUSY) == MAC_CSR_BUSY);\r | |
133 | \r | |
134 | // Set CSR busy bit to ensure read will occur\r | |
135 | // Set the R/W bit to indicate we are writing\r | |
136 | // Set the index of CSR Address to access desired register\r | |
137 | MacCSR = MAC_CSR_BUSY | MAC_CSR_WRITE | MAC_CSR_ADDR(Index);\r | |
138 | \r | |
139 | // Now write the value to the register before issuing the write command\r | |
140 | ValueWritten = MmioWrite32 (LAN9118_MAC_CSR_DATA, Value);\r | |
141 | \r | |
142 | // Write the config to the register\r | |
143 | MmioWrite32 (LAN9118_MAC_CSR_CMD, MacCSR);\r | |
144 | \r | |
145 | // Wait until CSR busy bit is cleared\r | |
146 | while ((MmioRead32 (LAN9118_MAC_CSR_CMD) & MAC_CSR_BUSY) == MAC_CSR_BUSY);\r | |
147 | \r | |
148 | return ValueWritten;\r | |
149 | }\r | |
150 | \r | |
151 | // Function to read from MII register (PHY Access)\r | |
152 | UINT32\r | |
153 | IndirectPHYRead32 (\r | |
154 | UINT32 Index\r | |
155 | )\r | |
156 | {\r | |
157 | UINT32 ValueRead;\r | |
158 | UINT32 MiiAcc;\r | |
159 | \r | |
160 | // Check it is a valid index\r | |
161 | ASSERT(Index < 31);\r | |
162 | \r | |
163 | // Wait for busy bit to clear\r | |
164 | while ((IndirectMACRead32 (INDIRECT_MAC_INDEX_MII_ACC) & MII_ACC_MII_BUSY) == MII_ACC_MII_BUSY);\r | |
165 | \r | |
166 | // Clear the R/W bit to indicate we are reading\r | |
167 | // Set the index of the MII register\r | |
168 | // Set the PHY Address\r | |
169 | // Set the MII busy bit to allow read\r | |
170 | MiiAcc = MII_ACC_MII_READ | MII_ACC_MII_REG_INDEX(Index) | MII_ACC_PHY_VALUE | MII_ACC_MII_BUSY;\r | |
171 | \r | |
172 | // Now write this config to register\r | |
173 | IndirectMACWrite32 (INDIRECT_MAC_INDEX_MII_ACC, MiiAcc & 0xFFFF);\r | |
174 | \r | |
175 | // Wait for busy bit to clear\r | |
176 | while ((IndirectMACRead32 (INDIRECT_MAC_INDEX_MII_ACC) & MII_ACC_MII_BUSY) == MII_ACC_MII_BUSY);\r | |
177 | \r | |
178 | // Now read the value of the register\r | |
179 | ValueRead = (IndirectMACRead32 (INDIRECT_MAC_INDEX_MII_DATA) & 0xFFFF); // only lower 16 bits are valid for any PHY register\r | |
180 | \r | |
181 | return ValueRead;\r | |
182 | }\r | |
183 | \r | |
184 | \r | |
185 | // Function to write to the MII register (PHY Access)\r | |
186 | UINT32\r | |
187 | IndirectPHYWrite32 (\r | |
188 | UINT32 Index,\r | |
189 | UINT32 Value\r | |
190 | )\r | |
191 | {\r | |
192 | UINT32 MiiAcc;\r | |
193 | UINT32 ValueWritten;\r | |
194 | \r | |
195 | // Check it is a valid index\r | |
196 | ASSERT(Index < 31);\r | |
197 | \r | |
198 | // Wait for busy bit to clear\r | |
199 | while ((IndirectMACRead32 (INDIRECT_MAC_INDEX_MII_ACC) & MII_ACC_MII_BUSY) == MII_ACC_MII_BUSY);\r | |
200 | \r | |
201 | // Clear the R/W bit to indicate we are reading\r | |
202 | // Set the index of the MII register\r | |
203 | // Set the PHY Address\r | |
204 | // Set the MII busy bit to allow read\r | |
205 | MiiAcc = MII_ACC_MII_WRITE | MII_ACC_MII_REG_INDEX(Index) | MII_ACC_PHY_VALUE | MII_ACC_MII_BUSY;\r | |
206 | \r | |
207 | // Write the desired value to the register first\r | |
208 | ValueWritten = IndirectMACWrite32 (INDIRECT_MAC_INDEX_MII_DATA, (Value & 0xFFFF));\r | |
209 | \r | |
210 | // Now write the config to register\r | |
211 | IndirectMACWrite32 (INDIRECT_MAC_INDEX_MII_ACC, MiiAcc & 0xFFFF);\r | |
212 | \r | |
213 | // Wait for operation to terminate\r | |
214 | while ((IndirectMACRead32 (INDIRECT_MAC_INDEX_MII_ACC) & MII_ACC_MII_BUSY) == MII_ACC_MII_BUSY);\r | |
215 | \r | |
216 | return ValueWritten;\r | |
217 | }\r | |
218 | \r | |
219 | \r | |
220 | /* ---------------- EEPROM Operations ------------------ */\r | |
221 | \r | |
222 | \r | |
223 | // Function to read from EEPROM memory\r | |
224 | UINT32\r | |
225 | IndirectEEPROMRead32 (\r | |
226 | UINT32 Index\r | |
227 | )\r | |
228 | {\r | |
229 | UINT32 EepromCmd;\r | |
230 | \r | |
231 | // Set the busy bit to ensure read will occur\r | |
232 | EepromCmd = E2P_EPC_BUSY | E2P_EPC_CMD_READ;\r | |
233 | \r | |
234 | // Set the index to access desired EEPROM memory location\r | |
235 | EepromCmd |= E2P_EPC_ADDRESS(Index);\r | |
236 | \r | |
237 | // Write to Eeprom command register\r | |
238 | MmioWrite32 (LAN9118_E2P_CMD, EepromCmd);\r | |
a4626006 | 239 | MemoryFence();\r |
46f2c53b OM |
240 | \r |
241 | // Wait until operation has completed\r | |
242 | while (MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_BUSY);\r | |
243 | \r | |
244 | // Check that operation didn't time out\r | |
245 | if (MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_TIMEOUT) {\r | |
246 | DEBUG ((EFI_D_ERROR, "EEPROM Operation Timed out: Read command on index %x\n",Index));\r | |
247 | return 0;\r | |
248 | }\r | |
249 | \r | |
250 | // Wait until operation has completed\r | |
251 | while (MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_BUSY);\r | |
252 | \r | |
253 | // Finally read the value\r | |
254 | return MmioRead32 (LAN9118_E2P_DATA);\r | |
255 | }\r | |
256 | \r | |
257 | // Function to write to EEPROM memory\r | |
258 | UINT32\r | |
259 | IndirectEEPROMWrite32 (\r | |
260 | UINT32 Index,\r | |
261 | UINT32 Value\r | |
262 | )\r | |
263 | {\r | |
264 | UINT32 ValueWritten;\r | |
265 | UINT32 EepromCmd;\r | |
266 | \r | |
267 | ValueWritten = 0;\r | |
268 | \r | |
269 | // Read the EEPROM Command register\r | |
270 | EepromCmd = MmioRead32 (LAN9118_E2P_CMD);\r | |
271 | \r | |
272 | // Set the busy bit to ensure read will occur\r | |
273 | EepromCmd |= ((UINT32)1 << 31);\r | |
274 | \r | |
275 | // Set the EEPROM command to write(0b011)\r | |
276 | EepromCmd &= ~(7 << 28); // Clear the command first\r | |
277 | EepromCmd |= (3 << 28); // Write 011\r | |
278 | \r | |
279 | // Set the index to access desired EEPROM memory location\r | |
280 | EepromCmd |= (Index & 0xF);\r | |
281 | \r | |
282 | // Write the value to the data register first\r | |
283 | ValueWritten = MmioWrite32 (LAN9118_E2P_DATA, Value);\r | |
284 | \r | |
285 | // Write to Eeprom command register\r | |
286 | MmioWrite32 (LAN9118_E2P_CMD, EepromCmd);\r | |
a4626006 | 287 | MemoryFence();\r |
46f2c53b OM |
288 | \r |
289 | // Wait until operation has completed\r | |
290 | while (MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_BUSY);\r | |
291 | \r | |
292 | // Check that operation didn't time out\r | |
293 | if (MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_TIMEOUT) {\r | |
294 | DEBUG ((EFI_D_ERROR, "EEPROM Operation Timed out: Write command at memloc 0x%x, with value 0x%x\n",Index, Value));\r | |
295 | return 0;\r | |
296 | }\r | |
297 | \r | |
298 | // Wait until operation has completed\r | |
299 | while (MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_BUSY);\r | |
300 | \r | |
301 | return ValueWritten;\r | |
302 | }\r | |
303 | \r | |
304 | /* ---------------- General Operations ----------------- */\r | |
305 | \r | |
306 | VOID\r | |
307 | Lan9118SetMacAddress (\r | |
308 | EFI_MAC_ADDRESS *Mac,\r | |
309 | EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r | |
310 | )\r | |
311 | {\r | |
312 | IndirectMACWrite32 (INDIRECT_MAC_INDEX_ADDRL,\r | |
313 | (Mac->Addr[0] & 0xFF) |\r | |
314 | ((Mac->Addr[1] & 0xFF) << 8) |\r | |
315 | ((Mac->Addr[2] & 0xFF) << 16) |\r | |
316 | ((Mac->Addr[3] & 0xFF) << 24)\r | |
317 | );\r | |
318 | \r | |
319 | IndirectMACWrite32 (INDIRECT_MAC_INDEX_ADDRH,\r | |
320 | (UINT32)(Mac->Addr[4] & 0xFF) |\r | |
321 | ((Mac->Addr[5] & 0xFF) << 8)\r | |
322 | );\r | |
46f2c53b OM |
323 | }\r |
324 | \r | |
325 | VOID\r | |
326 | Lan9118ReadMacAddress (\r | |
327 | OUT EFI_MAC_ADDRESS *MacAddress\r | |
328 | )\r | |
329 | {\r | |
330 | UINT32 MacAddrHighValue;\r | |
331 | UINT32 MacAddrLowValue;\r | |
332 | \r | |
333 | // Read the Mac Addr high register\r | |
334 | MacAddrHighValue = (IndirectMACRead32 (INDIRECT_MAC_INDEX_ADDRH) & 0xFFFF);\r | |
335 | // Read the Mac Addr low register\r | |
336 | MacAddrLowValue = IndirectMACRead32 (INDIRECT_MAC_INDEX_ADDRL);\r | |
337 | \r | |
338 | SetMem (MacAddress, sizeof(*MacAddress), 0);\r | |
339 | MacAddress->Addr[0] = (MacAddrLowValue & 0xFF);\r | |
340 | MacAddress->Addr[1] = (MacAddrLowValue & 0xFF00) >> 8;\r | |
341 | MacAddress->Addr[2] = (MacAddrLowValue & 0xFF0000) >> 16;\r | |
342 | MacAddress->Addr[3] = (MacAddrLowValue & 0xFF000000) >> 24;\r | |
343 | MacAddress->Addr[4] = (MacAddrHighValue & 0xFF);\r | |
344 | MacAddress->Addr[5] = (MacAddrHighValue & 0xFF00) >> 8;\r | |
345 | }\r | |
346 | \r | |
347 | /*\r | |
348 | * Power up the 9118 and find its MAC address.\r | |
349 | *\r | |
350 | * This operation can be carried out when the LAN9118 is in any power state\r | |
351 | *\r | |
352 | */\r | |
353 | EFI_STATUS\r | |
354 | Lan9118Initialize (\r | |
355 | IN EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r | |
356 | )\r | |
357 | {\r | |
bbff41c1 | 358 | UINTN Retries;\r |
46f2c53b OM |
359 | UINT64 DefaultMacAddress;\r |
360 | \r | |
361 | // Attempt to wake-up the device if it is in a lower power state\r | |
362 | if (((MmioRead32 (LAN9118_PMT_CTRL) & MPTCTRL_PM_MODE_MASK) >> 12) != 0) {\r | |
363 | DEBUG ((DEBUG_NET, "Waking from reduced power state.\n"));\r | |
364 | MmioWrite32 (LAN9118_BYTE_TEST, 0xFFFFFFFF);\r | |
a4626006 | 365 | MemoryFence();\r |
46f2c53b OM |
366 | }\r |
367 | \r | |
368 | // Check that device is active\r | |
bbff41c1 RH |
369 | Retries = 20;\r |
370 | while ((MmioRead32 (LAN9118_PMT_CTRL) & MPTCTRL_READY) == 0 && --Retries) {\r | |
46f2c53b | 371 | gBS->Stall (LAN9118_STALL);\r |
a4626006 | 372 | MemoryFence();\r |
46f2c53b | 373 | }\r |
bbff41c1 | 374 | if (!Retries) {\r |
46f2c53b OM |
375 | return EFI_TIMEOUT;\r |
376 | }\r | |
377 | \r | |
378 | // Check that EEPROM isn't active\r | |
bbff41c1 RH |
379 | Retries = 20;\r |
380 | while ((MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_BUSY) && --Retries){\r | |
46f2c53b | 381 | gBS->Stall (LAN9118_STALL);\r |
a4626006 | 382 | MemoryFence();\r |
46f2c53b | 383 | }\r |
bbff41c1 | 384 | if (!Retries) {\r |
46f2c53b OM |
385 | return EFI_TIMEOUT;\r |
386 | }\r | |
387 | \r | |
388 | // Check if a MAC address was loaded from EEPROM, and if it was, set it as the\r | |
389 | // current address.\r | |
390 | if ((MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_MAC_ADDRESS_LOADED) == 0) {\r | |
391 | DEBUG ((EFI_D_ERROR, "Warning: There was an error detecting EEPROM or loading the MAC Address.\n"));\r | |
392 | \r | |
393 | // If we had an address before (set by StationAddess), continue to use it\r | |
394 | if (CompareMem (&Snp->Mode->CurrentAddress, &mZeroMac, NET_ETHER_ADDR_LEN)) {\r | |
395 | Lan9118SetMacAddress (&Snp->Mode->CurrentAddress, Snp);\r | |
396 | } else {\r | |
397 | // If there are no cached addresses, then fall back to a default\r | |
398 | DEBUG ((EFI_D_WARN, "Warning: using driver-default MAC address\n"));\r | |
399 | DefaultMacAddress = FixedPcdGet64 (PcdLan9118DefaultMacAddress);\r | |
400 | Lan9118SetMacAddress((EFI_MAC_ADDRESS *) &DefaultMacAddress, Snp);\r | |
11bbc257 | 401 | CopyMem (&Snp->Mode->CurrentAddress, &DefaultMacAddress, NET_ETHER_ADDR_LEN);\r |
46f2c53b OM |
402 | }\r |
403 | } else {\r | |
404 | // Store the MAC address that was loaded from EEPROM\r | |
405 | Lan9118ReadMacAddress (&Snp->Mode->CurrentAddress);\r | |
406 | CopyMem (&Snp->Mode->PermanentAddress, &Snp->Mode->CurrentAddress, NET_ETHER_ADDR_LEN);\r | |
407 | }\r | |
408 | \r | |
409 | // Clear and acknowledge interrupts\r | |
410 | MmioWrite32 (LAN9118_INT_EN, 0);\r | |
411 | MmioWrite32 (LAN9118_IRQ_CFG, 0);\r | |
412 | MmioWrite32 (LAN9118_INT_STS, 0xFFFFFFFF);\r | |
413 | \r | |
414 | // Do self tests here?\r | |
415 | \r | |
416 | return EFI_SUCCESS;\r | |
417 | }\r | |
418 | \r | |
419 | \r | |
420 | // Perform software reset on the LAN9118\r | |
421 | // Return 0 on success, -1 on error\r | |
422 | EFI_STATUS\r | |
423 | SoftReset (\r | |
424 | UINT32 Flags,\r | |
425 | EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r | |
426 | )\r | |
427 | {\r | |
428 | UINT32 HwConf;\r | |
429 | UINT32 ResetTime;\r | |
430 | \r | |
431 | // Initialize variable\r | |
432 | ResetTime = 0;\r | |
433 | \r | |
434 | // Stop Rx and Tx\r | |
435 | StopTx (STOP_TX_MAC | STOP_TX_CFG | STOP_TX_CLEAR, Snp);\r | |
436 | StopRx (STOP_RX_CLEAR, Snp); // Clear receiver FIFO\r | |
437 | \r | |
438 | // Issue the reset\r | |
439 | HwConf = MmioRead32 (LAN9118_HW_CFG);\r | |
440 | HwConf |= 1;\r | |
441 | \r | |
442 | // Set the Must Be One (MBO) bit\r | |
443 | if (((HwConf & HWCFG_MBO) >> 20) == 0) {\r | |
444 | HwConf |= HWCFG_MBO;\r | |
445 | }\r | |
446 | \r | |
447 | // Check that EEPROM isn't active\r | |
448 | while (MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_BUSY);\r | |
449 | \r | |
450 | // Write the configuration\r | |
451 | MmioWrite32 (LAN9118_HW_CFG, HwConf);\r | |
a4626006 | 452 | MemoryFence();\r |
46f2c53b OM |
453 | \r |
454 | // Wait for reset to complete\r | |
455 | while (MmioRead32 (LAN9118_HW_CFG) & HWCFG_SRST) {\r | |
456 | \r | |
a4626006 | 457 | MemoryFence();\r |
46f2c53b OM |
458 | gBS->Stall (LAN9118_STALL);\r |
459 | ResetTime += 1;\r | |
460 | \r | |
461 | // If time taken exceeds 100us, then there was an error condition\r | |
462 | if (ResetTime > 1000) {\r | |
463 | Snp->Mode->State = EfiSimpleNetworkStopped;\r | |
464 | return EFI_TIMEOUT;\r | |
465 | }\r | |
466 | }\r | |
467 | \r | |
468 | // Check that EEPROM isn't active\r | |
469 | while (MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_BUSY);\r | |
470 | \r | |
471 | // TODO we probably need to re-set the mac address here.\r | |
472 | \r | |
473 | // Clear and acknowledge all interrupts\r | |
474 | if (Flags & SOFT_RESET_CLEAR_INT) {\r | |
475 | MmioWrite32 (LAN9118_INT_EN, 0);\r | |
476 | MmioWrite32 (LAN9118_IRQ_CFG, 0);\r | |
477 | MmioWrite32 (LAN9118_INT_STS, 0xFFFFFFFF);\r | |
478 | }\r | |
479 | \r | |
480 | // Do self tests here?\r | |
481 | if (Flags & SOFT_RESET_SELF_TEST) {\r | |
482 | \r | |
483 | }\r | |
484 | \r | |
485 | return EFI_SUCCESS;\r | |
486 | }\r | |
487 | \r | |
488 | \r | |
489 | // Perform PHY software reset\r | |
42589b9a | 490 | EFI_STATUS\r |
46f2c53b OM |
491 | PhySoftReset (\r |
492 | UINT32 Flags,\r | |
493 | EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r | |
494 | )\r | |
495 | {\r | |
496 | UINT32 PmtCtrl = 0;\r | |
46f2c53b OM |
497 | \r |
498 | // PMT PHY reset takes precedence over BCR\r | |
499 | if (Flags & PHY_RESET_PMT) {\r | |
500 | PmtCtrl = MmioRead32 (LAN9118_PMT_CTRL);\r | |
501 | PmtCtrl |= MPTCTRL_PHY_RST;\r | |
502 | MmioWrite32 (LAN9118_PMT_CTRL,PmtCtrl);\r | |
503 | \r | |
504 | // Wait for completion\r | |
505 | while (MmioRead32 (LAN9118_PMT_CTRL) & MPTCTRL_PHY_RST) {\r | |
a4626006 | 506 | MemoryFence();\r |
46f2c53b OM |
507 | }\r |
508 | // PHY Basic Control Register reset\r | |
fffa8522 | 509 | } else if (Flags & PHY_RESET_BCR) {\r |
46f2c53b OM |
510 | IndirectPHYWrite32 (PHY_INDEX_BASIC_CTRL, PHYCR_RESET);\r |
511 | \r | |
512 | // Wait for completion\r | |
513 | while (IndirectPHYRead32 (PHY_INDEX_BASIC_CTRL) & PHYCR_RESET) {\r | |
a4626006 | 514 | MemoryFence();\r |
46f2c53b OM |
515 | }\r |
516 | }\r | |
517 | \r | |
46f2c53b OM |
518 | // Clear and acknowledge all interrupts\r |
519 | if (Flags & PHY_SOFT_RESET_CLEAR_INT) {\r | |
520 | MmioWrite32 (LAN9118_INT_EN, 0);\r | |
521 | MmioWrite32 (LAN9118_IRQ_CFG, 0);\r | |
522 | MmioWrite32 (LAN9118_INT_STS, 0xFFFFFFFF);\r | |
523 | }\r | |
524 | \r | |
42589b9a | 525 | return EFI_SUCCESS;\r |
46f2c53b OM |
526 | }\r |
527 | \r | |
528 | \r | |
529 | // Configure hardware for LAN9118\r | |
530 | EFI_STATUS\r | |
531 | ConfigureHardware (\r | |
532 | UINT32 Flags,\r | |
533 | EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r | |
534 | )\r | |
535 | {\r | |
536 | UINT32 GpioConf;\r | |
537 | \r | |
538 | // Check if we want to use LEDs on GPIO\r | |
539 | if (Flags & HW_CONF_USE_LEDS) {\r | |
540 | GpioConf = MmioRead32 (LAN9118_GPIO_CFG);\r | |
541 | \r | |
542 | // Enable GPIO as LEDs and Config as Push-Pull driver\r | |
543 | GpioConf |= GPIO_GPIO0_PUSH_PULL | GPIO_GPIO1_PUSH_PULL | GPIO_GPIO2_PUSH_PULL |\r | |
544 | GPIO_LED1_ENABLE | GPIO_LED2_ENABLE | GPIO_LED3_ENABLE;\r | |
545 | \r | |
546 | // Write the configuration\r | |
547 | MmioWrite32 (LAN9118_GPIO_CFG, GpioConf);\r | |
a4626006 | 548 | MemoryFence();\r |
46f2c53b OM |
549 | }\r |
550 | \r | |
551 | return EFI_SUCCESS;\r | |
552 | }\r | |
553 | \r | |
554 | // Configure flow control\r | |
555 | EFI_STATUS\r | |
556 | ConfigureFlow (\r | |
557 | UINT32 Flags,\r | |
558 | UINT32 HighTrig,\r | |
559 | UINT32 LowTrig,\r | |
560 | UINT32 BPDuration,\r | |
561 | EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r | |
562 | )\r | |
563 | {\r | |
564 | return EFI_SUCCESS;\r | |
565 | }\r | |
566 | \r | |
567 | // Do auto-negotiation\r | |
568 | EFI_STATUS\r | |
569 | AutoNegotiate (\r | |
570 | UINT32 Flags,\r | |
571 | EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r | |
572 | )\r | |
573 | {\r | |
574 | UINT32 PhyControl;\r | |
575 | UINT32 PhyStatus;\r | |
576 | UINT32 Features;\r | |
bbff41c1 | 577 | UINT32 Retries;\r |
46f2c53b OM |
578 | \r |
579 | // First check that auto-negotiation is supported\r | |
580 | PhyStatus = IndirectPHYRead32 (PHY_INDEX_BASIC_STATUS);\r | |
581 | if ((PhyStatus & PHYSTS_AUTO_CAP) == 0) {\r | |
582 | DEBUG ((EFI_D_ERROR, "Auto-negotiation not supported.\n"));\r | |
583 | return EFI_DEVICE_ERROR;\r | |
584 | }\r | |
585 | \r | |
586 | // Check that link is up first\r | |
587 | if ((PhyStatus & PHYSTS_LINK_STS) == 0) {\r | |
588 | // Wait until it is up or until Time Out\r | |
bbff41c1 | 589 | Retries = FixedPcdGet32 (PcdLan9118DefaultNegotiationTimeout) / LAN9118_STALL;\r |
46f2c53b | 590 | while ((IndirectPHYRead32 (PHY_INDEX_BASIC_STATUS) & PHYSTS_LINK_STS) == 0) {\r |
a4626006 | 591 | MemoryFence();\r |
46f2c53b | 592 | gBS->Stall (LAN9118_STALL);\r |
bbff41c1 RH |
593 | Retries--;\r |
594 | if (!Retries) {\r | |
46f2c53b OM |
595 | DEBUG ((EFI_D_ERROR, "Link timeout in auto-negotiation.\n"));\r |
596 | return EFI_TIMEOUT;\r | |
597 | }\r | |
598 | }\r | |
599 | }\r | |
600 | \r | |
601 | // Configure features to advertise\r | |
602 | Features = IndirectPHYRead32 (PHY_INDEX_AUTO_NEG_ADVERT);\r | |
603 | \r | |
604 | if ((Flags & AUTO_NEGOTIATE_ADVERTISE_ALL) > 0) {\r | |
605 | // Link speed capabilities\r | |
606 | Features |= (PHYANA_10BASET | PHYANA_10BASETFD | PHYANA_100BASETX | PHYANA_100BASETXFD);\r | |
607 | \r | |
608 | // Pause frame capabilities\r | |
609 | Features &= ~(PHYANA_PAUSE_OP_MASK);\r | |
610 | Features |= 3 << 10;\r | |
611 | }\r | |
612 | \r | |
613 | // Write the features\r | |
614 | IndirectPHYWrite32 (PHY_INDEX_AUTO_NEG_ADVERT, Features);\r | |
615 | \r | |
616 | // Read control register\r | |
617 | PhyControl = IndirectPHYRead32 (PHY_INDEX_BASIC_CTRL);\r | |
618 | \r | |
619 | // Enable Auto-Negotiation\r | |
620 | if ((PhyControl & PHYCR_AUTO_EN) == 0) {\r | |
621 | PhyControl |= PHYCR_AUTO_EN;\r | |
622 | }\r | |
623 | \r | |
624 | // Restart auto-negotiation\r | |
625 | PhyControl |= PHYCR_RST_AUTO;\r | |
626 | \r | |
627 | // Enable collision test if required to do so\r | |
628 | if (Flags & AUTO_NEGOTIATE_COLLISION_TEST) {\r | |
629 | PhyControl |= PHYCR_COLL_TEST;\r | |
630 | } else {\r | |
631 | PhyControl &= ~ PHYCR_COLL_TEST;\r | |
632 | }\r | |
633 | \r | |
634 | // Write this configuration\r | |
635 | IndirectPHYWrite32 (PHY_INDEX_BASIC_CTRL, PhyControl);\r | |
636 | \r | |
637 | // Wait until process has completed\r | |
638 | while ((IndirectPHYRead32 (PHY_INDEX_BASIC_STATUS) & PHYSTS_AUTO_COMP) == 0);\r | |
639 | \r | |
640 | return EFI_SUCCESS;\r | |
641 | }\r | |
642 | \r | |
643 | // Check the Link Status and take appropriate action\r | |
644 | EFI_STATUS\r | |
645 | CheckLinkStatus (\r | |
646 | UINT32 Flags,\r | |
647 | EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r | |
648 | )\r | |
649 | {\r | |
650 | // Get the PHY Status\r | |
651 | UINT32 PhyBStatus = IndirectPHYRead32 (PHY_INDEX_BASIC_STATUS);\r | |
652 | \r | |
653 | if (PhyBStatus & PHYSTS_LINK_STS) {\r | |
654 | return EFI_SUCCESS;\r | |
655 | } else {\r | |
656 | return EFI_DEVICE_ERROR;\r | |
657 | }\r | |
658 | }\r | |
659 | \r | |
660 | // Stop the transmitter\r | |
661 | EFI_STATUS\r | |
662 | StopTx (\r | |
663 | UINT32 Flags,\r | |
664 | EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r | |
665 | )\r | |
666 | {\r | |
667 | UINT32 MacCsr;\r | |
668 | UINT32 TxCfg;\r | |
669 | \r | |
670 | MacCsr = 0;\r | |
671 | TxCfg = 0;\r | |
672 | \r | |
673 | // Check if we want to clear tx\r | |
674 | if (Flags & STOP_TX_CLEAR) {\r | |
675 | TxCfg = MmioRead32 (LAN9118_TX_CFG);\r | |
676 | TxCfg |= TXCFG_TXS_DUMP | TXCFG_TXD_DUMP;\r | |
677 | MmioWrite32 (LAN9118_TX_CFG, TxCfg);\r | |
a4626006 | 678 | MemoryFence();\r |
46f2c53b OM |
679 | }\r |
680 | \r | |
681 | // Check if already stopped\r | |
682 | if (Flags & STOP_TX_MAC) {\r | |
683 | MacCsr = IndirectMACRead32 (INDIRECT_MAC_INDEX_CR);\r | |
684 | \r | |
685 | if (MacCsr & MACCR_TX_EN) {\r | |
686 | MacCsr &= ~MACCR_TX_EN;\r | |
687 | IndirectMACWrite32 (INDIRECT_MAC_INDEX_CR, MacCsr);\r | |
688 | }\r | |
689 | }\r | |
690 | \r | |
691 | if (Flags & STOP_TX_CFG) {\r | |
692 | TxCfg = MmioRead32 (LAN9118_TX_CFG);\r | |
693 | \r | |
694 | if (TxCfg & TXCFG_TX_ON) {\r | |
695 | TxCfg |= TXCFG_STOP_TX;\r | |
696 | MmioWrite32 (LAN9118_TX_CFG, TxCfg);\r | |
a4626006 | 697 | MemoryFence();\r |
46f2c53b OM |
698 | \r |
699 | // Wait for Tx to finish transmitting\r | |
700 | while (MmioRead32 (LAN9118_TX_CFG) & TXCFG_STOP_TX);\r | |
701 | }\r | |
702 | }\r | |
703 | \r | |
704 | return EFI_SUCCESS;\r | |
705 | }\r | |
706 | \r | |
707 | // Stop the receiver\r | |
708 | EFI_STATUS\r | |
709 | StopRx (\r | |
710 | UINT32 Flags,\r | |
711 | EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r | |
712 | )\r | |
713 | {\r | |
714 | UINT32 MacCsr;\r | |
715 | UINT32 RxCfg;\r | |
716 | \r | |
717 | RxCfg = 0;\r | |
718 | \r | |
719 | // Check if already stopped\r | |
720 | MacCsr = IndirectMACRead32 (INDIRECT_MAC_INDEX_CR);\r | |
721 | \r | |
722 | if (MacCsr & MACCR_RX_EN) {\r | |
723 | MacCsr &= ~ MACCR_RX_EN;\r | |
724 | IndirectMACWrite32 (INDIRECT_MAC_INDEX_CR, MacCsr);\r | |
725 | }\r | |
726 | \r | |
727 | // Check if we want to clear receiver FIFOs\r | |
728 | if (Flags & STOP_RX_CLEAR) {\r | |
729 | RxCfg = MmioRead32 (LAN9118_RX_CFG);\r | |
730 | RxCfg |= RXCFG_RX_DUMP;\r | |
731 | MmioWrite32 (LAN9118_RX_CFG, RxCfg);\r | |
a4626006 | 732 | MemoryFence();\r |
46f2c53b OM |
733 | \r |
734 | while (MmioRead32 (LAN9118_RX_CFG) & RXCFG_RX_DUMP);\r | |
735 | }\r | |
736 | \r | |
737 | return EFI_SUCCESS;\r | |
738 | }\r | |
739 | \r | |
740 | // Start the transmitter\r | |
741 | EFI_STATUS\r | |
742 | StartTx (\r | |
743 | UINT32 Flags,\r | |
744 | EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r | |
745 | )\r | |
746 | {\r | |
747 | UINT32 MacCsr;\r | |
748 | UINT32 TxCfg;\r | |
749 | \r | |
750 | MacCsr = 0;\r | |
751 | TxCfg = 0;\r | |
752 | \r | |
753 | // Check if we want to clear tx\r | |
754 | if (Flags & START_TX_CLEAR) {\r | |
755 | TxCfg = MmioRead32 (LAN9118_TX_CFG);\r | |
756 | TxCfg |= TXCFG_TXS_DUMP | TXCFG_TXD_DUMP;\r | |
757 | MmioWrite32 (LAN9118_TX_CFG, TxCfg);\r | |
a4626006 | 758 | MemoryFence();\r |
46f2c53b OM |
759 | }\r |
760 | \r | |
761 | // Check if tx was started from MAC and enable if not\r | |
762 | if (Flags & START_TX_MAC) {\r | |
763 | MacCsr = IndirectMACRead32 (INDIRECT_MAC_INDEX_CR);\r | |
a4626006 | 764 | MemoryFence();\r |
46f2c53b OM |
765 | if ((MacCsr & MACCR_TX_EN) == 0) {\r |
766 | MacCsr |= MACCR_TX_EN;\r | |
767 | IndirectMACWrite32 (INDIRECT_MAC_INDEX_CR, MacCsr);\r | |
a4626006 | 768 | MemoryFence();\r |
46f2c53b OM |
769 | }\r |
770 | }\r | |
771 | \r | |
772 | // Check if tx was started from TX_CFG and enable if not\r | |
773 | if (Flags & START_TX_CFG) {\r | |
774 | TxCfg = MmioRead32 (LAN9118_TX_CFG);\r | |
a4626006 | 775 | MemoryFence();\r |
46f2c53b OM |
776 | if ((TxCfg & TXCFG_TX_ON) == 0) {\r |
777 | TxCfg |= TXCFG_TX_ON;\r | |
778 | MmioWrite32 (LAN9118_TX_CFG, TxCfg);\r | |
a4626006 | 779 | MemoryFence();\r |
46f2c53b OM |
780 | }\r |
781 | }\r | |
782 | \r | |
783 | // Set the tx data trigger level\r | |
784 | \r | |
785 | return EFI_SUCCESS;\r | |
786 | }\r | |
787 | \r | |
788 | // Start the receiver\r | |
789 | EFI_STATUS\r | |
790 | StartRx (\r | |
791 | UINT32 Flags,\r | |
792 | EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r | |
793 | )\r | |
794 | {\r | |
795 | UINT32 MacCsr;\r | |
796 | UINT32 RxCfg;\r | |
797 | \r | |
798 | RxCfg = 0;\r | |
799 | \r | |
800 | // Check if already started\r | |
801 | MacCsr = IndirectMACRead32 (INDIRECT_MAC_INDEX_CR);\r | |
802 | \r | |
803 | if ((MacCsr & MACCR_RX_EN) == 0) {\r | |
804 | // Check if we want to clear receiver FIFOs before starting\r | |
805 | if (Flags & START_RX_CLEAR) {\r | |
806 | RxCfg = MmioRead32 (LAN9118_RX_CFG);\r | |
807 | RxCfg |= RXCFG_RX_DUMP;\r | |
808 | MmioWrite32 (LAN9118_RX_CFG, RxCfg);\r | |
a4626006 | 809 | MemoryFence();\r |
46f2c53b OM |
810 | \r |
811 | while (MmioRead32 (LAN9118_RX_CFG) & RXCFG_RX_DUMP);\r | |
812 | }\r | |
813 | \r | |
814 | MacCsr |= MACCR_RX_EN;\r | |
815 | IndirectMACWrite32 (INDIRECT_MAC_INDEX_CR, MacCsr);\r | |
a4626006 | 816 | MemoryFence();\r |
46f2c53b OM |
817 | }\r |
818 | \r | |
819 | return EFI_SUCCESS;\r | |
820 | }\r | |
821 | \r | |
822 | // Check Tx Data available space\r | |
823 | UINT32\r | |
824 | TxDataFreeSpace (\r | |
825 | UINT32 Flags,\r | |
826 | EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r | |
827 | )\r | |
828 | {\r | |
829 | UINT32 TxInf;\r | |
830 | UINT32 FreeSpace;\r | |
831 | \r | |
832 | // Get the amount of free space from information register\r | |
833 | TxInf = MmioRead32 (LAN9118_TX_FIFO_INF);\r | |
834 | FreeSpace = (TxInf & TXFIFOINF_TDFREE_MASK);\r | |
835 | \r | |
836 | return FreeSpace; // Value in bytes\r | |
837 | }\r | |
838 | \r | |
839 | // Check Tx Status used space\r | |
840 | UINT32\r | |
841 | TxStatusUsedSpace (\r | |
842 | UINT32 Flags,\r | |
843 | EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r | |
844 | )\r | |
845 | {\r | |
846 | UINT32 TxInf;\r | |
847 | UINT32 UsedSpace;\r | |
848 | \r | |
849 | // Get the amount of used space from information register\r | |
850 | TxInf = MmioRead32 (LAN9118_TX_FIFO_INF);\r | |
851 | UsedSpace = (TxInf & TXFIFOINF_TXSUSED_MASK) >> 16;\r | |
852 | \r | |
853 | return UsedSpace << 2; // Value in bytes\r | |
854 | }\r | |
855 | \r | |
856 | // Check Rx Data used space\r | |
857 | UINT32\r | |
858 | RxDataUsedSpace (\r | |
859 | UINT32 Flags,\r | |
860 | EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r | |
861 | )\r | |
862 | {\r | |
863 | UINT32 RxInf;\r | |
864 | UINT32 UsedSpace;\r | |
865 | \r | |
866 | // Get the amount of used space from information register\r | |
867 | RxInf = MmioRead32 (LAN9118_RX_FIFO_INF);\r | |
868 | UsedSpace = (RxInf & RXFIFOINF_RXDUSED_MASK);\r | |
869 | \r | |
870 | return UsedSpace; // Value in bytes (rounded up to nearest DWORD)\r | |
871 | }\r | |
872 | \r | |
873 | // Check Rx Status used space\r | |
874 | UINT32\r | |
875 | RxStatusUsedSpace (\r | |
876 | UINT32 Flags,\r | |
877 | EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r | |
878 | )\r | |
879 | {\r | |
880 | UINT32 RxInf;\r | |
881 | UINT32 UsedSpace;\r | |
882 | \r | |
883 | // Get the amount of used space from information register\r | |
884 | RxInf = MmioRead32 (LAN9118_RX_FIFO_INF);\r | |
885 | UsedSpace = (RxInf & RXFIFOINF_RXSUSED_MASK) >> 16;\r | |
886 | \r | |
887 | return UsedSpace << 2; // Value in bytes\r | |
888 | }\r | |
889 | \r | |
890 | \r | |
891 | // Change the allocation of FIFOs\r | |
892 | EFI_STATUS\r | |
893 | ChangeFifoAllocation (\r | |
894 | IN UINT32 Flags,\r | |
895 | IN OUT UINTN *TxDataSize OPTIONAL,\r | |
896 | IN OUT UINTN *RxDataSize OPTIONAL,\r | |
897 | IN OUT UINT32 *TxStatusSize OPTIONAL,\r | |
898 | IN OUT UINT32 *RxStatusSize OPTIONAL,\r | |
899 | IN OUT EFI_SIMPLE_NETWORK_PROTOCOL *Snp\r | |
900 | )\r | |
901 | {\r | |
902 | UINT32 HwConf;\r | |
903 | UINT32 TxFifoOption;\r | |
904 | \r | |
905 | // Check that desired sizes don't exceed limits\r | |
906 | if (*TxDataSize > TX_FIFO_MAX_SIZE)\r | |
907 | return EFI_INVALID_PARAMETER;\r | |
908 | \r | |
909 | #if defined(RX_FIFO_MIN_SIZE) && defined(RX_FIFO_MAX_SIZE)\r | |
910 | if (*RxDataSize > RX_FIFO_MAX_SIZE) {\r | |
911 | return EFI_INVALID_PARAMETER;\r | |
912 | }\r | |
913 | #endif\r | |
914 | \r | |
915 | if (Flags & ALLOC_USE_DEFAULT) {\r | |
916 | return EFI_SUCCESS;\r | |
917 | }\r | |
918 | \r | |
919 | // If we use the FIFOs (always use this first)\r | |
920 | if (Flags & ALLOC_USE_FIFOS) {\r | |
921 | // Read the current value of allocation\r | |
922 | HwConf = MmioRead32 (LAN9118_HW_CFG);\r | |
923 | TxFifoOption = (HwConf >> 16) & 0xF;\r | |
924 | \r | |
925 | // Choose the correct size (always use larger than requested if possible)\r | |
926 | if (*TxDataSize < TX_FIFO_MIN_SIZE) {\r | |
927 | *TxDataSize = TX_FIFO_MIN_SIZE;\r | |
928 | *RxDataSize = 13440;\r | |
929 | *RxStatusSize = 896;\r | |
930 | TxFifoOption = 2;\r | |
931 | } else if ((*TxDataSize > TX_FIFO_MIN_SIZE) && (*TxDataSize <= 2560)) {\r | |
932 | *TxDataSize = 2560;\r | |
933 | *RxDataSize = 12480;\r | |
934 | *RxStatusSize = 832;\r | |
935 | TxFifoOption = 3;\r | |
936 | } else if ((*TxDataSize > 2560) && (*TxDataSize <= 3584)) {\r | |
937 | *TxDataSize = 3584;\r | |
938 | *RxDataSize = 11520;\r | |
939 | *RxStatusSize = 768;\r | |
940 | TxFifoOption = 4;\r | |
941 | } else if ((*TxDataSize > 3584) && (*TxDataSize <= 4608)) { // default option\r | |
942 | *TxDataSize = 4608;\r | |
943 | *RxDataSize = 10560;\r | |
944 | *RxStatusSize = 704;\r | |
945 | TxFifoOption = 5;\r | |
946 | } else if ((*TxDataSize > 4608) && (*TxDataSize <= 5632)) {\r | |
947 | *TxDataSize = 5632;\r | |
948 | *RxDataSize = 9600;\r | |
949 | *RxStatusSize = 640;\r | |
950 | TxFifoOption = 6;\r | |
951 | } else if ((*TxDataSize > 5632) && (*TxDataSize <= 6656)) {\r | |
952 | *TxDataSize = 6656;\r | |
953 | *RxDataSize = 8640;\r | |
954 | *RxStatusSize = 576;\r | |
955 | TxFifoOption = 7;\r | |
956 | } else if ((*TxDataSize > 6656) && (*TxDataSize <= 7680)) {\r | |
957 | *TxDataSize = 7680;\r | |
958 | *RxDataSize = 7680;\r | |
959 | *RxStatusSize = 512;\r | |
960 | TxFifoOption = 8;\r | |
961 | } else if ((*TxDataSize > 7680) && (*TxDataSize <= 8704)) {\r | |
962 | *TxDataSize = 8704;\r | |
963 | *RxDataSize = 6720;\r | |
964 | *RxStatusSize = 448;\r | |
965 | TxFifoOption = 9;\r | |
966 | } else if ((*TxDataSize > 8704) && (*TxDataSize <= 9728)) {\r | |
967 | *TxDataSize = 9728;\r | |
968 | *RxDataSize = 5760;\r | |
969 | *RxStatusSize = 384;\r | |
970 | TxFifoOption = 10;\r | |
971 | } else if ((*TxDataSize > 9728) && (*TxDataSize <= 10752)) {\r | |
972 | *TxDataSize = 10752;\r | |
973 | *RxDataSize = 4800;\r | |
974 | *RxStatusSize = 320;\r | |
975 | TxFifoOption = 11;\r | |
976 | } else if ((*TxDataSize > 10752) && (*TxDataSize <= 11776)) {\r | |
977 | *TxDataSize = 11776;\r | |
978 | *RxDataSize = 3840;\r | |
979 | *RxStatusSize = 256;\r | |
980 | TxFifoOption = 12;\r | |
981 | } else if ((*TxDataSize > 11776) && (*TxDataSize <= 12800)) {\r | |
982 | *TxDataSize = 12800;\r | |
983 | *RxDataSize = 2880;\r | |
984 | *RxStatusSize = 192;\r | |
985 | TxFifoOption = 13;\r | |
986 | } else if ((*TxDataSize > 12800) && (*TxDataSize <= 13824)) {\r | |
987 | *TxDataSize = 13824;\r | |
988 | *RxDataSize = 1920;\r | |
989 | *RxStatusSize = 128;\r | |
990 | TxFifoOption = 14;\r | |
991 | }\r | |
992 | } else {\r | |
993 | ASSERT(0); // Untested code path\r | |
994 | HwConf = 0;\r | |
995 | TxFifoOption = 0;\r | |
996 | }\r | |
997 | \r | |
998 | // Do we need DMA?\r | |
999 | if (Flags & ALLOC_USE_DMA) {\r | |
1000 | return EFI_UNSUPPORTED; // Unsupported as of now\r | |
1001 | }\r | |
1002 | // Clear and assign the new size option\r | |
1003 | HwConf &= ~(0xF0000);\r | |
1004 | HwConf |= ((TxFifoOption & 0xF) << 16);\r | |
1005 | MmioWrite32 (LAN9118_HW_CFG, HwConf);\r | |
a4626006 | 1006 | MemoryFence();\r |
46f2c53b OM |
1007 | \r |
1008 | return EFI_SUCCESS;\r | |
1009 | }\r |