[mirror_edk2.git] / IntelFrameworkModulePkg / Bus / Isa / IsaFloppyPei / Fdc.h

/** @file\r
Definition of FDC registers and structures.\r
\r
Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
\r
SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
#ifndef _PEI_RECOVERY_FDC_H_\r
#define _PEI_RECOVERY_FDC_H_\r
\r
//\r
// FDC Registers\r
//\r
#define FDC_REGISTER_DOR  2 //Digital Output Register\r
#define FDC_REGISTER_MSR  4 //Main Status Register\r
#define FDC_REGISTER_DTR  5 //Data Register\r
#define FDC_REGISTER_CCR  7 //Configuration Control Register(data rate select)\r
#define FDC_REGISTER_DIR  7 //Digital Input Register(diskchange)\r
//\r
// FDC Register Bit Definitions\r
//\r
//\r
// Digital Out Register(WO)\r
//\r
#define SELECT_DRV      BIT0  // Select Drive: 0=A 1=B\r
#define RESET_FDC       BIT2  // Reset FDC\r
#define INT_DMA_ENABLE  BIT3  // Enable Int & DMA\r
#define DRVA_MOTOR_ON   BIT4  // Turn On Drive A Motor\r
#define DRVB_MOTOR_ON   BIT5  // Turn On Drive B Motor\r
//\r
// Main Status Register(RO)\r
//\r
#define MSR_DAB BIT0  // Drive A Busy\r
#define MSR_DBB BIT1  // Drive B Busy\r
#define MSR_CB  BIT4  // FDC Busy\r
#define MSR_NDM BIT5  // Non-DMA Mode\r
#define MSR_DIO BIT6  // Data Input/Output\r
#define MSR_RQM BIT7  // Request For Master\r
//\r
// Configuration Control Register(WO)\r
//\r
#define CCR_DRC (BIT0 | BIT1) // Data Rate select\r
//\r
// Digital Input Register(RO)\r
//\r
#define DIR_DCL     BIT7  // Disk change line\r
#define DRC_500KBS  0x0   // 500K\r
#define DRC_300KBS  0x01  // 300K\r
#define DRC_250KBS  0x02  // 250K\r
//\r
// FDC Command Code\r
//\r
#define READ_DATA_CMD         0x06\r
#define SEEK_CMD              0x0F\r
#define RECALIBRATE_CMD       0x07\r
#define SENSE_INT_STATUS_CMD  0x08\r
#define SPECIFY_CMD           0x03\r
#define SENSE_DRV_STATUS_CMD  0x04\r
\r
///\r
/// CMD_MT: Multi_Track Selector\r
/// when set , this flag selects the multi-track operating mode.\r
/// In this mode, the FDC treats a complete cylinder under head0 and 1 as a single track\r
///\r
#define CMD_MT  BIT7\r
\r
///\r
/// CMD_MFM: MFM/FM Mode Selector\r
/// A one selects the double density(MFM) mode\r
/// A zero selects single density (FM) mode\r
///\r
#define CMD_MFM BIT6\r
\r
///\r
/// CMD_SK: Skip Flag\r
/// When set to 1, sectors containing a deleted data address mark will automatically be skipped\r
/// during the execution of Read Data.\r
/// When set to 0, the sector is read or written the same as the read and write commands.\r
///\r
#define CMD_SK  BIT5\r
\r
//\r
// FDC Status Register Bit Definitions\r
//\r
//\r
// Status Register 0\r
//\r
#define STS0_IC (BIT7 | BIT6) // Interrupt Code\r
#define STS0_SE BIT5          // Seek End: the FDC completed a seek or recalibrate command\r
#define STS0_EC BIT4          // Equipment Check\r
#define STS0_NR BIT3          // Not Ready(unused), this bit is always 0\r
#define STS0_HA BIT2          // Head Address: the current head address\r
//\r
// STS0_US1 & STS0_US0: Drive Select(the current selected drive)\r
//\r
#define STS0_US1  BIT1  // Unit Select1\r
#define STS0_US0  BIT0  // Unit Select0\r
//\r
// Status Register 1\r
//\r
#define STS1_EN BIT7  // End of Cylinder\r
//\r
// BIT6 is unused\r
//\r
#define STS1_DE BIT5  // Data Error: The FDC detected a CRC error in either the ID field or data field of a sector\r
#define STS1_OR BIT4  // Overrun/Underrun: Becomes set if FDC does not receive CPU or DMA service within the required time interval\r
//\r
// BIT3 is unused\r
//\r
#define STS1_ND BIT2  // No data\r
#define STS1_NW BIT1  // Not Writable\r
#define STS1_MA BIT0  // Missing Address Mark\r
\r
//\r
// Status Register 2\r
//\r
// BIT7 is unused\r
//\r
#define STS2_CM BIT6  // Control Mark\r
#define STS2_DD BIT5  // Data Error in Data Field: The FDC detected a CRC error in the data field\r
#define STS2_WC BIT4  // Wrong Cylinder: The track address from sector ID field is different from the track address maintained inside FDC\r
//\r
// BIT3 is unused\r
// BIT2 is unused\r
//\r
#define STS2_BC BIT1  // Bad Cylinder\r
#define STS2_MD BIT0  // Missing Address Mark in DataField\r
\r
//\r
// Status Register 3\r
//\r
// BIT7 is unused\r
//\r
#define STS3_WP BIT6  // Write Protected\r
//\r
// BIT5 is unused\r
//\r
#define STS3_T0 BIT4  // Track 0\r
//\r
// BIT3 is unused\r
//\r
#define STS3_HD BIT2  // Head Address\r
//\r
// STS3_US1 & STS3_US0 : Drive Select\r
//\r
#define STS3_US1  BIT1  // Unit Select1\r
#define STS3_US0  BIT0  // Unit Select0\r
\r
//\r
// Status Register 0 Interrupt Code Description\r
//\r
#define IC_NT   0x0   // Normal Termination of Command\r
#define IC_AT   0x40  // Abnormal Termination of Command\r
#define IC_IC   0x80  // Invalid Command\r
#define IC_ATRC 0xC0  // Abnormal Termination caused by Polling\r
\r
///\r
/// Table of parameters for diskette\r
///\r
typedef struct {\r
  UINT8 EndOfTrack;          ///< End of track\r
  UINT8 GapLength;           ///< Gap length\r
  UINT8 DataLength;          ///< Data length\r
  UINT8 Number;              ///< Number of bytes per sector\r
  UINT8 MaxTrackNum;\r
  UINT8 MotorStartTime;\r
  UINT8 MotorOffTime;\r
  UINT8 HeadSettlingTime;\r
  UINT8 DataTransferRate;\r
} DISKET_PARA_TABLE;\r
\r
///\r
/// Structure for FDC Command Packet 1\r
///\r
typedef struct {\r
  UINT8 CommandCode;\r
  UINT8 DiskHeadSel;\r
  UINT8 Cylinder;\r
  UINT8 Head;\r
  UINT8 Sector;\r
  UINT8 Number;\r
  UINT8 EndOfTrack;\r
  UINT8 GapLength;\r
  UINT8 DataLength;\r
} FDC_COMMAND_PACKET1;\r
\r
///\r
/// Structure for FDC Command Packet 2\r
///\r
typedef struct {\r
  UINT8 CommandCode;\r
  UINT8 DiskHeadSel;\r
} FDC_COMMAND_PACKET2;\r
\r
///\r
/// Structure for FDC Specify Command\r
///\r
typedef struct {\r
  UINT8 CommandCode;\r
  UINT8 SrtHut;\r
  UINT8 HltNd;\r
} FDC_SPECIFY_CMD;\r
\r
///\r
/// Structure for FDC Seek Command\r
///\r
typedef struct {\r
  UINT8 CommandCode;\r
  UINT8 DiskHeadSel;\r
  UINT8 NewCylinder;\r
} FDC_SEEK_CMD;\r
\r
///\r
/// Structure for FDC Result Packet\r
///\r
typedef struct {\r
  UINT8 Status0;\r
  UINT8 Status1;\r
  UINT8 Status2;\r
  UINT8 CylinderNumber;\r
  UINT8 HeaderAddress;\r
  UINT8 Record;\r
  UINT8 Number;\r
} FDC_RESULT_PACKET;\r
\r
#endif\r
Commit	Line	Data
0a6f4824	1	/** @file\r
d8387fa4	2	Definition of FDC registers and structures.\r
d8387fa4	3	\r
0a6f4824 LG	4	Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
0a6f4824 LG	5	\r
c0a00b14	6	SPDX-License-Identifier: BSD-2-Clause-Patent\r
d8387fa4	7	\r
	8	**/\r
	9	\r
	10	#ifndef _PEI_RECOVERY_FDC_H_\r
	11	#define _PEI_RECOVERY_FDC_H_\r
	12	\r
	13	//\r
	14	// FDC Registers\r
	15	//\r
	16	#define FDC_REGISTER_DOR 2 //Digital Output Register\r
	17	#define FDC_REGISTER_MSR 4 //Main Status Register\r
	18	#define FDC_REGISTER_DTR 5 //Data Register\r
	19	#define FDC_REGISTER_CCR 7 //Configuration Control Register(data rate select)\r
	20	#define FDC_REGISTER_DIR 7 //Digital Input Register(diskchange)\r
	21	//\r
	22	// FDC Register Bit Definitions\r
	23	//\r
	24	//\r
	25	// Digital Out Register(WO)\r
	26	//\r
	27	#define SELECT_DRV BIT0 // Select Drive: 0=A 1=B\r
	28	#define RESET_FDC BIT2 // Reset FDC\r
	29	#define INT_DMA_ENABLE BIT3 // Enable Int & DMA\r
	30	#define DRVA_MOTOR_ON BIT4 // Turn On Drive A Motor\r
	31	#define DRVB_MOTOR_ON BIT5 // Turn On Drive B Motor\r
	32	//\r
	33	// Main Status Register(RO)\r
	34	//\r
	35	#define MSR_DAB BIT0 // Drive A Busy\r
	36	#define MSR_DBB BIT1 // Drive B Busy\r
	37	#define MSR_CB BIT4 // FDC Busy\r
	38	#define MSR_NDM BIT5 // Non-DMA Mode\r
	39	#define MSR_DIO BIT6 // Data Input/Output\r
	40	#define MSR_RQM BIT7 // Request For Master\r
	41	//\r
	42	// Configuration Control Register(WO)\r
	43	//\r
	44	#define CCR_DRC (BIT0 \| BIT1) // Data Rate select\r
	45	//\r
	46	// Digital Input Register(RO)\r
	47	//\r
	48	#define DIR_DCL BIT7 // Disk change line\r
	49	#define DRC_500KBS 0x0 // 500K\r
	50	#define DRC_300KBS 0x01 // 300K\r
	51	#define DRC_250KBS 0x02 // 250K\r
	52	//\r
	53	// FDC Command Code\r
	54	//\r
	55	#define READ_DATA_CMD 0x06\r
	56	#define SEEK_CMD 0x0F\r
	57	#define RECALIBRATE_CMD 0x07\r
	58	#define SENSE_INT_STATUS_CMD 0x08\r
	59	#define SPECIFY_CMD 0x03\r
	60	#define SENSE_DRV_STATUS_CMD 0x04\r
	61	\r
	62	///\r
	63	/// CMD_MT: Multi_Track Selector\r
	64	/// when set , this flag selects the multi-track operating mode.\r
	65	/// In this mode, the FDC treats a complete cylinder under head0 and 1 as a single track\r
	66	///\r
	67	#define CMD_MT BIT7\r
	68	\r
	69	///\r
	70	/// CMD_MFM: MFM/FM Mode Selector\r
71	/// A one selects the double density(MFM) mode\r
72	/// A zero selects single density (FM) mode\r
73	///\r
74	#define CMD_MFM BIT6\r
75	\r
76	///\r
77	/// CMD_SK: Skip Flag\r
78	/// When set to 1, sectors containing a deleted data address mark will automatically be skipped\r
79	/// during the execution of Read Data.\r
80	/// When set to 0, the sector is read or written the same as the read and write commands.\r
81	///\r
82	#define CMD_SK BIT5\r
83	\r
84	//\r
85	// FDC Status Register Bit Definitions\r
86	//\r
87	//\r
88	// Status Register 0\r
89	//\r
90	#define STS0_IC (BIT7 \| BIT6) // Interrupt Code\r
91	#define STS0_SE BIT5 // Seek End: the FDC completed a seek or recalibrate command\r
92	#define STS0_EC BIT4 // Equipment Check\r
93	#define STS0_NR BIT3 // Not Ready(unused), this bit is always 0\r
94	#define STS0_HA BIT2 // Head Address: the current head address\r
95	//\r
96	// STS0_US1 & STS0_US0: Drive Select(the current selected drive)\r
97	//\r
98	#define STS0_US1 BIT1 // Unit Select1\r
99	#define STS0_US0 BIT0 // Unit Select0\r
100	//\r
101	// Status Register 1\r
102	//\r
103	#define STS1_EN BIT7 // End of Cylinder\r
104	//\r
105	// BIT6 is unused\r
106	//\r
107	#define STS1_DE BIT5 // Data Error: The FDC detected a CRC error in either the ID field or data field of a sector\r
108	#define STS1_OR BIT4 // Overrun/Underrun: Becomes set if FDC does not receive CPU or DMA service within the required time interval\r
109	//\r
110	// BIT3 is unused\r
111	//\r
112	#define STS1_ND BIT2 // No data\r
113	#define STS1_NW BIT1 // Not Writable\r
114	#define STS1_MA BIT0 // Missing Address Mark\r
115	\r
116	//\r
117	// Status Register 2\r
118	//\r
119	// BIT7 is unused\r
120	//\r
121	#define STS2_CM BIT6 // Control Mark\r
122	#define STS2_DD BIT5 // Data Error in Data Field: The FDC detected a CRC error in the data field\r
123	#define STS2_WC BIT4 // Wrong Cylinder: The track address from sector ID field is different from the track address maintained inside FDC\r
124	//\r
125	// BIT3 is unused\r
126	// BIT2 is unused\r
127	//\r
128	#define STS2_BC BIT1 // Bad Cylinder\r
129	#define STS2_MD BIT0 // Missing Address Mark in DataField\r
130	\r
131	//\r
132	// Status Register 3\r
133	//\r
134	// BIT7 is unused\r
135	//\r
136	#define STS3_WP BIT6 // Write Protected\r
137	//\r
138	// BIT5 is unused\r
139	//\r
140	#define STS3_T0 BIT4 // Track 0\r
141	//\r
142	// BIT3 is unused\r
143	//\r
144	#define STS3_HD BIT2 // Head Address\r
145	//\r
146	// STS3_US1 & STS3_US0 : Drive Select\r
147	//\r
148	#define STS3_US1 BIT1 // Unit Select1\r
149	#define STS3_US0 BIT0 // Unit Select0\r
150	\r
151	//\r
152	// Status Register 0 Interrupt Code Description\r
153	//\r
154	#define IC_NT 0x0 // Normal Termination of Command\r
155	#define IC_AT 0x40 // Abnormal Termination of Command\r
156	#define IC_IC 0x80 // Invalid Command\r
157	#define IC_ATRC 0xC0 // Abnormal Termination caused by Polling\r
158	\r
159	///\r
160	/// Table of parameters for diskette\r
161	///\r
162	typedef struct {\r
163	UINT8 EndOfTrack; ///< End of track\r
164	UINT8 GapLength; ///< Gap length\r
165	UINT8 DataLength; ///< Data length\r
166	UINT8 Number; ///< Number of bytes per sector\r
167	UINT8 MaxTrackNum;\r
168	UINT8 MotorStartTime;\r
169	UINT8 MotorOffTime;\r
170	UINT8 HeadSettlingTime;\r
171	UINT8 DataTransferRate;\r
172	} DISKET_PARA_TABLE;\r
173	\r
174	///\r
175	/// Structure for FDC Command Packet 1\r
176	///\r
177	typedef struct {\r
178	UINT8 CommandCode;\r
179	UINT8 DiskHeadSel;\r
180	UINT8 Cylinder;\r
181	UINT8 Head;\r
182	UINT8 Sector;\r
183	UINT8 Number;\r
184	UINT8 EndOfTrack;\r
185	UINT8 GapLength;\r
186	UINT8 DataLength;\r
187	} FDC_COMMAND_PACKET1;\r
188	\r
189	///\r
190	/// Structure for FDC Command Packet 2\r
191	///\r
192	typedef struct {\r
193	UINT8 CommandCode;\r
194	UINT8 DiskHeadSel;\r
195	} FDC_COMMAND_PACKET2;\r
196	\r
197	///\r
198	/// Structure for FDC Specify Command\r
199	///\r
200	typedef struct {\r
201	UINT8 CommandCode;\r
202	UINT8 SrtHut;\r
203	UINT8 HltNd;\r
204	} FDC_SPECIFY_CMD;\r
205	\r
206	///\r
207	/// Structure for FDC Seek Command\r
208	///\r
209	typedef struct {\r
210	UINT8 CommandCode;\r
211	UINT8 DiskHeadSel;\r
212	UINT8 NewCylinder;\r
213	} FDC_SEEK_CMD;\r
214	\r
215	///\r
216	/// Structure for FDC Result Packet\r
217	///\r
218	typedef struct {\r
219	UINT8 Status0;\r
220	UINT8 Status1;\r
221	UINT8 Status2;\r
222	UINT8 CylinderNumber;\r
223	UINT8 HeaderAddress;\r
224	UINT8 Record;\r
225	UINT8 Number;\r
226	} FDC_RESULT_PACKET;\r
227	\r
228	#endif\r