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f8cd287b | 1 | /**@file\r |
637ff819 | 2 | Include for Serial Driver\r |
f8cd287b | 3 | \r |
4 | Copyright (c) 2006 - 2007, Intel Corporation.<BR>\r | |
5 | All rights reserved. This program and the accompanying materials\r | |
6 | are licensed and made available under the terms and conditions of the BSD License\r | |
7 | which accompanies this distribution. The full text of the license may be found at\r | |
8 | http://opensource.org/licenses/bsd-license.php\r | |
637ff819 | 9 | \r |
f8cd287b | 10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
637ff819 | 12 | \r |
f8cd287b | 13 | **/\r |
637ff819 | 14 | \r |
15 | #ifndef _SERIAL_H\r | |
16 | #define _SERIAL_H\r | |
17 | \r | |
ed7748fe | 18 | \r |
637ff819 | 19 | #include <PiDxe.h>\r |
20 | #include <FrameworkPei.h>\r | |
ed7748fe | 21 | \r |
637ff819 | 22 | #include <Protocol/IsaIo.h>\r |
23 | #include <Protocol/SerialIo.h>\r | |
24 | #include <Protocol/DevicePath.h>\r | |
ed7748fe | 25 | \r |
637ff819 | 26 | #include <Library/DebugLib.h>\r |
27 | #include <Library/UefiDriverEntryPoint.h>\r | |
28 | #include <Library/BaseLib.h>\r | |
29 | #include <Library/UefiLib.h>\r | |
30 | #include <Library/DevicePathLib.h>\r | |
31 | #include <Library/BaseMemoryLib.h>\r | |
32 | #include <Library/MemoryAllocationLib.h>\r | |
33 | #include <Library/UefiBootServicesTableLib.h>\r | |
34 | #include <Library/ReportStatusCodeLib.h>\r | |
35 | #include <Library/PcdLib.h>\r | |
36 | //\r | |
37 | // Driver Binding Externs\r | |
38 | //\r | |
f3d08ccf | 39 | extern EFI_DRIVER_BINDING_PROTOCOL gSerialControllerDriver;\r |
40 | extern EFI_COMPONENT_NAME_PROTOCOL gIsaSerialComponentName;\r | |
41 | extern EFI_COMPONENT_NAME2_PROTOCOL gIsaSerialComponentName2;\r | |
637ff819 | 42 | \r |
43 | //\r | |
44 | // Internal Data Structures\r | |
45 | //\r | |
f02bd376 | 46 | #define SERIAL_DEV_SIGNATURE SIGNATURE_32 ('s', 'e', 'r', 'd')\r |
637ff819 | 47 | #define SERIAL_MAX_BUFFER_SIZE 16\r |
48 | #define TIMEOUT_STALL_INTERVAL 10\r | |
49 | \r | |
50 | //\r | |
51 | // Name: SERIAL_DEV_FIFO\r | |
52 | // Purpose: To define Receive FIFO and Transmit FIFO\r | |
53 | // Context: Used by serial data transmit and receive\r | |
54 | // Fields:\r | |
55 | // First UINT32: The index of the first data in array Data[]\r | |
56 | // Last UINT32: The index, which you can put a new data into array Data[]\r | |
57 | // Surplus UINT32: Identify how many data you can put into array Data[]\r | |
58 | // Data[] UINT8 : An array, which used to store data\r | |
59 | //\r | |
60 | typedef struct {\r | |
61 | UINT32 First;\r | |
62 | UINT32 Last;\r | |
63 | UINT32 Surplus;\r | |
64 | UINT8 Data[SERIAL_MAX_BUFFER_SIZE];\r | |
65 | } SERIAL_DEV_FIFO;\r | |
66 | \r | |
67 | typedef enum {\r | |
68 | UART8250 = 0,\r | |
69 | UART16450 = 1,\r | |
70 | UART16550 = 2,\r | |
71 | UART16550A= 3\r | |
72 | } EFI_UART_TYPE;\r | |
73 | \r | |
74 | //\r | |
75 | // Name: SERIAL_DEV\r | |
76 | // Purpose: To provide device specific information\r | |
77 | // Context:\r | |
78 | // Fields:\r | |
79 | // Signature UINTN: The identity of the serial device\r | |
80 | // SerialIo SERIAL_IO_PROTOCOL: Serial I/O protocol interface\r | |
81 | // SerialMode SERIAL_IO_MODE:\r | |
82 | // DevicePath EFI_DEVICE_PATH_PROTOCOL *: Device path of the serial device\r | |
83 | // Handle EFI_HANDLE: The handle instance attached to serial device\r | |
84 | // BaseAddress UINT16: The base address of specific serial device\r | |
85 | // Receive SERIAL_DEV_FIFO: The FIFO used to store data,\r | |
86 | // which is received by UART\r | |
87 | // Transmit SERIAL_DEV_FIFO: The FIFO used to store data,\r | |
88 | // which you want to transmit by UART\r | |
89 | // SoftwareLoopbackEnable BOOLEAN:\r | |
90 | // Type EFI_UART_TYPE: Specify the UART type of certain serial device\r | |
91 | //\r | |
92 | typedef struct {\r | |
93 | UINTN Signature;\r | |
94 | \r | |
95 | EFI_HANDLE Handle;\r | |
96 | EFI_SERIAL_IO_PROTOCOL SerialIo;\r | |
97 | EFI_SERIAL_IO_MODE SerialMode;\r | |
98 | EFI_DEVICE_PATH_PROTOCOL *DevicePath;\r | |
99 | \r | |
100 | EFI_DEVICE_PATH_PROTOCOL *ParentDevicePath;\r | |
101 | UART_DEVICE_PATH UartDevicePath;\r | |
102 | EFI_ISA_IO_PROTOCOL *IsaIo;\r | |
103 | \r | |
104 | UINT16 BaseAddress;\r | |
105 | SERIAL_DEV_FIFO Receive;\r | |
106 | SERIAL_DEV_FIFO Transmit;\r | |
107 | BOOLEAN SoftwareLoopbackEnable;\r | |
108 | BOOLEAN HardwareFlowControl;\r | |
109 | EFI_UART_TYPE Type;\r | |
110 | EFI_UNICODE_STRING_TABLE *ControllerNameTable;\r | |
111 | } SERIAL_DEV;\r | |
112 | \r | |
113 | #include "ComponentName.h"\r | |
114 | \r | |
115 | #define SERIAL_DEV_FROM_THIS(a) CR (a, SERIAL_DEV, SerialIo, SERIAL_DEV_SIGNATURE)\r | |
116 | \r | |
637ff819 | 117 | \r |
118 | //\r | |
119 | // Serial Driver Defaults\r | |
120 | //\r | |
637ff819 | 121 | #define SERIAL_PORT_DEFAULT_RECEIVE_FIFO_DEPTH 1\r |
122 | #define SERIAL_PORT_DEFAULT_TIMEOUT 1000000\r | |
6b88ceec A |
123 | \r |
124 | /*\r | |
125 | #define SERIAL_PORT_DEFAULT_BAUD_RATE 115200\r | |
637ff819 | 126 | #define SERIAL_PORT_DEFAULT_PARITY NoParity\r |
127 | #define SERIAL_PORT_DEFAULT_DATA_BITS 8\r | |
128 | #define SERIAL_PORT_DEFAULT_STOP_BITS 1\r | |
6b88ceec | 129 | */\r |
637ff819 | 130 | #define SERIAL_PORT_DEFAULT_CONTROL_MASK 0\r |
131 | \r | |
6b88ceec | 132 | \r |
637ff819 | 133 | //\r |
134 | // (24000000/13)MHz input clock\r | |
135 | //\r | |
136 | #define SERIAL_PORT_INPUT_CLOCK 1843200\r | |
137 | \r | |
138 | //\r | |
139 | // 115200 baud with rounding errors\r | |
140 | //\r | |
141 | #define SERIAL_PORT_MAX_BAUD_RATE 115400\r | |
142 | #define SERIAL_PORT_MIN_BAUD_RATE 50\r | |
143 | \r | |
144 | #define SERIAL_PORT_MAX_RECEIVE_FIFO_DEPTH 16\r | |
145 | #define SERIAL_PORT_MIN_TIMEOUT 1 // 1 uS\r | |
146 | #define SERIAL_PORT_MAX_TIMEOUT 100000000 // 100 seconds\r | |
147 | //\r | |
148 | // UART Registers\r | |
149 | //\r | |
150 | #define SERIAL_REGISTER_THR 0 // WO Transmit Holding Register\r | |
151 | #define SERIAL_REGISTER_RBR 0 // RO Receive Buffer Register\r | |
152 | #define SERIAL_REGISTER_DLL 0 // R/W Divisor Latch LSB\r | |
153 | #define SERIAL_REGISTER_DLM 1 // R/W Divisor Latch MSB\r | |
154 | #define SERIAL_REGISTER_IER 1 // R/W Interrupt Enable Register\r | |
155 | #define SERIAL_REGISTER_IIR 2 // RO Interrupt Identification Register\r | |
156 | #define SERIAL_REGISTER_FCR 2 // WO FIFO Cotrol Register\r | |
157 | #define SERIAL_REGISTER_LCR 3 // R/W Line Control Register\r | |
158 | #define SERIAL_REGISTER_MCR 4 // R/W Modem Control Register\r | |
159 | #define SERIAL_REGISTER_LSR 5 // R/W Line Status Register\r | |
160 | #define SERIAL_REGISTER_MSR 6 // R/W Modem Status Register\r | |
161 | #define SERIAL_REGISTER_SCR 7 // R/W Scratch Pad Register\r | |
162 | #pragma pack(1)\r | |
163 | //\r | |
164 | // Name: SERIAL_PORT_IER_BITS\r | |
165 | // Purpose: Define each bit in Interrupt Enable Register\r | |
166 | // Context:\r | |
167 | // Fields:\r | |
168 | // RAVIE Bit0: Receiver Data Available Interrupt Enable\r | |
169 | // THEIE Bit1: Transmistter Holding Register Empty Interrupt Enable\r | |
170 | // RIE Bit2: Receiver Interrupt Enable\r | |
171 | // MIE Bit3: Modem Interrupt Enable\r | |
172 | // Reserved Bit4-Bit7: Reserved\r | |
173 | //\r | |
174 | typedef struct {\r | |
175 | UINT8 RAVIE : 1;\r | |
176 | UINT8 THEIE : 1;\r | |
177 | UINT8 RIE : 1;\r | |
178 | UINT8 MIE : 1;\r | |
179 | UINT8 Reserved : 4;\r | |
180 | } SERIAL_PORT_IER_BITS;\r | |
181 | \r | |
182 | //\r | |
183 | // Name: SERIAL_PORT_IER\r | |
184 | // Purpose:\r | |
185 | // Context:\r | |
186 | // Fields:\r | |
187 | // Bits SERIAL_PORT_IER_BITS: Bits of the IER\r | |
188 | // Data UINT8: the value of the IER\r | |
189 | //\r | |
190 | typedef union {\r | |
191 | SERIAL_PORT_IER_BITS Bits;\r | |
192 | UINT8 Data;\r | |
193 | } SERIAL_PORT_IER;\r | |
194 | \r | |
195 | //\r | |
196 | // Name: SERIAL_PORT_IIR_BITS\r | |
197 | // Purpose: Define each bit in Interrupt Identification Register\r | |
198 | // Context:\r | |
199 | // Fields:\r | |
200 | // IPS Bit0: Interrupt Pending Status\r | |
201 | // IIB Bit1-Bit3: Interrupt ID Bits\r | |
202 | // Reserved Bit4-Bit5: Reserved\r | |
203 | // FIFOES Bit6-Bit7: FIFO Mode Enable Status\r | |
204 | //\r | |
205 | typedef struct {\r | |
206 | UINT8 IPS : 1;\r | |
207 | UINT8 IIB : 3;\r | |
208 | UINT8 Reserved : 2;\r | |
209 | UINT8 FIFOES : 2;\r | |
210 | } SERIAL_PORT_IIR_BITS;\r | |
211 | \r | |
212 | //\r | |
213 | // Name: SERIAL_PORT_IIR\r | |
214 | // Purpose:\r | |
215 | // Context:\r | |
216 | // Fields:\r | |
217 | // Bits SERIAL_PORT_IIR_BITS: Bits of the IIR\r | |
218 | // Data UINT8: the value of the IIR\r | |
219 | //\r | |
220 | typedef union {\r | |
221 | SERIAL_PORT_IIR_BITS Bits;\r | |
222 | UINT8 Data;\r | |
223 | } SERIAL_PORT_IIR;\r | |
224 | \r | |
225 | //\r | |
226 | // Name: SERIAL_PORT_FCR_BITS\r | |
227 | // Purpose: Define each bit in FIFO Control Register\r | |
228 | // Context:\r | |
229 | // Fields:\r | |
230 | // TRFIFOE Bit0: Transmit and Receive FIFO Enable\r | |
231 | // RESETRF Bit1: Reset Reciever FIFO\r | |
232 | // RESETTF Bit2: Reset Transmistter FIFO\r | |
233 | // DMS Bit3: DMA Mode Select\r | |
234 | // Reserved Bit4-Bit5: Reserved\r | |
235 | // RTB Bit6-Bit7: Receive Trigger Bits\r | |
236 | //\r | |
237 | typedef struct {\r | |
238 | UINT8 TRFIFOE : 1;\r | |
239 | UINT8 RESETRF : 1;\r | |
240 | UINT8 RESETTF : 1;\r | |
241 | UINT8 DMS : 1;\r | |
242 | UINT8 Reserved : 2;\r | |
243 | UINT8 RTB : 2;\r | |
244 | } SERIAL_PORT_FCR_BITS;\r | |
245 | \r | |
246 | //\r | |
247 | // Name: SERIAL_PORT_FCR\r | |
248 | // Purpose:\r | |
249 | // Context:\r | |
250 | // Fields:\r | |
251 | // Bits SERIAL_PORT_FCR_BITS: Bits of the FCR\r | |
252 | // Data UINT8: the value of the FCR\r | |
253 | //\r | |
254 | typedef union {\r | |
255 | SERIAL_PORT_FCR_BITS Bits;\r | |
256 | UINT8 Data;\r | |
257 | } SERIAL_PORT_FCR;\r | |
258 | \r | |
259 | //\r | |
260 | // Name: SERIAL_PORT_LCR_BITS\r | |
261 | // Purpose: Define each bit in Line Control Register\r | |
262 | // Context:\r | |
263 | // Fields:\r | |
264 | // SERIALDB Bit0-Bit1: Number of Serial Data Bits\r | |
265 | // STOPB Bit2: Number of Stop Bits\r | |
266 | // PAREN Bit3: Parity Enable\r | |
267 | // EVENPAR Bit4: Even Parity Select\r | |
268 | // STICPAR Bit5: Sticky Parity\r | |
269 | // BRCON Bit6: Break Control\r | |
270 | // DLAB Bit7: Divisor Latch Access Bit\r | |
271 | //\r | |
272 | typedef struct {\r | |
273 | UINT8 SERIALDB : 2;\r | |
274 | UINT8 STOPB : 1;\r | |
275 | UINT8 PAREN : 1;\r | |
276 | UINT8 EVENPAR : 1;\r | |
277 | UINT8 STICPAR : 1;\r | |
278 | UINT8 BRCON : 1;\r | |
279 | UINT8 DLAB : 1;\r | |
280 | } SERIAL_PORT_LCR_BITS;\r | |
281 | \r | |
282 | //\r | |
283 | // Name: SERIAL_PORT_LCR\r | |
284 | // Purpose:\r | |
285 | // Context:\r | |
286 | // Fields:\r | |
287 | // Bits SERIAL_PORT_LCR_BITS: Bits of the LCR\r | |
288 | // Data UINT8: the value of the LCR\r | |
289 | //\r | |
290 | typedef union {\r | |
291 | SERIAL_PORT_LCR_BITS Bits;\r | |
292 | UINT8 Data;\r | |
293 | } SERIAL_PORT_LCR;\r | |
294 | \r | |
295 | //\r | |
296 | // Name: SERIAL_PORT_MCR_BITS\r | |
297 | // Purpose: Define each bit in Modem Control Register\r | |
298 | // Context:\r | |
299 | // Fields:\r | |
300 | // DTRC Bit0: Data Terminal Ready Control\r | |
301 | // RTS Bit1: Request To Send Control\r | |
302 | // OUT1 Bit2: Output1\r | |
303 | // OUT2 Bit3: Output2, used to disable interrupt\r | |
304 | // LME; Bit4: Loopback Mode Enable\r | |
305 | // Reserved Bit5-Bit7: Reserved\r | |
306 | //\r | |
307 | typedef struct {\r | |
308 | UINT8 DTRC : 1;\r | |
309 | UINT8 RTS : 1;\r | |
310 | UINT8 OUT1 : 1;\r | |
311 | UINT8 OUT2 : 1;\r | |
312 | UINT8 LME : 1;\r | |
313 | UINT8 Reserved : 3;\r | |
314 | } SERIAL_PORT_MCR_BITS;\r | |
315 | \r | |
316 | //\r | |
317 | // Name: SERIAL_PORT_MCR\r | |
318 | // Purpose:\r | |
319 | // Context:\r | |
320 | // Fields:\r | |
321 | // Bits SERIAL_PORT_MCR_BITS: Bits of the MCR\r | |
322 | // Data UINT8: the value of the MCR\r | |
323 | //\r | |
324 | typedef union {\r | |
325 | SERIAL_PORT_MCR_BITS Bits;\r | |
326 | UINT8 Data;\r | |
327 | } SERIAL_PORT_MCR;\r | |
328 | \r | |
329 | //\r | |
330 | // Name: SERIAL_PORT_LSR_BITS\r | |
331 | // Purpose: Define each bit in Line Status Register\r | |
332 | // Context:\r | |
333 | // Fields:\r | |
334 | // DR Bit0: Receiver Data Ready Status\r | |
335 | // OE Bit1: Overrun Error Status\r | |
336 | // PE Bit2: Parity Error Status\r | |
337 | // FE Bit3: Framing Error Status\r | |
338 | // BI Bit4: Break Interrupt Status\r | |
339 | // THRE Bit5: Transmistter Holding Register Status\r | |
340 | // TEMT Bit6: Transmitter Empty Status\r | |
341 | // FIFOE Bit7: FIFO Error Status\r | |
342 | //\r | |
343 | typedef struct {\r | |
344 | UINT8 DR : 1;\r | |
345 | UINT8 OE : 1;\r | |
346 | UINT8 PE : 1;\r | |
347 | UINT8 FE : 1;\r | |
348 | UINT8 BI : 1;\r | |
349 | UINT8 THRE : 1;\r | |
350 | UINT8 TEMT : 1;\r | |
351 | UINT8 FIFOE : 1;\r | |
352 | } SERIAL_PORT_LSR_BITS;\r | |
353 | \r | |
354 | //\r | |
355 | // Name: SERIAL_PORT_LSR\r | |
356 | // Purpose:\r | |
357 | // Context:\r | |
358 | // Fields:\r | |
359 | // Bits SERIAL_PORT_LSR_BITS: Bits of the LSR\r | |
360 | // Data UINT8: the value of the LSR\r | |
361 | //\r | |
362 | typedef union {\r | |
363 | SERIAL_PORT_LSR_BITS Bits;\r | |
364 | UINT8 Data;\r | |
365 | } SERIAL_PORT_LSR;\r | |
366 | \r | |
367 | //\r | |
368 | // Name: SERIAL_PORT_MSR_BITS\r | |
369 | // Purpose: Define each bit in Modem Status Register\r | |
370 | // Context:\r | |
371 | // Fields:\r | |
372 | // DeltaCTS Bit0: Delta Clear To Send Status\r | |
373 | // DeltaDSR Bit1: Delta Data Set Ready Status\r | |
374 | // TrailingEdgeRI Bit2: Trailing Edge of Ring Indicator Status\r | |
375 | // DeltaDCD Bit3: Delta Data Carrier Detect Status\r | |
376 | // CTS Bit4: Clear To Send Status\r | |
377 | // DSR Bit5: Data Set Ready Status\r | |
378 | // RI Bit6: Ring Indicator Status\r | |
379 | // DCD Bit7: Data Carrier Detect Status\r | |
380 | //\r | |
381 | typedef struct {\r | |
382 | UINT8 DeltaCTS : 1;\r | |
383 | UINT8 DeltaDSR : 1;\r | |
384 | UINT8 TrailingEdgeRI : 1;\r | |
385 | UINT8 DeltaDCD : 1;\r | |
386 | UINT8 CTS : 1;\r | |
387 | UINT8 DSR : 1;\r | |
388 | UINT8 RI : 1;\r | |
389 | UINT8 DCD : 1;\r | |
390 | } SERIAL_PORT_MSR_BITS;\r | |
391 | \r | |
392 | //\r | |
393 | // Name: SERIAL_PORT_MSR\r | |
394 | // Purpose:\r | |
395 | // Context:\r | |
396 | // Fields:\r | |
397 | // Bits SERIAL_PORT_MSR_BITS: Bits of the MSR\r | |
398 | // Data UINT8: the value of the MSR\r | |
399 | //\r | |
400 | typedef union {\r | |
401 | SERIAL_PORT_MSR_BITS Bits;\r | |
402 | UINT8 Data;\r | |
403 | } SERIAL_PORT_MSR;\r | |
404 | \r | |
405 | #pragma pack()\r | |
406 | //\r | |
407 | // Define serial register I/O macros\r | |
408 | //\r | |
409 | #define READ_RBR(IO, B) IsaSerialReadPort (IO, B, SERIAL_REGISTER_RBR)\r | |
410 | #define READ_DLL(IO, B) IsaSerialReadPort (IO, B, SERIAL_REGISTER_DLL)\r | |
411 | #define READ_DLM(IO, B) IsaSerialReadPort (IO, B, SERIAL_REGISTER_DLM)\r | |
412 | #define READ_IER(IO, B) IsaSerialReadPort (IO, B, SERIAL_REGISTER_IER)\r | |
413 | #define READ_IIR(IO, B) IsaSerialReadPort (IO, B, SERIAL_REGISTER_IIR)\r | |
414 | #define READ_LCR(IO, B) IsaSerialReadPort (IO, B, SERIAL_REGISTER_LCR)\r | |
415 | #define READ_MCR(IO, B) IsaSerialReadPort (IO, B, SERIAL_REGISTER_MCR)\r | |
416 | #define READ_LSR(IO, B) IsaSerialReadPort (IO, B, SERIAL_REGISTER_LSR)\r | |
417 | #define READ_MSR(IO, B) IsaSerialReadPort (IO, B, SERIAL_REGISTER_MSR)\r | |
418 | #define READ_SCR(IO, B) IsaSerialReadPort (IO, B, SERIAL_REGISTER_SCR)\r | |
419 | \r | |
420 | #define WRITE_THR(IO, B, D) IsaSerialWritePort (IO, B, SERIAL_REGISTER_THR, D)\r | |
421 | #define WRITE_DLL(IO, B, D) IsaSerialWritePort (IO, B, SERIAL_REGISTER_DLL, D)\r | |
422 | #define WRITE_DLM(IO, B, D) IsaSerialWritePort (IO, B, SERIAL_REGISTER_DLM, D)\r | |
423 | #define WRITE_IER(IO, B, D) IsaSerialWritePort (IO, B, SERIAL_REGISTER_IER, D)\r | |
424 | #define WRITE_FCR(IO, B, D) IsaSerialWritePort (IO, B, SERIAL_REGISTER_FCR, D)\r | |
425 | #define WRITE_LCR(IO, B, D) IsaSerialWritePort (IO, B, SERIAL_REGISTER_LCR, D)\r | |
426 | #define WRITE_MCR(IO, B, D) IsaSerialWritePort (IO, B, SERIAL_REGISTER_MCR, D)\r | |
427 | #define WRITE_LSR(IO, B, D) IsaSerialWritePort (IO, B, SERIAL_REGISTER_LSR, D)\r | |
428 | #define WRITE_MSR(IO, B, D) IsaSerialWritePort (IO, B, SERIAL_REGISTER_MSR, D)\r | |
429 | #define WRITE_SCR(IO, B, D) IsaSerialWritePort (IO, B, SERIAL_REGISTER_SCR, D)\r | |
430 | \r | |
431 | //\r | |
432 | // Prototypes\r | |
433 | // Driver model protocol interface\r | |
434 | //\r | |
435 | \r | |
436 | EFI_STATUS\r | |
437 | EFIAPI\r | |
438 | SerialControllerDriverSupported (\r | |
439 | IN EFI_DRIVER_BINDING_PROTOCOL *This,\r | |
440 | IN EFI_HANDLE Controller,\r | |
441 | IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath\r | |
442 | );\r | |
443 | \r | |
444 | EFI_STATUS\r | |
445 | EFIAPI\r | |
446 | SerialControllerDriverStart (\r | |
447 | IN EFI_DRIVER_BINDING_PROTOCOL *This,\r | |
448 | IN EFI_HANDLE Controller,\r | |
449 | IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath\r | |
450 | );\r | |
451 | \r | |
452 | EFI_STATUS\r | |
453 | EFIAPI\r | |
454 | SerialControllerDriverStop (\r | |
455 | IN EFI_DRIVER_BINDING_PROTOCOL *This,\r | |
456 | IN EFI_HANDLE Controller,\r | |
457 | IN UINTN NumberOfChildren,\r | |
458 | IN EFI_HANDLE *ChildHandleBuffer\r | |
459 | );\r | |
460 | \r | |
461 | //\r | |
462 | // Serial I/O Protocol Interface\r | |
463 | //\r | |
464 | EFI_STATUS\r | |
465 | EFIAPI\r | |
466 | IsaSerialReset (\r | |
467 | IN EFI_SERIAL_IO_PROTOCOL *This\r | |
468 | );\r | |
469 | \r | |
470 | EFI_STATUS\r | |
471 | EFIAPI\r | |
472 | IsaSerialSetAttributes (\r | |
473 | IN EFI_SERIAL_IO_PROTOCOL *This,\r | |
474 | IN UINT64 BaudRate,\r | |
475 | IN UINT32 ReceiveFifoDepth,\r | |
476 | IN UINT32 Timeout,\r | |
477 | IN EFI_PARITY_TYPE Parity,\r | |
478 | IN UINT8 DataBits,\r | |
479 | IN EFI_STOP_BITS_TYPE StopBits\r | |
480 | );\r | |
481 | \r | |
482 | EFI_STATUS\r | |
483 | EFIAPI\r | |
484 | IsaSerialSetControl (\r | |
485 | IN EFI_SERIAL_IO_PROTOCOL *This,\r | |
486 | IN UINT32 Control\r | |
487 | );\r | |
488 | \r | |
489 | EFI_STATUS\r | |
490 | EFIAPI\r | |
491 | IsaSerialGetControl (\r | |
492 | IN EFI_SERIAL_IO_PROTOCOL *This,\r | |
493 | OUT UINT32 *Control\r | |
494 | );\r | |
495 | \r | |
496 | EFI_STATUS\r | |
497 | EFIAPI\r | |
498 | IsaSerialWrite (\r | |
499 | IN EFI_SERIAL_IO_PROTOCOL *This,\r | |
500 | IN OUT UINTN *BufferSize,\r | |
501 | IN VOID *Buffer\r | |
502 | );\r | |
503 | \r | |
504 | EFI_STATUS\r | |
505 | EFIAPI\r | |
506 | IsaSerialRead (\r | |
507 | IN EFI_SERIAL_IO_PROTOCOL *This,\r | |
508 | IN OUT UINTN *BufferSize,\r | |
509 | OUT VOID *Buffer\r | |
510 | );\r | |
511 | \r | |
512 | //\r | |
513 | // Internal Functions\r | |
514 | //\r | |
515 | BOOLEAN\r | |
516 | IsaSerialPortPresent (\r | |
517 | IN SERIAL_DEV *SerialDevice\r | |
518 | );\r | |
519 | \r | |
520 | BOOLEAN\r | |
521 | IsaSerialFifoFull (\r | |
522 | IN SERIAL_DEV_FIFO *Fifo\r | |
523 | );\r | |
524 | \r | |
525 | BOOLEAN\r | |
526 | IsaSerialFifoEmpty (\r | |
527 | IN SERIAL_DEV_FIFO *Fifo\r | |
528 | );\r | |
529 | \r | |
530 | EFI_STATUS\r | |
531 | IsaSerialFifoAdd (\r | |
532 | IN SERIAL_DEV_FIFO *Fifo,\r | |
533 | IN UINT8 Data\r | |
534 | );\r | |
535 | \r | |
536 | EFI_STATUS\r | |
537 | IsaSerialFifoRemove (\r | |
538 | IN SERIAL_DEV_FIFO *Fifo,\r | |
539 | OUT UINT8 *Data\r | |
540 | );\r | |
541 | \r | |
542 | EFI_STATUS\r | |
543 | IsaSerialReceiveTransmit (\r | |
544 | IN SERIAL_DEV *SerialDevice\r | |
545 | );\r | |
546 | \r | |
547 | UINT8\r | |
548 | IsaSerialReadPort (\r | |
549 | IN EFI_ISA_IO_PROTOCOL *IsaIo,\r | |
550 | IN UINT16 BaseAddress,\r | |
551 | IN UINT32 Offset\r | |
552 | );\r | |
553 | \r | |
554 | VOID\r | |
555 | IsaSerialWritePort (\r | |
556 | IN EFI_ISA_IO_PROTOCOL *IsaIo,\r | |
557 | IN UINT16 BaseAddress,\r | |
558 | IN UINT32 Offset,\r | |
559 | IN UINT8 Data\r | |
560 | );\r | |
561 | \r | |
562 | #endif\r |