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ead42efc | 1 | /** @file\r |
2 | Header file for IDE Bus Driver's Data Structures\r | |
3 | \r | |
4 | Copyright (c) 2006 - 2007 Intel Corporation. <BR>\r | |
5 | All rights reserved. This program and the accompanying materials \r | |
6 | are licensed and made available under the terms and conditions of the BSD License \r | |
7 | which accompanies this distribution. The full text of the license may be found at \r | |
8 | http://opensource.org/licenses/bsd-license.php \r | |
9 | \r | |
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r | |
12 | \r | |
13 | **/\r | |
14 | \r | |
15 | #ifndef _IDE_DATA_H\r | |
16 | #define _IDE_DATA_H\r | |
17 | \r | |
1e23bd8d | 18 | #include <IndustryStandard/Atapi.h>\r |
ead42efc | 19 | \r |
20 | //\r | |
21 | // common constants\r | |
22 | //\r | |
23 | #define STALL_1_MILLI_SECOND 1000 // stall 1 ms\r | |
24 | #define STALL_1_SECOND 1000000 // stall 1 second\r | |
25 | typedef enum {\r | |
26 | IdePrimary = 0,\r | |
27 | IdeSecondary = 1,\r | |
28 | IdeMaxChannel = 2\r | |
29 | } EFI_IDE_CHANNEL;\r | |
30 | \r | |
31 | typedef enum {\r | |
32 | IdeMaster = 0,\r | |
33 | IdeSlave = 1,\r | |
34 | IdeMaxDevice = 2\r | |
35 | } EFI_IDE_DEVICE;\r | |
36 | \r | |
37 | typedef enum {\r | |
38 | IdeMagnetic, /* ZIP Drive or LS120 Floppy Drive */\r | |
39 | IdeCdRom, /* ATAPI CDROM */\r | |
40 | IdeHardDisk, /* Hard Disk */\r | |
41 | Ide48bitAddressingHardDisk, /* Hard Disk larger than 120GB */\r | |
42 | IdeUnknown\r | |
43 | } IDE_DEVICE_TYPE;\r | |
44 | \r | |
45 | typedef enum {\r | |
46 | SenseNoSenseKey,\r | |
47 | SenseDeviceNotReadyNoRetry,\r | |
48 | SenseDeviceNotReadyNeedRetry,\r | |
49 | SenseNoMedia,\r | |
50 | SenseMediaChange,\r | |
51 | SenseMediaError,\r | |
52 | SenseOtherSense\r | |
53 | } SENSE_RESULT;\r | |
54 | \r | |
55 | typedef enum {\r | |
56 | AtaUdmaReadOp,\r | |
57 | AtaUdmaReadExtOp,\r | |
58 | AtaUdmaWriteOp,\r | |
59 | AtaUdmaWriteExtOp\r | |
60 | } ATA_UDMA_OPERATION;\r | |
61 | \r | |
62 | //\r | |
63 | // IDE Registers\r | |
64 | //\r | |
65 | typedef union {\r | |
66 | UINT16 Command; /* when write */\r | |
67 | UINT16 Status; /* when read */\r | |
68 | } IDE_CMD_OR_STATUS;\r | |
69 | \r | |
70 | typedef union {\r | |
71 | UINT16 Error; /* when read */\r | |
72 | UINT16 Feature; /* when write */\r | |
73 | } IDE_ERROR_OR_FEATURE;\r | |
74 | \r | |
75 | typedef union {\r | |
76 | UINT16 AltStatus; /* when read */\r | |
77 | UINT16 DeviceControl; /* when write */\r | |
78 | } IDE_AltStatus_OR_DeviceControl;\r | |
79 | \r | |
80 | //\r | |
81 | // IDE registers set\r | |
82 | //\r | |
83 | typedef struct {\r | |
84 | UINT16 Data;\r | |
85 | IDE_ERROR_OR_FEATURE Reg1;\r | |
86 | UINT16 SectorCount;\r | |
87 | UINT16 SectorNumber;\r | |
88 | UINT16 CylinderLsb;\r | |
89 | UINT16 CylinderMsb;\r | |
90 | UINT16 Head;\r | |
91 | IDE_CMD_OR_STATUS Reg;\r | |
92 | \r | |
93 | IDE_AltStatus_OR_DeviceControl Alt;\r | |
94 | UINT16 DriveAddress;\r | |
95 | \r | |
96 | UINT16 MasterSlave;\r | |
97 | UINT16 BusMasterBaseAddr;\r | |
98 | } IDE_BASE_REGISTERS;\r | |
99 | \r | |
100 | //\r | |
101 | // IDE registers' base addresses\r | |
102 | //\r | |
103 | typedef struct {\r | |
104 | UINT16 CommandBlockBaseAddr;\r | |
105 | UINT16 ControlBlockBaseAddr;\r | |
106 | UINT16 BusMasterBaseAddr;\r | |
107 | } IDE_REGISTERS_BASE_ADDR;\r | |
108 | \r | |
109 | //\r | |
110 | // Bit definitions in Programming Interface byte of the Class Code field\r | |
111 | // in PCI IDE controller's Configuration Space\r | |
112 | //\r | |
1e23bd8d | 113 | #define IDE_PRIMARY_OPERATING_MODE BIT0\r |
114 | #define IDE_PRIMARY_PROGRAMMABLE_INDICATOR BIT1\r | |
115 | #define IDE_SECONDARY_OPERATING_MODE BIT2\r | |
116 | #define IDE_SECONDARY_PROGRAMMABLE_INDICATOR BIT3\r | |
ead42efc | 117 | \r |
ead42efc | 118 | \r |
119 | //\r | |
120 | // Bus Master Reg\r | |
121 | //\r | |
1e23bd8d | 122 | #define BMIC_nREAD BIT3\r |
123 | #define BMIC_START BIT0\r | |
124 | #define BMIS_INTERRUPT BIT2\r | |
125 | #define BMIS_ERROR BIT1\r | |
ead42efc | 126 | \r |
127 | #define BMICP_OFFSET 0x00\r | |
128 | #define BMISP_OFFSET 0x02\r | |
129 | #define BMIDP_OFFSET 0x04\r | |
130 | #define BMICS_OFFSET 0x08\r | |
131 | #define BMISS_OFFSET 0x0A\r | |
132 | #define BMIDS_OFFSET 0x0C\r | |
133 | \r | |
134 | //\r | |
135 | // Time Out Value For IDE Device Polling\r | |
136 | //\r | |
137 | \r | |
138 | //\r | |
139 | // ATATIMEOUT is used for waiting time out for ATA device\r | |
140 | //\r | |
141 | \r | |
142 | //\r | |
143 | // 1 second\r | |
144 | //\r | |
145 | #define ATATIMEOUT 1000 \r | |
146 | \r | |
147 | //\r | |
148 | // ATAPITIMEOUT is used for waiting operation\r | |
149 | // except read and write time out for ATAPI device\r | |
150 | //\r | |
151 | \r | |
152 | //\r | |
153 | // 1 second\r | |
154 | //\r | |
155 | #define ATAPITIMEOUT 1000 \r | |
156 | \r | |
157 | //\r | |
158 | // ATAPILONGTIMEOUT is used for waiting read and\r | |
159 | // write operation timeout for ATAPI device\r | |
160 | //\r | |
161 | \r | |
162 | //\r | |
163 | // 2 seconds\r | |
164 | //\r | |
165 | #define CDROMLONGTIMEOUT 2000 \r | |
166 | \r | |
167 | //\r | |
168 | // 5 seconds\r | |
169 | //\r | |
170 | #define ATAPILONGTIMEOUT 5000 \r | |
171 | \r | |
172 | //\r | |
173 | // 10 seconds\r | |
174 | //\r | |
175 | #define ATASMARTTIMEOUT 10000\r | |
176 | \r | |
ead42efc | 177 | \r |
178 | //\r | |
179 | // ATAPI6 related data structure definition\r | |
180 | //\r | |
181 | \r | |
182 | //\r | |
183 | // The maximum sectors count in 28 bit addressing mode\r | |
184 | //\r | |
185 | #define MAX_28BIT_ADDRESSING_CAPACITY 0xfffffff\r | |
186 | \r | |
ead42efc | 187 | #pragma pack(1)\r |
188 | \r | |
ead42efc | 189 | typedef struct {\r |
190 | UINT32 RegionBaseAddr;\r | |
191 | UINT16 ByteCount;\r | |
192 | UINT16 EndOfTable;\r | |
193 | } IDE_DMA_PRD;\r | |
194 | \r | |
ead42efc | 195 | #pragma pack()\r |
196 | \r | |
ead42efc | 197 | #define SETFEATURE TRUE\r |
198 | #define CLEARFEATURE FALSE\r | |
199 | \r | |
ead42efc | 200 | //\r |
201 | // PIO mode definition\r | |
202 | //\r | |
203 | typedef enum {\r | |
204 | ATA_PIO_MODE_BELOW_2,\r | |
205 | ATA_PIO_MODE_2,\r | |
206 | ATA_PIO_MODE_3,\r | |
207 | ATA_PIO_MODE_4\r | |
208 | } ATA_PIO_MODE;\r | |
209 | \r | |
210 | //\r | |
211 | // Multi word DMA definition\r | |
212 | //\r | |
213 | typedef enum {\r | |
214 | ATA_MDMA_MODE_0,\r | |
215 | ATA_MDMA_MODE_1,\r | |
216 | ATA_MDMA_MODE_2\r | |
217 | } ATA_MDMA_MODE;\r | |
218 | \r | |
219 | //\r | |
220 | // UDMA mode definition\r | |
221 | //\r | |
222 | typedef enum {\r | |
223 | ATA_UDMA_MODE_0,\r | |
224 | ATA_UDMA_MODE_1,\r | |
225 | ATA_UDMA_MODE_2,\r | |
226 | ATA_UDMA_MODE_3,\r | |
227 | ATA_UDMA_MODE_4,\r | |
228 | ATA_UDMA_MODE_5\r | |
229 | } ATA_UDMA_MODE;\r | |
230 | \r | |
231 | #define ATA_MODE_CATEGORY_DEFAULT_PIO 0x00\r | |
232 | #define ATA_MODE_CATEGORY_FLOW_PIO 0x01\r | |
233 | #define ATA_MODE_CATEGORY_MDMA 0x04\r | |
234 | #define ATA_MODE_CATEGORY_UDMA 0x08\r | |
235 | \r | |
236 | #pragma pack(1)\r | |
237 | \r | |
238 | typedef struct {\r | |
239 | UINT8 ModeNumber : 3;\r | |
240 | UINT8 ModeCategory : 5;\r | |
241 | } ATA_TRANSFER_MODE;\r | |
242 | \r | |
243 | typedef struct {\r | |
244 | UINT8 Sector;\r | |
245 | UINT8 Heads;\r | |
246 | UINT8 MultipleSector;\r | |
247 | } ATA_DRIVE_PARMS;\r | |
248 | \r | |
249 | #pragma pack()\r | |
250 | //\r | |
251 | // IORDY Sample Point field value\r | |
252 | //\r | |
253 | #define ISP_5_CLK 0\r | |
254 | #define ISP_4_CLK 1\r | |
255 | #define ISP_3_CLK 2\r | |
256 | #define ISP_2_CLK 3\r | |
257 | \r | |
258 | //\r | |
259 | // Recovery Time field value\r | |
260 | //\r | |
261 | #define RECVY_4_CLK 0\r | |
262 | #define RECVY_3_CLK 1\r | |
263 | #define RECVY_2_CLK 2\r | |
264 | #define RECVY_1_CLK 3\r | |
265 | \r | |
266 | //\r | |
267 | // Slave IDE Timing Register Enable\r | |
268 | //\r | |
1e23bd8d | 269 | #define SITRE BIT14\r |
ead42efc | 270 | \r |
271 | //\r | |
272 | // DMA Timing Enable Only Select 1\r | |
273 | //\r | |
1e23bd8d | 274 | #define DTE1 BIT7\r |
ead42efc | 275 | \r |
276 | //\r | |
277 | // Pre-fetch and Posting Enable Select 1\r | |
278 | //\r | |
1e23bd8d | 279 | #define PPE1 BIT6\r |
ead42efc | 280 | \r |
281 | //\r | |
282 | // IORDY Sample Point Enable Select 1\r | |
283 | //\r | |
1e23bd8d | 284 | #define IE1 BIT5\r |
ead42efc | 285 | \r |
286 | //\r | |
287 | // Fast Timing Bank Drive Select 1\r | |
288 | //\r | |
1e23bd8d | 289 | #define TIME1 BIT4\r |
ead42efc | 290 | \r |
291 | //\r | |
292 | // DMA Timing Enable Only Select 0\r | |
293 | //\r | |
1e23bd8d | 294 | #define DTE0 BIT3\r |
ead42efc | 295 | \r |
296 | //\r | |
297 | // Pre-fetch and Posting Enable Select 0\r | |
298 | //\r | |
1e23bd8d | 299 | #define PPE0 BIT2\r |
ead42efc | 300 | \r |
301 | //\r | |
302 | // IOREY Sample Point Enable Select 0\r | |
303 | //\r | |
1e23bd8d | 304 | #define IE0 BIT1\r |
ead42efc | 305 | \r |
306 | //\r | |
307 | // Fast Timing Bank Drive Select 0\r | |
308 | //\r | |
1e23bd8d | 309 | #define TIME0 BIT0\r |
ead42efc | 310 | \r |
311 | #endif\r |