[mirror_edk2.git] / IntelFrameworkModulePkg / Bus / Pci / PciBusDxe / PciBus.h

/** @file\r
  Header files and data structures needed by PCI Bus module.\r
\r
Copyright (c) 2006 - 2009, Intel Corporation\r
All rights reserved. This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution.  The full text of the license may be found at\r
http://opensource.org/licenses/bsd-license.php\r
\r
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
\r
#ifndef _EFI_PCI_BUS_H_\r
#define _EFI_PCI_BUS_H_\r
\r
#include <FrameworkDxe.h>\r
\r
#include <Protocol/LoadedImage.h>\r
#include <Protocol/PciHostBridgeResourceAllocation.h>\r
#include <Protocol/PciIo.h>\r
#include <Protocol/LoadFile2.h>\r
#include <Protocol/PciRootBridgeIo.h>\r
#include <Protocol/PciHotPlugRequest.h>\r
#include <Protocol/DevicePath.h>\r
#include <Protocol/PciPlatform.h>\r
#include <Protocol/PciHotPlugInit.h>\r
#include <Protocol/Decompress.h>\r
#include <Protocol/BusSpecificDriverOverride.h>\r
#include <Protocol/IncompatiblePciDeviceSupport.h>\r
\r
#include <Library/DebugLib.h>\r
#include <Library/UefiDriverEntryPoint.h>\r
#include <Library/BaseLib.h>\r
#include <Library/UefiLib.h>\r
#include <Library/BaseMemoryLib.h>\r
#include <Library/ReportStatusCodeLib.h>\r
#include <Library/MemoryAllocationLib.h>\r
#include <Library/UefiBootServicesTableLib.h>\r
#include <Library/DevicePathLib.h>\r
#include <Library/PcdLib.h>\r
#include <Library/PeCoffLib.h>\r
\r
#include <IndustryStandard/Pci.h>\r
#include <IndustryStandard/PeImage.h>\r
#include <IndustryStandard/Acpi.h>\r
\r
typedef struct _PCI_IO_DEVICE              PCI_IO_DEVICE;\r
typedef struct _PCI_BAR                    PCI_BAR;\r
\r
typedef enum {\r
  PciBarTypeUnknown = 0,\r
  PciBarTypeIo16,\r
  PciBarTypeIo32,\r
  PciBarTypeMem32,\r
  PciBarTypePMem32,\r
  PciBarTypeMem64,\r
  PciBarTypePMem64,\r
  PciBarTypeIo,\r
  PciBarTypeMem,\r
  PciBarTypeMaxType\r
} PCI_BAR_TYPE;\r
\r
#include "ComponentName.h"\r
#include "PciIo.h"\r
#include "PciCommand.h"\r
#include "PciDeviceSupport.h"\r
#include "PciEnumerator.h"\r
#include "PciEnumeratorSupport.h"\r
#include "PciDriverOverride.h"\r
#include "PciRomTable.h"\r
#include "PciOptionRomSupport.h"\r
#include "PciPowerManagement.h"\r
#include "PciHotPlugSupport.h"\r
#include "PciLib.h"\r
\r
#define VGABASE1  0x3B0\r
#define VGALIMIT1 0x3BB\r
\r
#define VGABASE2  0x3C0\r
#define VGALIMIT2 0x3DF\r
\r
#define ISABASE   0x100\r
#define ISALIMIT  0x3FF\r
\r
//\r
// PCI BAR parameters\r
//\r
struct _PCI_BAR {\r
  UINT64        BaseAddress;\r
  UINT64        Length;\r
  UINT64        Alignment;\r
  PCI_BAR_TYPE  BarType;\r
  BOOLEAN       Prefetchable;\r
  UINT8         MemType;\r
  UINT8         Offset;\r
};\r
\r
//\r
// defined in PCI Card Specification, 8.0\r
//\r
#define PCI_CARD_MEMORY_BASE_0                0x1C\r
#define PCI_CARD_MEMORY_LIMIT_0               0x20\r
#define PCI_CARD_MEMORY_BASE_1                0x24\r
#define PCI_CARD_MEMORY_LIMIT_1               0x28\r
#define PCI_CARD_IO_BASE_0_LOWER              0x2C\r
#define PCI_CARD_IO_BASE_0_UPPER              0x2E\r
#define PCI_CARD_IO_LIMIT_0_LOWER             0x30\r
#define PCI_CARD_IO_LIMIT_0_UPPER             0x32\r
#define PCI_CARD_IO_BASE_1_LOWER              0x34\r
#define PCI_CARD_IO_BASE_1_UPPER              0x36\r
#define PCI_CARD_IO_LIMIT_1_LOWER             0x38\r
#define PCI_CARD_IO_LIMIT_1_UPPER             0x3A\r
#define PCI_CARD_BRIDGE_CONTROL               0x3E\r
\r
#define PCI_CARD_PREFETCHABLE_MEMORY_0_ENABLE BIT8\r
#define PCI_CARD_PREFETCHABLE_MEMORY_1_ENABLE BIT9\r
\r
#define PPB_BAR_0                             0\r
#define PPB_BAR_1                             1\r
#define PPB_IO_RANGE                          2\r
#define PPB_MEM32_RANGE                       3\r
#define PPB_PMEM32_RANGE                      4\r
#define PPB_PMEM64_RANGE                      5\r
#define PPB_MEM64_RANGE                       0xFF\r
\r
#define P2C_BAR_0                             0\r
#define P2C_MEM_1                             1\r
#define P2C_MEM_2                             2\r
#define P2C_IO_1                              3\r
#define P2C_IO_2                              4\r
\r
#define EFI_BRIDGE_IO32_DECODE_SUPPORTED      0x0001\r
#define EFI_BRIDGE_PMEM32_DECODE_SUPPORTED    0x0002\r
#define EFI_BRIDGE_PMEM64_DECODE_SUPPORTED    0x0004\r
#define EFI_BRIDGE_IO16_DECODE_SUPPORTED      0x0008\r
#define EFI_BRIDGE_PMEM_MEM_COMBINE_SUPPORTED 0x0010\r
#define EFI_BRIDGE_MEM64_DECODE_SUPPORTED     0x0020\r
#define EFI_BRIDGE_MEM32_DECODE_SUPPORTED     0x0040\r
\r
#define PCI_MAX_HOST_BRIDGE_NUM               0x0010\r
\r
//\r
// Define option for attribute\r
//\r
#define EFI_SET_SUPPORTS    0\r
#define EFI_SET_ATTRIBUTES  1\r
\r
#define PCI_IO_DEVICE_SIGNATURE               SIGNATURE_32 ('p', 'c', 'i', 'o')\r
\r
struct _PCI_IO_DEVICE {\r
  UINT32                                    Signature;\r
  EFI_HANDLE                                Handle;\r
  EFI_PCI_IO_PROTOCOL                       PciIo;\r
  LIST_ENTRY                                Link;\r
\r
  EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL PciDriverOverride;\r
  EFI_DEVICE_PATH_PROTOCOL                  *DevicePath;\r
  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL           *PciRootBridgeIo;\r
  EFI_LOAD_FILE2_PROTOCOL                   LoadFile2;\r
\r
  //\r
  // PCI configuration space header type\r
  //\r
  PCI_TYPE00                                Pci;\r
\r
  //\r
  // Bus number, Device number, Function number\r
  //\r
  UINT8                                     BusNumber;\r
  UINT8                                     DeviceNumber;\r
  UINT8                                     FunctionNumber;\r
\r
  //\r
  // BAR for this PCI Device\r
  //\r
  PCI_BAR                                   PciBar[PCI_MAX_BAR];\r
\r
  //\r
  // The bridge device this pci device is subject to\r
  //\r
  PCI_IO_DEVICE                             *Parent;\r
\r
  //\r
  // A linked list for children Pci Device if it is bridge device\r
  //\r
  LIST_ENTRY                                ChildList;\r
\r
  //\r
  // TURE if the PCI bus driver creates the handle for this PCI device\r
  //\r
  BOOLEAN                                   Registered;\r
\r
  //\r
  // TRUE if the PCI bus driver successfully allocates the resource required by\r
  // this PCI device\r
  //\r
  BOOLEAN                                   Allocated;\r
\r
  //\r
  // The attribute this PCI device currently set\r
  //\r
  UINT64                                    Attributes;\r
\r
  //\r
  // The attributes this PCI device actually supports\r
  //\r
  UINT64                                    Supports;\r
\r
  //\r
  // The resource decode the bridge supports\r
  //\r
  UINT32                                    Decodes;\r
\r
  //\r
  // The OptionRom Size\r
  //\r
  UINT64                                    RomSize;\r
\r
  //\r
  // The OptionRom Size\r
  //\r
  UINT64                                    RomBase;\r
\r
  //\r
  // TRUE if all OpROM (in device or in platform specific position) have been processed\r
  //\r
  BOOLEAN                                   AllOpRomProcessed;\r
\r
  //\r
  // TRUE if there is any EFI driver in the OptionRom\r
  //\r
  BOOLEAN                                   BusOverride;\r
\r
  //\r
  // A list tracking reserved resource on a bridge device\r
  //\r
  LIST_ENTRY                                ReservedResourceList;\r
\r
  //\r
  // A list tracking image handle of platform specific overriding driver\r
  //\r
  LIST_ENTRY                                OptionRomDriverList;\r
\r
  EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR         *ResourcePaddingDescriptors;\r
  EFI_HPC_PADDING_ATTRIBUTES                PaddingAttributes;\r
\r
  BOOLEAN                                   IsPciExp;\r
\r
};\r
\r
#define PCI_IO_DEVICE_FROM_PCI_IO_THIS(a) \\r
  CR (a, PCI_IO_DEVICE, PciIo, PCI_IO_DEVICE_SIGNATURE)\r
\r
#define PCI_IO_DEVICE_FROM_PCI_DRIVER_OVERRIDE_THIS(a) \\r
  CR (a, PCI_IO_DEVICE, PciDriverOverride, PCI_IO_DEVICE_SIGNATURE)\r
\r
#define PCI_IO_DEVICE_FROM_LINK(a) \\r
  CR (a, PCI_IO_DEVICE, Link, PCI_IO_DEVICE_SIGNATURE)\r
\r
#define PCI_IO_DEVICE_FROM_LOAD_FILE2_THIS(a) \\r
  CR (a, PCI_IO_DEVICE, LoadFile2, PCI_IO_DEVICE_SIGNATURE)\r
\r
\r
\r
//\r
// Global Variables\r
//\r
extern EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL *gEfiIncompatiblePciDeviceSupport;\r
extern EFI_DRIVER_BINDING_PROTOCOL                  gPciBusDriverBinding;\r
extern EFI_COMPONENT_NAME_PROTOCOL                  gPciBusComponentName;\r
extern EFI_COMPONENT_NAME2_PROTOCOL                 gPciBusComponentName2;\r
extern BOOLEAN                                      gFullEnumeration;\r
extern UINTN                                        gPciHostBridgeNumber;\r
extern EFI_HANDLE                                   gPciHostBrigeHandles[PCI_MAX_HOST_BRIDGE_NUM];\r
extern UINT64                                       gAllOne;\r
extern UINT64                                       gAllZero;\r
extern EFI_PCI_PLATFORM_PROTOCOL                    *gPciPlatformProtocol;\r
\r
\r
/**\r
  Macro that checks whether device is a GFX device.\r
\r
  @param  _p      Specified device.\r
\r
  @retval TRUE    Device is a a GFX device.\r
  @retval FALSE   Device is not a a GFX device.\r
\r
**/\r
#define IS_PCI_GFX(_p)     IS_CLASS2 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_OTHER)\r
\r
/**\r
  Test to see if this driver supports ControllerHandle. Any ControllerHandle\r
  than contains a gEfiPciRootBridgeIoProtocolGuid protocol can be supported.\r
\r
  @param  This                Protocol instance pointer.\r
  @param  Controller          Handle of device to test.\r
  @param  RemainingDevicePath Optional parameter use to pick a specific child.\r
                              device to start.\r
\r
  @retval EFI_SUCCESS         This driver supports this device.\r
  @retval EFI_ALREADY_STARTED This driver is already running on this device.\r
  @retval other               This driver does not support this device.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
PciBusDriverBindingSupported (\r
  IN EFI_DRIVER_BINDING_PROTOCOL    *This,\r
  IN EFI_HANDLE                     Controller,\r
  IN EFI_DEVICE_PATH_PROTOCOL       *RemainingDevicePath\r
  );\r
\r
/**\r
  Start this driver on ControllerHandle and enumerate Pci bus and start\r
  all device under PCI bus.\r
\r
  @param  This                 Protocol instance pointer.\r
  @param  Controller           Handle of device to bind driver to.\r
  @param  RemainingDevicePath  Optional parameter use to pick a specific child.\r
                               device to start.\r
\r
  @retval EFI_SUCCESS          This driver is added to ControllerHandle.\r
  @retval EFI_ALREADY_STARTED  This driver is already running on ControllerHandle.\r
  @retval other                This driver does not support this device.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
PciBusDriverBindingStart (\r
  IN EFI_DRIVER_BINDING_PROTOCOL    *This,\r
  IN EFI_HANDLE                     Controller,\r
  IN EFI_DEVICE_PATH_PROTOCOL       *RemainingDevicePath\r
  );\r
\r
/**\r
  Stop this driver on ControllerHandle. Support stoping any child handles\r
  created by this driver.\r
\r
  @param  This              Protocol instance pointer.\r
  @param  Controller        Handle of device to stop driver on.\r
  @param  NumberOfChildren  Number of Handles in ChildHandleBuffer. If number of\r
                            children is zero stop the entire bus driver.\r
  @param  ChildHandleBuffer List of Child Handles to Stop.\r
\r
  @retval EFI_SUCCESS       This driver is removed ControllerHandle.\r
  @retval other             This driver was not removed from this device.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
PciBusDriverBindingStop (\r
  IN  EFI_DRIVER_BINDING_PROTOCOL   *This,\r
  IN  EFI_HANDLE                    Controller,\r
  IN  UINTN                         NumberOfChildren,\r
  IN  EFI_HANDLE                    *ChildHandleBuffer\r
  );\r
\r
#endif\r
Commit	Line	Data
eeefcb9d	1	/** @file\r
48a9ea7b	2	Header files and data structures needed by PCI Bus module.\r
ead42efc	3	\r
c72216a6	4	Copyright (c) 2006 - 2009, Intel Corporation\r
ea5632e5	5	All rights reserved. This program and the accompanying materials\r
	6	are licensed and made available under the terms and conditions of the BSD License\r
	7	which accompanies this distribution. The full text of the license may be found at\r
	8	http://opensource.org/licenses/bsd-license.php\r
	9	\r
	10	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	11	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
ead42efc	12	\r
3db51098	13	**/\r
ead42efc	14	\r
ead42efc	15	\r
eeefcb9d	16	#ifndef _EFI_PCI_BUS_H_\r
eeefcb9d	17	#define _EFI_PCI_BUS_H_\r
ead42efc	18	\r
694b922c	19	#include <FrameworkDxe.h>\r
694b922c	20	\r
ead42efc	21	#include <Protocol/LoadedImage.h>\r
	22	#include <Protocol/PciHostBridgeResourceAllocation.h>\r
	23	#include <Protocol/PciIo.h>\r
8e6b0dcb	24	#include <Protocol/LoadFile2.h>\r
ead42efc	25	#include <Protocol/PciRootBridgeIo.h>\r
	26	#include <Protocol/PciHotPlugRequest.h>\r
	27	#include <Protocol/DevicePath.h>\r
	28	#include <Protocol/PciPlatform.h>\r
	29	#include <Protocol/PciHotPlugInit.h>\r
	30	#include <Protocol/Decompress.h>\r
ead42efc	31	#include <Protocol/BusSpecificDriverOverride.h>\r
ea5632e5	32	#include <Protocol/IncompatiblePciDeviceSupport.h>\r
ed7748fe	33	\r
ead42efc	34	#include <Library/DebugLib.h>\r
	35	#include <Library/UefiDriverEntryPoint.h>\r
	36	#include <Library/BaseLib.h>\r
	37	#include <Library/UefiLib.h>\r
	38	#include <Library/BaseMemoryLib.h>\r
	39	#include <Library/ReportStatusCodeLib.h>\r
	40	#include <Library/MemoryAllocationLib.h>\r
	41	#include <Library/UefiBootServicesTableLib.h>\r
	42	#include <Library/DevicePathLib.h>\r
	43	#include <Library/PcdLib.h>\r
2fb718b0	44	#include <Library/PeCoffLib.h>\r
ead42efc	45	\r
bc14bdb3	46	#include <IndustryStandard/Pci.h>\r
b1ef4015	47	#include <IndustryStandard/PeImage.h>\r
ead42efc	48	#include <IndustryStandard/Acpi.h>\r
9f6531d1	49	\r
48a9ea7b	50	typedef struct _PCI_IO_DEVICE PCI_IO_DEVICE;\r
48a9ea7b	51	typedef struct _PCI_BAR PCI_BAR;\r
71b320c7	52	\r
	53	typedef enum {\r
	54	PciBarTypeUnknown = 0,\r
	55	PciBarTypeIo16,\r
	56	PciBarTypeIo32,\r
	57	PciBarTypeMem32,\r
	58	PciBarTypePMem32,\r
	59	PciBarTypeMem64,\r
	60	PciBarTypePMem64,\r
	61	PciBarTypeIo,\r
	62	PciBarTypeMem,\r
	63	PciBarTypeMaxType\r
	64	} PCI_BAR_TYPE;\r
9f6531d1	65	\r
48a9ea7b	66	#include "ComponentName.h"\r
	67	#include "PciIo.h"\r
	68	#include "PciCommand.h"\r
	69	#include "PciDeviceSupport.h"\r
	70	#include "PciEnumerator.h"\r
	71	#include "PciEnumeratorSupport.h"\r
	72	#include "PciDriverOverride.h"\r
	73	#include "PciRomTable.h"\r
	74	#include "PciOptionRomSupport.h"\r
	75	#include "PciPowerManagement.h"\r
	76	#include "PciHotPlugSupport.h"\r
	77	#include "PciLib.h"\r
ead42efc	78	\r
	79	#define VGABASE1 0x3B0\r
	80	#define VGALIMIT1 0x3BB\r
	81	\r
	82	#define VGABASE2 0x3C0\r
	83	#define VGALIMIT2 0x3DF\r
	84	\r
	85	#define ISABASE 0x100\r
	86	#define ISALIMIT 0x3FF\r
	87	\r
48a9ea7b	88	//\r
	89	// PCI BAR parameters\r
	90	//\r
	91	struct _PCI_BAR {\r
ead42efc	92	UINT64 BaseAddress;\r
	93	UINT64 Length;\r
	94	UINT64 Alignment;\r
	95	PCI_BAR_TYPE BarType;\r
	96	BOOLEAN Prefetchable;\r
	97	UINT8 MemType;\r
	98	UINT8 Offset;\r
48a9ea7b	99	};\r
ead42efc	100	\r
8e8227d1	101	//\r
	102	// defined in PCI Card Specification, 8.0\r
	103	//\r
	104	#define PCI_CARD_MEMORY_BASE_0 0x1C\r
	105	#define PCI_CARD_MEMORY_LIMIT_0 0x20\r
	106	#define PCI_CARD_MEMORY_BASE_1 0x24\r
	107	#define PCI_CARD_MEMORY_LIMIT_1 0x28\r
	108	#define PCI_CARD_IO_BASE_0_LOWER 0x2C\r
	109	#define PCI_CARD_IO_BASE_0_UPPER 0x2E\r
	110	#define PCI_CARD_IO_LIMIT_0_LOWER 0x30\r
	111	#define PCI_CARD_IO_LIMIT_0_UPPER 0x32\r
	112	#define PCI_CARD_IO_BASE_1_LOWER 0x34\r
	113	#define PCI_CARD_IO_BASE_1_UPPER 0x36\r
	114	#define PCI_CARD_IO_LIMIT_1_LOWER 0x38\r
	115	#define PCI_CARD_IO_LIMIT_1_UPPER 0x3A\r
	116	#define PCI_CARD_BRIDGE_CONTROL 0x3E\r
	117	\r
	118	#define PCI_CARD_PREFETCHABLE_MEMORY_0_ENABLE BIT8\r
	119	#define PCI_CARD_PREFETCHABLE_MEMORY_1_ENABLE BIT9\r
	120	\r
ead42efc	121	#define PPB_BAR_0 0\r
	122	#define PPB_BAR_1 1\r
	123	#define PPB_IO_RANGE 2\r
	124	#define PPB_MEM32_RANGE 3\r
	125	#define PPB_PMEM32_RANGE 4\r
	126	#define PPB_PMEM64_RANGE 5\r
	127	#define PPB_MEM64_RANGE 0xFF\r
	128	\r
	129	#define P2C_BAR_0 0\r
	130	#define P2C_MEM_1 1\r
	131	#define P2C_MEM_2 2\r
	132	#define P2C_IO_1 3\r
	133	#define P2C_IO_2 4\r
	134	\r
ead42efc	135	#define EFI_BRIDGE_IO32_DECODE_SUPPORTED 0x0001\r
	136	#define EFI_BRIDGE_PMEM32_DECODE_SUPPORTED 0x0002\r
	137	#define EFI_BRIDGE_PMEM64_DECODE_SUPPORTED 0x0004\r
	138	#define EFI_BRIDGE_IO16_DECODE_SUPPORTED 0x0008\r
	139	#define EFI_BRIDGE_PMEM_MEM_COMBINE_SUPPORTED 0x0010\r
	140	#define EFI_BRIDGE_MEM64_DECODE_SUPPORTED 0x0020\r
	141	#define EFI_BRIDGE_MEM32_DECODE_SUPPORTED 0x0040\r
	142	\r
	143	#define PCI_MAX_HOST_BRIDGE_NUM 0x0010\r
ead42efc	144	\r
	145	//\r
	146	// Define option for attribute\r
	147	//\r
	148	#define EFI_SET_SUPPORTS 0\r
	149	#define EFI_SET_ATTRIBUTES 1\r
	150	\r
48a9ea7b	151	#define PCI_IO_DEVICE_SIGNATURE SIGNATURE_32 ('p', 'c', 'i', 'o')\r
c72216a6	152	\r
c72216a6	153	struct _PCI_IO_DEVICE {\r
ead42efc	154	UINT32 Signature;\r
	155	EFI_HANDLE Handle;\r
	156	EFI_PCI_IO_PROTOCOL PciIo;\r
	157	LIST_ENTRY Link;\r
	158	\r
	159	EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL PciDriverOverride;\r
	160	EFI_DEVICE_PATH_PROTOCOL *DevicePath;\r
	161	EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;\r
8e6b0dcb	162	EFI_LOAD_FILE2_PROTOCOL LoadFile2;\r
ead42efc	163	\r
	164	//\r
	165	// PCI configuration space header type\r
	166	//\r
	167	PCI_TYPE00 Pci;\r
	168	\r
	169	//\r
	170	// Bus number, Device number, Function number\r
	171	//\r
	172	UINT8 BusNumber;\r
	173	UINT8 DeviceNumber;\r
	174	UINT8 FunctionNumber;\r
	175	\r
	176	//\r
	177	// BAR for this PCI Device\r
	178	//\r
	179	PCI_BAR PciBar[PCI_MAX_BAR];\r
	180	\r
	181	//\r
	182	// The bridge device this pci device is subject to\r
	183	//\r
c72216a6	184	PCI_IO_DEVICE *Parent;\r
ead42efc	185	\r
	186	//\r
	187	// A linked list for children Pci Device if it is bridge device\r
	188	//\r
	189	LIST_ENTRY ChildList;\r
	190	\r
	191	//\r
	192	// TURE if the PCI bus driver creates the handle for this PCI device\r
	193	//\r
	194	BOOLEAN Registered;\r
	195	\r
	196	//\r
	197	// TRUE if the PCI bus driver successfully allocates the resource required by\r
	198	// this PCI device\r
	199	//\r
	200	BOOLEAN Allocated;\r
	201	\r
	202	//\r
	203	// The attribute this PCI device currently set\r
	204	//\r
	205	UINT64 Attributes;\r
	206	\r
	207	//\r
	208	// The attributes this PCI device actually supports\r
	209	//\r
	210	UINT64 Supports;\r
	211	\r
	212	//\r
	213	// The resource decode the bridge supports\r
	214	//\r
	215	UINT32 Decodes;\r
	216	\r
	217	//\r
	218	// The OptionRom Size\r
	219	//\r
	220	UINT64 RomSize;\r
	221	\r
	222	//\r
	223	// The OptionRom Size\r
	224	//\r
	225	UINT64 RomBase;\r
	226	\r
	227	//\r
	228	// TRUE if all OpROM (in device or in platform specific position) have been processed\r
	229	//\r
	230	BOOLEAN AllOpRomProcessed;\r
	231	\r
	232	//\r
	233	// TRUE if there is any EFI driver in the OptionRom\r
	234	//\r
	235	BOOLEAN BusOverride;\r
	236	\r
	237	//\r
48a9ea7b	238	// A list tracking reserved resource on a bridge device\r
ead42efc	239	//\r
	240	LIST_ENTRY ReservedResourceList;\r
	241	\r
	242	//\r
	243	// A list tracking image handle of platform specific overriding driver\r
	244	//\r
	245	LIST_ENTRY OptionRomDriverList;\r
	246	\r
	247	EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *ResourcePaddingDescriptors;\r
	248	EFI_HPC_PADDING_ATTRIBUTES PaddingAttributes;\r
	249	\r
	250	BOOLEAN IsPciExp;\r
	251	\r
c72216a6	252	};\r
ead42efc	253	\r
ead42efc	254	#define PCI_IO_DEVICE_FROM_PCI_IO_THIS(a) \\r
	255	CR (a, PCI_IO_DEVICE, PciIo, PCI_IO_DEVICE_SIGNATURE)\r
	256	\r
	257	#define PCI_IO_DEVICE_FROM_PCI_DRIVER_OVERRIDE_THIS(a) \\r
	258	CR (a, PCI_IO_DEVICE, PciDriverOverride, PCI_IO_DEVICE_SIGNATURE)\r
	259	\r
	260	#define PCI_IO_DEVICE_FROM_LINK(a) \\r
	261	CR (a, PCI_IO_DEVICE, Link, PCI_IO_DEVICE_SIGNATURE)\r
	262	\r
8e6b0dcb	263	#define PCI_IO_DEVICE_FROM_LOAD_FILE2_THIS(a) \\r
	264	CR (a, PCI_IO_DEVICE, LoadFile2, PCI_IO_DEVICE_SIGNATURE)\r
	265	\r
48a9ea7b	266	\r
48a9ea7b	267	\r
ead42efc	268	//\r
	269	// Global Variables\r
	270	//\r
48a9ea7b	271	extern EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL *gEfiIncompatiblePciDeviceSupport;\r
	272	extern EFI_DRIVER_BINDING_PROTOCOL gPciBusDriverBinding;\r
	273	extern EFI_COMPONENT_NAME_PROTOCOL gPciBusComponentName;\r
	274	extern EFI_COMPONENT_NAME2_PROTOCOL gPciBusComponentName2;\r
ead42efc	275	extern BOOLEAN gFullEnumeration;\r
	276	extern UINTN gPciHostBridgeNumber;\r
	277	extern EFI_HANDLE gPciHostBrigeHandles[PCI_MAX_HOST_BRIDGE_NUM];\r
	278	extern UINT64 gAllOne;\r
	279	extern UINT64 gAllZero;\r
ead42efc	280	extern EFI_PCI_PLATFORM_PROTOCOL *gPciPlatformProtocol;\r
ead42efc	281	\r
ead42efc	282	\r
8e8227d1	283	/**\r
48a9ea7b	284	Macro that checks whether device is a GFX device.\r
	285	\r
	286	@param _p Specified device.\r
	287	\r
	288	@retval TRUE Device is a a GFX device.\r
	289	@retval FALSE Device is not a a GFX device.\r
	290	\r
	291	**/\r
	292	#define IS_PCI_GFX(_p) IS_CLASS2 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_OTHER)\r
	293	\r
eeefcb9d	294	/**\r
	295	Test to see if this driver supports ControllerHandle. Any ControllerHandle\r
	296	than contains a gEfiPciRootBridgeIoProtocolGuid protocol can be supported.\r
	297	\r
	298	@param This Protocol instance pointer.\r
48a9ea7b	299	@param Controller Handle of device to test.\r
eeefcb9d	300	@param RemainingDevicePath Optional parameter use to pick a specific child.\r
	301	device to start.\r
	302	\r
	303	@retval EFI_SUCCESS This driver supports this device.\r
	304	@retval EFI_ALREADY_STARTED This driver is already running on this device.\r
	305	@retval other This driver does not support this device.\r
	306	\r
	307	**/\r
ead42efc	308	EFI_STATUS\r
	309	EFIAPI\r
	310	PciBusDriverBindingSupported (\r
	311	IN EFI_DRIVER_BINDING_PROTOCOL *This,\r
	312	IN EFI_HANDLE Controller,\r
	313	IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath\r
	314	);\r
	315	\r
eeefcb9d	316	/**\r
	317	Start this driver on ControllerHandle and enumerate Pci bus and start\r
	318	all device under PCI bus.\r
	319	\r
	320	@param This Protocol instance pointer.\r
48a9ea7b	321	@param Controller Handle of device to bind driver to.\r
eeefcb9d	322	@param RemainingDevicePath Optional parameter use to pick a specific child.\r
	323	device to start.\r
	324	\r
	325	@retval EFI_SUCCESS This driver is added to ControllerHandle.\r
	326	@retval EFI_ALREADY_STARTED This driver is already running on ControllerHandle.\r
	327	@retval other This driver does not support this device.\r
	328	\r
	329	**/\r
ead42efc	330	EFI_STATUS\r
	331	EFIAPI\r
	332	PciBusDriverBindingStart (\r
	333	IN EFI_DRIVER_BINDING_PROTOCOL *This,\r
	334	IN EFI_HANDLE Controller,\r
	335	IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath\r
	336	);\r
	337	\r
eeefcb9d	338	/**\r
	339	Stop this driver on ControllerHandle. Support stoping any child handles\r
	340	created by this driver.\r
	341	\r
	342	@param This Protocol instance pointer.\r
48a9ea7b	343	@param Controller Handle of device to stop driver on.\r
eeefcb9d	344	@param NumberOfChildren Number of Handles in ChildHandleBuffer. If number of\r
	345	children is zero stop the entire bus driver.\r
	346	@param ChildHandleBuffer List of Child Handles to Stop.\r
	347	\r
	348	@retval EFI_SUCCESS This driver is removed ControllerHandle.\r
	349	@retval other This driver was not removed from this device.\r
	350	\r
	351	**/\r
ead42efc	352	EFI_STATUS\r
	353	EFIAPI\r
	354	PciBusDriverBindingStop (\r
	355	IN EFI_DRIVER_BINDING_PROTOCOL *This,\r
	356	IN EFI_HANDLE Controller,\r
	357	IN UINTN NumberOfChildren,\r
	358	IN EFI_HANDLE *ChildHandleBuffer\r
	359	);\r
	360	\r
	361	#endif\r