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3db51098 1/**@file\r
57076f45 2 Implement all interfaces for EFI_PCI_IO_PROTOCOL.\r
3 \r
9a2d4fe9 4Copyright (c) 2006 - 2008, Intel Corporation \r
ead42efc 5All rights reserved. This program and the accompanying materials \r
6are licensed and made available under the terms and conditions of the BSD License \r
7which accompanies this distribution. The full text of the license may be found at \r
8http://opensource.org/licenses/bsd-license.php \r
9 \r
10THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
11WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
12\r
3db51098 13**/\r
ead42efc 14\r
ead42efc 15\r
03417d8d 16#include "PciBus.h"\r
ead42efc 17\r
18//\r
19// Internal use only\r
20//\r
ead42efc 21EFI_STATUS\r
22ReportErrorStatusCode (\r
23 IN PCI_IO_DEVICE *PciIoDevice,\r
24 IN EFI_STATUS_CODE_VALUE Code\r
25 );\r
26\r
27//\r
28// PCI I/O Support Function Prototypes\r
29//\r
30//\r
31//\r
32// Pci Io Protocol Interface\r
33//\r
819d1488 34EFI_PCI_IO_PROTOCOL PciIoInterface = {\r
ead42efc 35 PciIoPollMem,\r
36 PciIoPollIo,\r
37 {\r
38 PciIoMemRead,\r
39 PciIoMemWrite\r
40 },\r
41 {\r
42 PciIoIoRead,\r
43 PciIoIoWrite\r
44 },\r
45 {\r
46 PciIoConfigRead,\r
47 PciIoConfigWrite\r
48 },\r
49 PciIoCopyMem,\r
50 PciIoMap,\r
51 PciIoUnmap,\r
52 PciIoAllocateBuffer,\r
53 PciIoFreeBuffer,\r
54 PciIoFlush,\r
55 PciIoGetLocation,\r
56 PciIoAttributes,\r
57 PciIoGetBarAttributes,\r
58 PciIoSetBarAttributes,\r
59 0,\r
60 NULL\r
61};\r
62\r
57076f45 63/**\r
64 report a error Status code of PCI bus driver controller\r
65 \r
66 @param PciIoDevice Pci device instance\r
67 @param Code status code\r
68**/\r
ead42efc 69EFI_STATUS\r
70ReportErrorStatusCode (\r
71 IN PCI_IO_DEVICE *PciIoDevice,\r
72 IN EFI_STATUS_CODE_VALUE Code\r
73 )\r
ead42efc 74{\r
75 return REPORT_STATUS_CODE_WITH_DEVICE_PATH (\r
76 EFI_ERROR_CODE | EFI_ERROR_MINOR,\r
77 Code,\r
78 PciIoDevice->DevicePath\r
79 );\r
80}\r
81\r
bcd70414 82/**\r
ead42efc 83 Initializes a PCI I/O Instance\r
ead42efc 84 \r
57076f45 85 @param PciIoDevice Pci device instance\r
86 \r
87 @retval EFI_SUCCESS Success operation\r
bcd70414 88**/\r
57076f45 89EFI_STATUS\r
90InitializePciIoInstance (\r
91 PCI_IO_DEVICE *PciIoDevice\r
92 )\r
ead42efc 93{\r
94 CopyMem (&PciIoDevice->PciIo, &PciIoInterface, sizeof (EFI_PCI_IO_PROTOCOL));\r
95 return EFI_SUCCESS;\r
96}\r
97\r
57076f45 98/**\r
99 Verifies access to a PCI Base Address Register (BAR)\r
100 \r
101 @param PciIoDevice Pci device instance\r
102 @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r
103 base address for the memory or I/O operation to perform. \r
104 @param Type Operation type could be memory or I/O\r
105 @param Width Signifies the width of the memory or I/O operations.\r
106 @param Count The number of memory or I/O operations to perform.\r
107 @param Offset The offset within the PCI configuration space for the PCI controller.\r
108 \r
109 @retval EFI_INVALID_PARAMETER Invalid Width/BarIndex or Bar type.\r
110 @retval EFI_SUCCESS Success Operation.\r
111**/\r
ead42efc 112EFI_STATUS\r
113PciIoVerifyBarAccess (\r
114 PCI_IO_DEVICE *PciIoDevice,\r
115 UINT8 BarIndex,\r
116 PCI_BAR_TYPE Type,\r
117 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
118 IN UINTN Count,\r
119 UINT64 *Offset\r
120 )\r
ead42efc 121{\r
122 if (Width < 0 || Width >= EfiPciIoWidthMaximum) {\r
123 return EFI_INVALID_PARAMETER;\r
124 }\r
125\r
126 if (BarIndex == EFI_PCI_IO_PASS_THROUGH_BAR) {\r
127 return EFI_SUCCESS;\r
128 }\r
129\r
130 //\r
131 // BarIndex 0-5 is legal\r
132 //\r
133 if (BarIndex >= PCI_MAX_BAR) {\r
134 return EFI_INVALID_PARAMETER;\r
135 }\r
136\r
137 if (!CheckBarType (PciIoDevice, BarIndex, Type)) {\r
138 return EFI_INVALID_PARAMETER;\r
139 }\r
140\r
141 //\r
142 // If Width is EfiPciIoWidthFifoUintX then convert to EfiPciIoWidthUintX\r
143 // If Width is EfiPciIoWidthFillUintX then convert to EfiPciIoWidthUintX\r
144 //\r
145 if (Width >= EfiPciWidthFifoUint8 && Width <= EfiPciWidthFifoUint64) {\r
146 Count = 1;\r
147 }\r
148\r
149 Width = (EFI_PCI_IO_PROTOCOL_WIDTH) (Width & 0x03);\r
150\r
151 if ((*Offset + Count * (UINTN)(1 << Width)) - 1 >= PciIoDevice->PciBar[BarIndex].Length) {\r
152 return EFI_INVALID_PARAMETER;\r
153 }\r
154\r
155 *Offset = *Offset + PciIoDevice->PciBar[BarIndex].BaseAddress;\r
156\r
157 return EFI_SUCCESS;\r
158}\r
159\r
57076f45 160/**\r
161 Verifies access to a PCI Config Header\r
162 \r
163 @param PciIoDevice Pci device instance\r
164 @param Width Signifies the width of the memory or I/O operations.\r
165 @param Count The number of memory or I/O operations to perform.\r
166 @param Offset The offset within the PCI configuration space for the PCI controller.\r
167\r
168 @retval EFI_INVALID_PARAMETER Invalid Width\r
169 @retval EFI_UNSUPPORTED Offset overflow\r
170 @retval EFI_SUCCESS Success operation\r
171**/\r
ead42efc 172EFI_STATUS\r
173PciIoVerifyConfigAccess (\r
174 PCI_IO_DEVICE *PciIoDevice,\r
175 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
176 IN UINTN Count,\r
177 IN UINT64 *Offset\r
178 )\r
ead42efc 179{\r
180 UINT64 ExtendOffset;\r
181\r
182 if (Width < 0 || Width >= EfiPciIoWidthMaximum) {\r
183 return EFI_INVALID_PARAMETER;\r
184 }\r
185\r
186 //\r
187 // If Width is EfiPciIoWidthFillUintX then convert to EfiPciIoWidthUintX\r
188 //\r
189 Width = (EFI_PCI_IO_PROTOCOL_WIDTH) (Width & 0x03);\r
190\r
191 if (PciIoDevice->IsPciExp) {\r
192 if ((*Offset + Count * (UINTN)(1 << Width)) - 1 >= PCI_EXP_MAX_CONFIG_OFFSET) {\r
193 return EFI_UNSUPPORTED;\r
194 }\r
195\r
196 ExtendOffset = LShiftU64 (*Offset, 32);\r
197 *Offset = EFI_PCI_ADDRESS (PciIoDevice->BusNumber, PciIoDevice->DeviceNumber, PciIoDevice->FunctionNumber, 0);\r
198 *Offset = (*Offset) | ExtendOffset;\r
199\r
200 } else {\r
201 if ((*Offset + Count * (UINTN)(1 << Width)) - 1 >= PCI_MAX_CONFIG_OFFSET) {\r
202 return EFI_UNSUPPORTED;\r
203 }\r
204\r
205 *Offset = EFI_PCI_ADDRESS (PciIoDevice->BusNumber, PciIoDevice->DeviceNumber, PciIoDevice->FunctionNumber, *Offset);\r
206 }\r
207\r
208 return EFI_SUCCESS;\r
209}\r
210\r
57076f45 211/**\r
212 Reads from the I/O space of a PCI Root Bridge. Returns when either the polling exit criteria is\r
213 satisfied or after a defined duration.\r
214 \r
215 @param This Pointer to protocol instance of EFI_PCI_IO_PROTOCOL\r
216 @param Width Signifies the width of the memory or I/O operations.\r
217 @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r
218 base address for the memory or I/O operation to perform. \r
219 @param Offset The offset within the PCI configuration space for the PCI controller.\r
220 @param Mask Mask used for the polling criteria.\r
221 @param Value The comparison value used for the polling exit criteria.\r
222 @param Delay The number of 100 ns units to poll.\r
223 @param Result Pointer to the last value read from the memory location.\r
224 \r
225 @retval EFI_SUCCESS The last data returned from the access matched the poll exit criteria.\r
226 @retval EFI_TIMEOUT Delay expired before a match occurred.\r
227 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
228 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
229**/\r
ead42efc 230EFI_STATUS\r
231EFIAPI\r
232PciIoPollMem (\r
233 IN EFI_PCI_IO_PROTOCOL *This,\r
234 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
235 IN UINT8 BarIndex,\r
236 IN UINT64 Offset,\r
237 IN UINT64 Mask,\r
238 IN UINT64 Value,\r
239 IN UINT64 Delay,\r
240 OUT UINT64 *Result\r
241 )\r
ead42efc 242{\r
243 EFI_STATUS Status;\r
244 PCI_IO_DEVICE *PciIoDevice;\r
245\r
246 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);\r
247\r
248 if (Width < 0 || Width >= EfiPciIoWidthMaximum) {\r
249 return EFI_INVALID_PARAMETER;\r
250 }\r
251\r
252 Status = PciIoVerifyBarAccess (PciIoDevice, BarIndex, PciBarTypeMem, Width, 1, &Offset);\r
253 if (EFI_ERROR (Status)) {\r
254 return EFI_UNSUPPORTED;\r
255 }\r
256\r
257 if (Width > EfiPciIoWidthUint64) {\r
258 return EFI_INVALID_PARAMETER;\r
259 }\r
260\r
261 Status = PciIoDevice->PciRootBridgeIo->PollMem (\r
262 PciIoDevice->PciRootBridgeIo,\r
263 (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,\r
264 Offset,\r
265 Mask,\r
266 Value,\r
267 Delay,\r
268 Result\r
269 );\r
270\r
271 if (EFI_ERROR (Status)) {\r
272 ReportErrorStatusCode (PciIoDevice, EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR);\r
273 }\r
274\r
275 return Status;\r
276}\r
277\r
57076f45 278/** \r
279 Reads from the I/O space of a PCI Root Bridge. Returns when either the polling exit criteria is\r
280 satisfied or after a defined duration.\r
281 \r
282 @param This A pointer to the EFI_PCI_IO_PROTOCOL.\r
283 @param Width Signifies the width of the memory or I/O operations.\r
284 @param Address The base address of the memory or I/O operations. \r
285 @param Mask Mask used for the polling criteria.\r
286 @param Value The comparison value used for the polling exit criteria.\r
287 @param Delay The number of 100 ns units to poll.\r
288 @param Result Pointer to the last value read from the memory location.\r
289 \r
290 @retval EFI_SUCCESS The last data returned from the access matched the poll exit criteria.\r
291 @retval EFI_TIMEOUT Delay expired before a match occurred.\r
292 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
293 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
294 \r
295**/\r
ead42efc 296EFI_STATUS\r
297EFIAPI\r
298PciIoPollIo (\r
299 IN EFI_PCI_IO_PROTOCOL *This,\r
300 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
301 IN UINT8 BarIndex,\r
302 IN UINT64 Offset,\r
303 IN UINT64 Mask,\r
304 IN UINT64 Value,\r
305 IN UINT64 Delay,\r
306 OUT UINT64 *Result\r
307 )\r
ead42efc 308{\r
309 EFI_STATUS Status;\r
310 PCI_IO_DEVICE *PciIoDevice;\r
311\r
312 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);\r
313\r
314 if (Width < 0 || Width > EfiPciIoWidthUint64) {\r
315 return EFI_INVALID_PARAMETER;\r
316 }\r
317\r
318 Status = PciIoVerifyBarAccess (PciIoDevice, BarIndex, PciBarTypeIo, Width, 1, &Offset);\r
319 if (EFI_ERROR (Status)) {\r
320 return EFI_UNSUPPORTED;\r
321 }\r
322\r
323 Status = PciIoDevice->PciRootBridgeIo->PollIo (\r
324 PciIoDevice->PciRootBridgeIo,\r
325 (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,\r
326 Offset,\r
327 Mask,\r
328 Value,\r
329 Delay,\r
330 Result\r
331 );\r
332\r
333 if (EFI_ERROR (Status)) {\r
334 ReportErrorStatusCode (PciIoDevice, EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR);\r
335 }\r
336\r
337 return Status;\r
338}\r
339\r
57076f45 340/** \r
341 Enable a PCI driver to access PCI controller registers in the PCI memory or I/O space.\r
342 \r
343 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
344 @param Width Signifies the width of the memory or I/O operations.\r
345 @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r
346 base address for the memory or I/O operation to perform. \r
347 @param Offset The offset within the selected BAR to start the memory or I/O operation. \r
348 @param Count The number of memory or I/O operations to perform.\r
349 @param Buffer For read operations, the destination buffer to store the results. For write\r
350 operations, the source buffer to write data from. \r
351 \r
352 @retval EFI_SUCCESS The data was read from or written to the PCI controller.\r
353 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r
354 @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not\r
355 valid for the PCI BAR specified by BarIndex. \r
356 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
357 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
358 \r
359**/\r
ead42efc 360EFI_STATUS\r
361EFIAPI\r
362PciIoMemRead (\r
363 IN EFI_PCI_IO_PROTOCOL *This,\r
364 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
365 IN UINT8 BarIndex,\r
366 IN UINT64 Offset,\r
367 IN UINTN Count,\r
368 IN OUT VOID *Buffer\r
369 )\r
ead42efc 370{\r
371 EFI_STATUS Status;\r
372 PCI_IO_DEVICE *PciIoDevice;\r
373\r
374 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);\r
375\r
376 if (Width < 0 || Width >= EfiPciIoWidthMaximum) {\r
377 return EFI_INVALID_PARAMETER;\r
378 }\r
379\r
9a2d4fe9 380 if (Buffer == NULL) {\r
381 return EFI_INVALID_PARAMETER;\r
382 }\r
383\r
ead42efc 384 Status = PciIoVerifyBarAccess (PciIoDevice, BarIndex, PciBarTypeMem, Width, Count, &Offset);\r
385 if (EFI_ERROR (Status)) {\r
386 return EFI_UNSUPPORTED;\r
387 }\r
388\r
389 Status = PciIoDevice->PciRootBridgeIo->Mem.Read (\r
390 PciIoDevice->PciRootBridgeIo,\r
391 (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,\r
392 Offset,\r
393 Count,\r
394 Buffer\r
395 );\r
396\r
397 if (EFI_ERROR (Status)) {\r
398 ReportErrorStatusCode (PciIoDevice, EFI_IO_BUS_PCI | EFI_IOB_EC_READ_ERROR);\r
399 }\r
400\r
401 return Status;\r
402}\r
403\r
57076f45 404/** \r
405 Enable a PCI driver to access PCI controller registers in the PCI memory or I/O space.\r
406 \r
407 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
408 @param Width Signifies the width of the memory or I/O operations.\r
409 @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r
410 base address for the memory or I/O operation to perform. \r
411 @param Offset The offset within the selected BAR to start the memory or I/O operation. \r
412 @param Count The number of memory or I/O operations to perform.\r
413 @param Buffer For read operations, the destination buffer to store the results. For write\r
414 operations, the source buffer to write data from. \r
415 \r
416 @retval EFI_SUCCESS The data was read from or written to the PCI controller.\r
417 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r
418 @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not\r
419 valid for the PCI BAR specified by BarIndex. \r
420 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
421 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
422 \r
423**/\r
ead42efc 424EFI_STATUS\r
425EFIAPI\r
426PciIoMemWrite (\r
427 IN EFI_PCI_IO_PROTOCOL *This,\r
428 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
429 IN UINT8 BarIndex,\r
430 IN UINT64 Offset,\r
431 IN UINTN Count,\r
432 IN OUT VOID *Buffer\r
433 )\r
ead42efc 434{\r
435 EFI_STATUS Status;\r
436 PCI_IO_DEVICE *PciIoDevice;\r
437\r
438 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);\r
439\r
440 if (Width < 0 || Width >= EfiPciIoWidthMaximum) {\r
441 return EFI_INVALID_PARAMETER;\r
442 }\r
443\r
9a2d4fe9 444 if (Buffer == NULL) {\r
445 return EFI_INVALID_PARAMETER;\r
446 }\r
447\r
ead42efc 448 Status = PciIoVerifyBarAccess (PciIoDevice, BarIndex, PciBarTypeMem, Width, Count, &Offset);\r
449 if (EFI_ERROR (Status)) {\r
450 return EFI_UNSUPPORTED;\r
451 }\r
452\r
453 Status = PciIoDevice->PciRootBridgeIo->Mem.Write (\r
454 PciIoDevice->PciRootBridgeIo,\r
455 (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,\r
456 Offset,\r
457 Count,\r
458 Buffer\r
459 );\r
460\r
461 if (EFI_ERROR (Status)) {\r
462 ReportErrorStatusCode (PciIoDevice, EFI_IO_BUS_PCI | EFI_IOB_EC_WRITE_ERROR);\r
463 }\r
464\r
465 return Status;\r
466}\r
467\r
57076f45 468/** \r
469 Enable a PCI driver to access PCI controller registers in the PCI memory or I/O space.\r
470 \r
471 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
472 @param Width Signifies the width of the memory or I/O operations.\r
473 @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r
474 base address for the memory or I/O operation to perform. \r
475 @param Offset The offset within the selected BAR to start the memory or I/O operation. \r
476 @param Count The number of memory or I/O operations to perform.\r
477 @param Buffer For read operations, the destination buffer to store the results. For write\r
478 operations, the source buffer to write data from. \r
479 \r
480 @retval EFI_SUCCESS The data was read from or written to the PCI controller.\r
481 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r
482 @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not\r
483 valid for the PCI BAR specified by BarIndex. \r
484 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
485 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
486 \r
487**/\r
ead42efc 488EFI_STATUS\r
489EFIAPI\r
490PciIoIoRead (\r
491 IN EFI_PCI_IO_PROTOCOL *This,\r
492 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
493 IN UINT8 BarIndex,\r
494 IN UINT64 Offset,\r
495 IN UINTN Count,\r
496 IN OUT VOID *Buffer\r
497 )\r
ead42efc 498{\r
499 EFI_STATUS Status;\r
500 PCI_IO_DEVICE *PciIoDevice;\r
501\r
502 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);\r
503\r
504 if (Width < 0 || Width >= EfiPciIoWidthMaximum) {\r
505 return EFI_INVALID_PARAMETER;\r
506 }\r
507\r
9a2d4fe9 508 if (Buffer == NULL) {\r
509 return EFI_INVALID_PARAMETER;\r
510 }\r
511\r
ead42efc 512 Status = PciIoVerifyBarAccess (PciIoDevice, BarIndex, PciBarTypeIo, Width, Count, &Offset);\r
513 if (EFI_ERROR (Status)) {\r
514 return EFI_UNSUPPORTED;\r
515 }\r
516\r
517 Status = PciIoDevice->PciRootBridgeIo->Io.Read (\r
518 PciIoDevice->PciRootBridgeIo,\r
519 (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,\r
520 Offset,\r
521 Count,\r
522 Buffer\r
523 );\r
524\r
525 if (EFI_ERROR (Status)) {\r
526 ReportErrorStatusCode (PciIoDevice, EFI_IO_BUS_PCI | EFI_IOB_EC_READ_ERROR);\r
527 }\r
528\r
529 return Status;\r
530}\r
531\r
57076f45 532/** \r
533 Enable a PCI driver to access PCI controller registers in the PCI memory or I/O space.\r
534 \r
535 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
536 @param Width Signifies the width of the memory or I/O operations.\r
537 @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r
538 base address for the memory or I/O operation to perform. \r
539 @param Offset The offset within the selected BAR to start the memory or I/O operation. \r
540 @param Count The number of memory or I/O operations to perform.\r
541 @param Buffer For read operations, the destination buffer to store the results. For write\r
542 operations, the source buffer to write data from. \r
543 \r
544 @retval EFI_SUCCESS The data was read from or written to the PCI controller.\r
545 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r
546 @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not\r
547 valid for the PCI BAR specified by BarIndex. \r
548 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
549 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
550 \r
551**/\r
ead42efc 552EFI_STATUS\r
553EFIAPI\r
554PciIoIoWrite (\r
555 IN EFI_PCI_IO_PROTOCOL *This,\r
556 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
557 IN UINT8 BarIndex,\r
558 IN UINT64 Offset,\r
559 IN UINTN Count,\r
560 IN OUT VOID *Buffer\r
561 )\r
ead42efc 562{\r
563 EFI_STATUS Status;\r
564 PCI_IO_DEVICE *PciIoDevice;\r
565\r
566 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);\r
567\r
568 if (Width < 0 || Width >= EfiPciIoWidthMaximum) {\r
569 return EFI_INVALID_PARAMETER;\r
570 }\r
571\r
9a2d4fe9 572 if (Buffer == NULL) {\r
573 return EFI_INVALID_PARAMETER;\r
574 }\r
575\r
ead42efc 576 Status = PciIoVerifyBarAccess (PciIoDevice, BarIndex, PciBarTypeIo, Width, Count, &Offset);\r
577 if (EFI_ERROR (Status)) {\r
578 return EFI_UNSUPPORTED;\r
579 }\r
580\r
581 Status = PciIoDevice->PciRootBridgeIo->Io.Write (\r
582 PciIoDevice->PciRootBridgeIo,\r
583 (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,\r
584 Offset,\r
585 Count,\r
586 Buffer\r
587 );\r
588\r
589 if (EFI_ERROR (Status)) {\r
590 ReportErrorStatusCode (PciIoDevice, EFI_IO_BUS_PCI | EFI_IOB_EC_WRITE_ERROR);\r
591 }\r
592\r
593 return Status;\r
594}\r
595\r
57076f45 596/** \r
597 Enable a PCI driver to access PCI controller registers in PCI configuration space.\r
598 \r
599 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. \r
600 @param Width Signifies the width of the memory operations.\r
601 @param Offset The offset within the PCI configuration space for the PCI controller.\r
602 @param Count The number of PCI configuration operations to perform.\r
603 @param Buffer For read operations, the destination buffer to store the results. For write\r
604 operations, the source buffer to write data from.\r
605 \r
606 \r
607 @retval EFI_SUCCESS The data was read from or written to the PCI controller.\r
608 @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not\r
609 valid for the PCI configuration header of the PCI controller.\r
610 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. \r
611 @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid. \r
612 \r
613**/\r
ead42efc 614EFI_STATUS\r
615EFIAPI\r
616PciIoConfigRead (\r
617 IN EFI_PCI_IO_PROTOCOL *This,\r
618 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
619 IN UINT32 Offset,\r
620 IN UINTN Count,\r
621 IN OUT VOID *Buffer\r
622 )\r
ead42efc 623{\r
624 EFI_STATUS Status;\r
625 PCI_IO_DEVICE *PciIoDevice;\r
626 UINT64 Address;\r
627\r
628 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);\r
629\r
630 Address = Offset;\r
631 Status = PciIoVerifyConfigAccess (PciIoDevice, Width, Count, &Address);\r
632 if (EFI_ERROR (Status)) {\r
633 return Status;\r
634 }\r
635\r
636 Status = PciIoDevice->PciRootBridgeIo->Pci.Read (\r
637 PciIoDevice->PciRootBridgeIo,\r
638 (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,\r
639 Address,\r
640 Count,\r
641 Buffer\r
642 );\r
643\r
644 if (EFI_ERROR (Status)) {\r
645 ReportErrorStatusCode (PciIoDevice, EFI_IO_BUS_PCI | EFI_IOB_EC_READ_ERROR);\r
646 }\r
647\r
648 return Status;\r
649}\r
650\r
57076f45 651/** \r
652 Enable a PCI driver to access PCI controller registers in PCI configuration space.\r
653 \r
654 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. \r
655 @param Width Signifies the width of the memory operations.\r
656 @param Offset The offset within the PCI configuration space for the PCI controller.\r
657 @param Count The number of PCI configuration operations to perform.\r
658 @param Buffer For read operations, the destination buffer to store the results. For write\r
659 operations, the source buffer to write data from.\r
660 \r
661 \r
662 @retval EFI_SUCCESS The data was read from or written to the PCI controller.\r
663 @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not\r
664 valid for the PCI configuration header of the PCI controller.\r
665 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. \r
666 @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid. \r
667 \r
668**/\r
ead42efc 669EFI_STATUS\r
670EFIAPI\r
671PciIoConfigWrite (\r
672 IN EFI_PCI_IO_PROTOCOL *This,\r
673 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
674 IN UINT32 Offset,\r
675 IN UINTN Count,\r
676 IN OUT VOID *Buffer\r
677 )\r
ead42efc 678{\r
679 EFI_STATUS Status;\r
680 PCI_IO_DEVICE *PciIoDevice;\r
681 UINT64 Address;\r
682\r
683 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);\r
684\r
685 Address = Offset;\r
686 Status = PciIoVerifyConfigAccess (PciIoDevice, Width, Count, &Address);\r
687 if (EFI_ERROR (Status)) {\r
688 return Status;\r
689 }\r
690\r
691 Status = PciIoDevice->PciRootBridgeIo->Pci.Write (\r
692 PciIoDevice->PciRootBridgeIo,\r
693 (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,\r
694 Address,\r
695 Count,\r
696 Buffer\r
697 );\r
698\r
699 if (EFI_ERROR (Status)) {\r
700 ReportErrorStatusCode (PciIoDevice, EFI_IO_BUS_PCI | EFI_IOB_EC_WRITE_ERROR);\r
701 }\r
702\r
703 return Status;\r
704}\r
705\r
57076f45 706/** \r
707 Enables a PCI driver to copy one region of PCI memory space to another region of PCI\r
708 memory space.\r
709 \r
710 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
711 @param Width Signifies the width of the memory operations.\r
712 @param DestBarIndex The BAR index in the standard PCI Configuration header to use as the\r
713 base address for the memory operation to perform. \r
714 @param DestOffset The destination offset within the BAR specified by DestBarIndex to\r
715 start the memory writes for the copy operation. \r
716 @param SrcBarIndex The BAR index in the standard PCI Configuration header to use as the\r
717 base address for the memory operation to perform. \r
718 @param SrcOffset The source offset within the BAR specified by SrcBarIndex to start\r
719 the memory reads for the copy operation. \r
720 @param Count The number of memory operations to perform. Bytes moved is Width\r
721 size * Count, starting at DestOffset and SrcOffset. \r
722 \r
723 @retval EFI_SUCCESS The data was copied from one memory region to another memory region.\r
724 @retval EFI_UNSUPPORTED DestBarIndex not valid for this PCI controller.\r
725 @retval EFI_UNSUPPORTED SrcBarIndex not valid for this PCI controller.\r
726 @retval EFI_UNSUPPORTED The address range specified by DestOffset, Width, and Count\r
727 is not valid for the PCI BAR specified by DestBarIndex. \r
728 @retval EFI_UNSUPPORTED The address range specified by SrcOffset, Width, and Count is\r
729 not valid for the PCI BAR specified by SrcBarIndex. \r
730 @retval EFI_INVALID_PARAMETER Width is invalid.\r
731 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
732 \r
733**/\r
ead42efc 734EFI_STATUS\r
735EFIAPI\r
736PciIoCopyMem (\r
737 IN EFI_PCI_IO_PROTOCOL *This,\r
738 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
739 IN UINT8 DestBarIndex,\r
740 IN UINT64 DestOffset,\r
741 IN UINT8 SrcBarIndex,\r
742 IN UINT64 SrcOffset,\r
743 IN UINTN Count\r
744 )\r
ead42efc 745{\r
746 EFI_STATUS Status;\r
747 PCI_IO_DEVICE *PciIoDevice;\r
748\r
749 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);\r
750\r
751 if (Width < 0 || Width >= EfiPciIoWidthMaximum) {\r
752 return EFI_INVALID_PARAMETER;\r
753 }\r
754\r
755 if (Width == EfiPciIoWidthFifoUint8 ||\r
756 Width == EfiPciIoWidthFifoUint16 ||\r
757 Width == EfiPciIoWidthFifoUint32 ||\r
758 Width == EfiPciIoWidthFifoUint64 ||\r
759 Width == EfiPciIoWidthFillUint8 ||\r
760 Width == EfiPciIoWidthFillUint16 ||\r
761 Width == EfiPciIoWidthFillUint32 ||\r
762 Width == EfiPciIoWidthFillUint64) {\r
763 return EFI_INVALID_PARAMETER;\r
764 }\r
765\r
766 Status = PciIoVerifyBarAccess (PciIoDevice, DestBarIndex, PciBarTypeMem, Width, Count, &DestOffset);\r
767 if (EFI_ERROR (Status)) {\r
768 return EFI_UNSUPPORTED;\r
769 }\r
770\r
771 Status = PciIoVerifyBarAccess (PciIoDevice, SrcBarIndex, PciBarTypeMem, Width, Count, &SrcOffset);\r
772 if (EFI_ERROR (Status)) {\r
773 return EFI_UNSUPPORTED;\r
774 }\r
775\r
776 Status = PciIoDevice->PciRootBridgeIo->CopyMem (\r
777 PciIoDevice->PciRootBridgeIo,\r
778 (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,\r
779 DestOffset,\r
780 SrcOffset,\r
781 Count\r
782 );\r
783\r
784 if (EFI_ERROR (Status)) {\r
785 ReportErrorStatusCode (PciIoDevice, EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR);\r
786 }\r
787\r
788 return Status;\r
789}\r
790\r
57076f45 791/** \r
792 Provides the PCI controller-Cspecific addresses needed to access system memory.\r
793 \r
794 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
795 @param Operation Indicates if the bus master is going to read or write to system memory.\r
796 @param HostAddress The system memory address to map to the PCI controller.\r
797 @param NumberOfBytes On input the number of bytes to map. On output the number of bytes\r
798 that were mapped. \r
799 @param DeviceAddress The resulting map address for the bus master PCI controller to use to\r
800 access the hosts HostAddress. \r
801 @param Mapping A resulting value to pass to Unmap().\r
802 \r
803 @retval EFI_SUCCESS The range was mapped for the returned NumberOfBytes.\r
804 @retval EFI_UNSUPPORTED The HostAddress cannot be mapped as a common buffer. \r
805 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
806 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
807 @retval EFI_DEVICE_ERROR The system hardware could not map the requested address.\r
808 \r
809**/\r
ead42efc 810EFI_STATUS\r
811EFIAPI\r
812PciIoMap (\r
813 IN EFI_PCI_IO_PROTOCOL *This,\r
814 IN EFI_PCI_IO_PROTOCOL_OPERATION Operation,\r
815 IN VOID *HostAddress,\r
816 IN OUT UINTN *NumberOfBytes,\r
817 OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,\r
818 OUT VOID **Mapping\r
819 )\r
ead42efc 820{\r
821 EFI_STATUS Status;\r
822 PCI_IO_DEVICE *PciIoDevice;\r
823\r
824 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);\r
825\r
826 if (Operation < 0 || Operation >= EfiPciIoOperationMaximum) {\r
827 return EFI_INVALID_PARAMETER;\r
828 }\r
829\r
830 if (HostAddress == NULL || NumberOfBytes == NULL || DeviceAddress == NULL || Mapping == NULL) {\r
831 return EFI_INVALID_PARAMETER;\r
832 }\r
833\r
834 if (PciIoDevice->Attributes & EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE) {\r
835 Operation = (EFI_PCI_IO_PROTOCOL_OPERATION) (Operation + EfiPciOperationBusMasterRead64);\r
836 }\r
837\r
838 Status = PciIoDevice->PciRootBridgeIo->Map (\r
839 PciIoDevice->PciRootBridgeIo,\r
840 (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION) Operation,\r
841 HostAddress,\r
842 NumberOfBytes,\r
843 DeviceAddress,\r
844 Mapping\r
845 );\r
846\r
847 if (EFI_ERROR (Status)) {\r
848 ReportErrorStatusCode (PciIoDevice, EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR);\r
849 }\r
850\r
851 return Status;\r
852}\r
853\r
57076f45 854/** \r
855 Completes the Map() operation and releases any corresponding resources.\r
856 \r
857 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. \r
858 @param Mapping The mapping value returned from Map().\r
859 \r
860 @retval EFI_SUCCESS The range was unmapped.\r
861 @retval EFI_DEVICE_ERROR The data was not committed to the target system memory.\r
862 \r
863**/\r
ead42efc 864EFI_STATUS\r
865EFIAPI\r
866PciIoUnmap (\r
867 IN EFI_PCI_IO_PROTOCOL *This,\r
868 IN VOID *Mapping\r
869 )\r
ead42efc 870{\r
871 EFI_STATUS Status;\r
872 PCI_IO_DEVICE *PciIoDevice;\r
873\r
874 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);\r
875\r
876 Status = PciIoDevice->PciRootBridgeIo->Unmap (\r
877 PciIoDevice->PciRootBridgeIo,\r
878 Mapping\r
879 );\r
880\r
881 if (EFI_ERROR (Status)) {\r
882 ReportErrorStatusCode (PciIoDevice, EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR);\r
883 }\r
884\r
885 return Status;\r
886}\r
887\r
57076f45 888/** \r
889 Allocates pages that are suitable for an EfiPciIoOperationBusMasterCommonBuffer\r
890 mapping. \r
891 \r
892 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
893 @param Type This parameter is not used and must be ignored.\r
894 @param MemoryType The type of memory to allocate, EfiBootServicesData or\r
895 EfiRuntimeServicesData. \r
896 @param Pages The number of pages to allocate. \r
897 @param HostAddress A pointer to store the base system memory address of the\r
898 allocated range. \r
899 @param Attributes The requested bit mask of attributes for the allocated range.\r
900 \r
901 @retval EFI_SUCCESS The requested memory pages were allocated.\r
902 @retval EFI_UNSUPPORTED Attributes is unsupported. The only legal attribute bits are\r
903 MEMORY_WRITE_COMBINE and MEMORY_CACHED. \r
904 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
905 @retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated. \r
906 \r
907**/\r
ead42efc 908EFI_STATUS\r
909EFIAPI\r
910PciIoAllocateBuffer (\r
911 IN EFI_PCI_IO_PROTOCOL *This,\r
912 IN EFI_ALLOCATE_TYPE Type,\r
913 IN EFI_MEMORY_TYPE MemoryType,\r
914 IN UINTN Pages,\r
915 OUT VOID **HostAddress,\r
916 IN UINT64 Attributes\r
917 )\r
ead42efc 918{\r
919 EFI_STATUS Status;\r
920 PCI_IO_DEVICE *PciIoDevice;\r
921\r
922 if (Attributes &\r
923 (~(EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE | EFI_PCI_ATTRIBUTE_MEMORY_CACHED))) {\r
924 return EFI_UNSUPPORTED;\r
925 }\r
926\r
927 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);\r
928\r
929 if (PciIoDevice->Attributes & EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE) {\r
930 Attributes |= EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE;\r
931 }\r
932\r
933 Status = PciIoDevice->PciRootBridgeIo->AllocateBuffer (\r
934 PciIoDevice->PciRootBridgeIo,\r
935 Type,\r
936 MemoryType,\r
937 Pages,\r
938 HostAddress,\r
939 Attributes\r
940 );\r
941\r
942 if (EFI_ERROR (Status)) {\r
943 ReportErrorStatusCode (PciIoDevice, EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR);\r
944 }\r
945\r
946 return Status;\r
947}\r
948\r
57076f45 949/** \r
950 Frees memory that was allocated with AllocateBuffer().\r
951 \r
952 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. \r
953 @param Pages The number of pages to free. \r
954 @param HostAddress The base system memory address of the allocated range. \r
955 \r
956 @retval EFI_SUCCESS The requested memory pages were freed.\r
957 @retval EFI_INVALID_PARAMETER The memory range specified by HostAddress and Pages\r
958 was not allocated with AllocateBuffer().\r
959 \r
960**/\r
ead42efc 961EFI_STATUS\r
962EFIAPI\r
963PciIoFreeBuffer (\r
964 IN EFI_PCI_IO_PROTOCOL *This,\r
965 IN UINTN Pages,\r
966 IN VOID *HostAddress\r
967 )\r
ead42efc 968{\r
969 EFI_STATUS Status;\r
970 PCI_IO_DEVICE *PciIoDevice;\r
971\r
972 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);\r
973\r
974 Status = PciIoDevice->PciRootBridgeIo->FreeBuffer (\r
975 PciIoDevice->PciRootBridgeIo,\r
976 Pages,\r
977 HostAddress\r
978 );\r
979\r
980 if (EFI_ERROR (Status)) {\r
981 ReportErrorStatusCode (PciIoDevice, EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR);\r
982 }\r
983\r
984 return Status;\r
985}\r
986\r
57076f45 987/** \r
988 Flushes all PCI posted write transactions from a PCI host bridge to system memory.\r
989 \r
990 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. \r
991 \r
992 @retval EFI_SUCCESS The PCI posted write transactions were flushed from the PCI host\r
993 bridge to system memory. \r
994 @retval EFI_DEVICE_ERROR The PCI posted write transactions were not flushed from the PCI\r
995 host bridge due to a hardware error. \r
996 \r
997**/\r
ead42efc 998EFI_STATUS\r
999EFIAPI\r
1000PciIoFlush (\r
1001 IN EFI_PCI_IO_PROTOCOL *This\r
1002 )\r
ead42efc 1003{\r
1004 EFI_STATUS Status;\r
1005 PCI_IO_DEVICE *PciIoDevice;\r
1006\r
1007 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);\r
1008\r
1009 Status = PciIoDevice->PciRootBridgeIo->Flush (\r
1010 PciIoDevice->PciRootBridgeIo\r
1011 );\r
1012 if (EFI_ERROR (Status)) {\r
1013 ReportErrorStatusCode (PciIoDevice, EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR);\r
1014 }\r
1015\r
1016 return Status;\r
1017}\r
1018\r
57076f45 1019/** \r
1020 Retrieves this PCI controller's current PCI bus number, device number, and function number.\r
1021 \r
1022 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. \r
1023 @param SegmentNumber The PCI controller's current PCI segment number.\r
1024 @param BusNumber The PCI controller's current PCI bus number.\r
1025 @param DeviceNumber The PCI controller's current PCI device number.\r
1026 @param FunctionNumber The PCI controller's current PCI function number.\r
1027 \r
1028 @retval EFI_SUCCESS The PCI controller location was returned. \r
1029 @retval EFI_INVALID_PARAMETER One or more parameters are invalid. \r
1030 \r
1031**/\r
ead42efc 1032EFI_STATUS\r
1033EFIAPI\r
1034PciIoGetLocation (\r
1035 IN EFI_PCI_IO_PROTOCOL *This,\r
1036 OUT UINTN *Segment,\r
1037 OUT UINTN *Bus,\r
1038 OUT UINTN *Device,\r
1039 OUT UINTN *Function\r
1040 )\r
ead42efc 1041{\r
1042 PCI_IO_DEVICE *PciIoDevice;\r
1043\r
1044 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);\r
1045\r
1046 if (Segment == NULL || Bus == NULL || Device == NULL || Function == NULL) {\r
1047 return EFI_INVALID_PARAMETER;\r
1048 }\r
1049\r
1050 *Segment = PciIoDevice->PciRootBridgeIo->SegmentNumber;\r
1051 *Bus = PciIoDevice->BusNumber;\r
1052 *Device = PciIoDevice->DeviceNumber;\r
1053 *Function = PciIoDevice->FunctionNumber;\r
1054\r
1055 return EFI_SUCCESS;\r
1056}\r
1057\r
57076f45 1058/**\r
1059 Check BAR type for PCI resource.\r
1060 \r
1061 @param PciIoDevice PCI device instance\r
1062 @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r
1063 base address for the memory or I/O operation to perform. \r
1064 @param BarType Memory or I/O\r
1065 \r
1066 @return whether Pci device's bar type is same with input BarType.\r
1067**/\r
ead42efc 1068BOOLEAN\r
1069CheckBarType (\r
1070 IN PCI_IO_DEVICE *PciIoDevice,\r
1071 UINT8 BarIndex,\r
1072 PCI_BAR_TYPE BarType\r
1073 )\r
ead42efc 1074{\r
1075 switch (BarType) {\r
1076\r
1077 case PciBarTypeMem:\r
1078\r
1079 if (PciIoDevice->PciBar[BarIndex].BarType != PciBarTypeMem32 &&\r
1080 PciIoDevice->PciBar[BarIndex].BarType != PciBarTypePMem32 &&\r
1081 PciIoDevice->PciBar[BarIndex].BarType != PciBarTypePMem64 &&\r
1082 PciIoDevice->PciBar[BarIndex].BarType != PciBarTypeMem64 ) {\r
1083 return FALSE;\r
1084 }\r
1085\r
1086 return TRUE;\r
1087\r
1088 case PciBarTypeIo:\r
1089 if (PciIoDevice->PciBar[BarIndex].BarType != PciBarTypeIo32 &&\r
1090 PciIoDevice->PciBar[BarIndex].BarType != PciBarTypeIo16){\r
1091 return FALSE;\r
1092 }\r
1093\r
1094 return TRUE;\r
1095\r
1096 default:\r
1097 break;\r
1098 }\r
1099\r
1100 return FALSE;\r
1101}\r
1102\r
57076f45 1103/**\r
1104 Set/Disable new attributes to a Root Bridge\r
1105 \r
1106 @param PciIoDevice Pci device instance\r
1107 @param Attributes New attribute want to be set\r
1108 @param Operation Set or Disable\r
1109 \r
1110 @retval EFI_UNSUPPORTED If root bridge does not support change attribute\r
1111 @retval EFI_SUCCESS Success operation.\r
1112**/\r
ead42efc 1113EFI_STATUS\r
1114ModifyRootBridgeAttributes (\r
1115 IN PCI_IO_DEVICE *PciIoDevice,\r
1116 IN UINT64 Attributes,\r
1117 IN EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION Operation\r
1118 )\r
ead42efc 1119{\r
1120 UINT64 PciRootBridgeSupports;\r
1121 UINT64 PciRootBridgeAttributes;\r
1122 UINT64 NewPciRootBridgeAttributes;\r
1123 EFI_STATUS Status;\r
1124\r
1125 //\r
1126 // Get the current attributes of this PCI device's PCI Root Bridge\r
1127 //\r
1128 Status = PciIoDevice->PciRootBridgeIo->GetAttributes (\r
1129 PciIoDevice->PciRootBridgeIo,\r
1130 &PciRootBridgeSupports,\r
1131 &PciRootBridgeAttributes\r
1132 );\r
1133 if (EFI_ERROR (Status)) {\r
1134 return EFI_UNSUPPORTED;\r
1135 }\r
1136 \r
1137 //\r
1138 // Record the new attribute of the Root Bridge\r
1139 //\r
1140 if (Operation == EfiPciIoAttributeOperationEnable) {\r
1141 NewPciRootBridgeAttributes = PciRootBridgeAttributes | Attributes;\r
1142 } else {\r
1143 NewPciRootBridgeAttributes = PciRootBridgeAttributes & (~Attributes);\r
1144 }\r
1145 \r
1146 //\r
1147 // Call the PCI Root Bridge to attempt to modify the attributes\r
1148 //\r
1149 if (NewPciRootBridgeAttributes ^ PciRootBridgeAttributes) {\r
1150\r
1151 Status = PciIoDevice->PciRootBridgeIo->SetAttributes (\r
1152 PciIoDevice->PciRootBridgeIo,\r
1153 NewPciRootBridgeAttributes,\r
1154 NULL,\r
1155 NULL\r
1156 );\r
1157 if (EFI_ERROR (Status)) {\r
1158 //\r
1159 // The PCI Root Bridge could not modify the attributes, so return the error.\r
1160 //\r
1161 return EFI_UNSUPPORTED;\r
1162 }\r
1163 }\r
1164 \r
1165 //\r
1166 // Also update the attributes for this Root Bridge structure\r
1167 //\r
1168 PciIoDevice->Attributes = NewPciRootBridgeAttributes;\r
1169 return EFI_SUCCESS;\r
1170\r
1171}\r
1172\r
57076f45 1173/**\r
1174 Check whether this device can be enable/disable to snoop\r
1175 \r
1176 @param PciIoDevice Pci device instance\r
1177 @param Operation Enable/Disable\r
1178 \r
1179 @retval EFI_UNSUPPORTED Pci device is not GFX device or not support snoop\r
1180 @retval EFI_SUCCESS Snoop can be supported.\r
1181**/\r
ead42efc 1182EFI_STATUS\r
1183SupportPaletteSnoopAttributes (\r
1184 IN PCI_IO_DEVICE *PciIoDevice,\r
1185 IN EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION Operation\r
1186 )\r
ead42efc 1187{\r
1188 PCI_IO_DEVICE *Temp;\r
1189 UINT16 VGACommand;\r
1190\r
1191 //\r
1192 // Snoop attribute can be only modified by GFX\r
1193 //\r
1194 if (!IS_PCI_GFX (&PciIoDevice->Pci)) {\r
1195 return EFI_UNSUPPORTED;\r
1196 }\r
1197\r
1198 //\r
1199 // Get the boot VGA on the same segement\r
1200 //\r
1201 Temp = ActiveVGADeviceOnTheSameSegment (PciIoDevice);\r
1202\r
1203 if (!Temp) {\r
1204 //\r
1205 // If there is no VGA device on the segement, set\r
1206 // this graphics card to decode the palette range\r
1207 //\r
1208 return EFI_SUCCESS;\r
1209 }\r
1210 \r
1211 //\r
1212 // Check these two agents are on the same path\r
1213 //\r
1214 if (!PciDevicesOnTheSamePath (Temp, PciIoDevice)) {\r
1215 //\r
1216 // they are not on the same path, so snoop can be enabled or disabled\r
1217 //\r
1218 return EFI_SUCCESS;\r
1219 }\r
1220 //\r
1221 // Check if they are on the same bus\r
1222 //\r
1223 if (Temp->Parent == PciIoDevice->Parent) {\r
1224\r
1225 PciReadCommandRegister (Temp, &VGACommand);\r
1226\r
1227 //\r
1228 // If they are on the same bus, either one can\r
1229 // be set to snoop, the other set to decode\r
1230 //\r
1231 if (VGACommand & EFI_PCI_COMMAND_VGA_PALETTE_SNOOP) {\r
1232 //\r
1233 // VGA has set to snoop, so GFX can be only set to disable snoop\r
1234 //\r
1235 if (Operation == EfiPciIoAttributeOperationEnable) {\r
1236 return EFI_UNSUPPORTED;\r
1237 }\r
1238 } else {\r
1239 //\r
1240 // VGA has disabled to snoop, so GFX can be only enabled\r
1241 //\r
1242 if (Operation == EfiPciIoAttributeOperationDisable) {\r
1243 return EFI_UNSUPPORTED;\r
1244 }\r
1245 }\r
1246\r
1247 return EFI_SUCCESS;\r
1248 }\r
1249 \r
1250 //\r
1251 // If they are on the same path but on the different bus\r
1252 // The first agent is set to snoop, the second one set to\r
1253 // decode\r
1254 //\r
1255 \r
1256 if (Temp->BusNumber < PciIoDevice->BusNumber) {\r
1257 //\r
1258 // GFX should be set to decode\r
1259 //\r
1260 if (Operation == EfiPciIoAttributeOperationDisable) {\r
1261 PciEnableCommandRegister (Temp, EFI_PCI_COMMAND_VGA_PALETTE_SNOOP);\r
1262 Temp->Attributes |= EFI_PCI_COMMAND_VGA_PALETTE_SNOOP;\r
1263 } else {\r
1264 return EFI_UNSUPPORTED;\r
1265 }\r
1266\r
1267 } else {\r
1268 //\r
1269 // GFX should be set to snoop\r
1270 //\r
1271 if (Operation == EfiPciIoAttributeOperationEnable) {\r
1272 PciDisableCommandRegister (Temp, EFI_PCI_COMMAND_VGA_PALETTE_SNOOP);\r
1273 Temp->Attributes &= (~EFI_PCI_COMMAND_VGA_PALETTE_SNOOP);\r
1274 } else {\r
1275 return EFI_UNSUPPORTED;\r
1276 }\r
1277\r
1278 }\r
1279\r
1280 return EFI_SUCCESS;\r
1281}\r
1282\r
57076f45 1283/** \r
1284 Performs an operation on the attributes that this PCI controller supports. The operations include\r
1285 getting the set of supported attributes, retrieving the current attributes, setting the current \r
1286 attributes, enabling attributes, and disabling attributes. \r
1287 \r
1288 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. \r
1289 @param Operation The operation to perform on the attributes for this PCI controller.\r
1290 @param Attributes The mask of attributes that are used for Set, Enable, and Disable\r
1291 operations. \r
1292 @param Result A pointer to the result mask of attributes that are returned for the Get\r
1293 and Supported operations. \r
1294 \r
1295 @retval EFI_SUCCESS The operation on the PCI controller's attributes was completed.\r
1296 @retval EFI_INVALID_PARAMETER One or more parameters are invalid. \r
1297 @retval EFI_UNSUPPORTED one or more of the bits set in \r
1298 Attributes are not supported by this PCI controller or one of\r
1299 its parent bridges when Operation is Set, Enable or Disable.\r
1300 \r
1301**/\r
ead42efc 1302EFI_STATUS\r
1303EFIAPI\r
1304PciIoAttributes (\r
1305 IN EFI_PCI_IO_PROTOCOL * This,\r
1306 IN EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION Operation,\r
1307 IN UINT64 Attributes,\r
1308 OUT UINT64 *Result OPTIONAL\r
1309 )\r
ead42efc 1310{\r
1311 EFI_STATUS Status;\r
1312\r
1313 PCI_IO_DEVICE *PciIoDevice;\r
1314 PCI_IO_DEVICE *UpStreamBridge;\r
1315 PCI_IO_DEVICE *Temp;\r
1316\r
1317 UINT64 Supports;\r
1318 UINT64 UpStreamAttributes;\r
1319 UINT16 BridgeControl;\r
1320 UINT16 Command;\r
1321\r
1322 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);\r
1323\r
1324 switch (Operation) {\r
1325 case EfiPciIoAttributeOperationGet:\r
1326 if (Result == NULL) {\r
1327 return EFI_INVALID_PARAMETER;\r
1328 }\r
1329\r
1330 *Result = PciIoDevice->Attributes;\r
1331 return EFI_SUCCESS;\r
1332\r
1333 case EfiPciIoAttributeOperationSupported:\r
1334 if (Result == NULL) {\r
1335 return EFI_INVALID_PARAMETER;\r
1336 }\r
1337\r
1338 *Result = PciIoDevice->Supports;\r
1339 return EFI_SUCCESS;\r
1340\r
1341 case EfiPciIoAttributeOperationSet:\r
1342 Status = PciIoDevice->PciIo.Attributes (\r
1343 &(PciIoDevice->PciIo),\r
1344 EfiPciIoAttributeOperationEnable,\r
1345 Attributes,\r
1346 NULL\r
1347 );\r
1348 if (EFI_ERROR (Status)) {\r
1349 return EFI_UNSUPPORTED;\r
1350 }\r
1351\r
1352 Status = PciIoDevice->PciIo.Attributes (\r
1353 &(PciIoDevice->PciIo),\r
1354 EfiPciIoAttributeOperationDisable,\r
1355 (~Attributes) & (PciIoDevice->Supports),\r
1356 NULL\r
1357 );\r
1358 if (EFI_ERROR (Status)) {\r
1359 return EFI_UNSUPPORTED;\r
1360 }\r
1361\r
1362 return EFI_SUCCESS;\r
1363\r
1364 case EfiPciIoAttributeOperationEnable:\r
1365 case EfiPciIoAttributeOperationDisable:\r
1366 break;\r
1367\r
1368 default:\r
1369 return EFI_INVALID_PARAMETER;\r
1370 }\r
1371 //\r
1372 // Just a trick for ENABLE attribute\r
96f6af14
LG		 1373 // EFI_PCI_DEVICE_ENABLE is not defined in UEFI spec, which is the internal usage.\r
1374 // So, this logic doesn't confrom to UEFI spec, which should be removed.\r
cb33842e 1375 // But this trick logic is still kept for some binary drivers that depend on it.\r
ead42efc 1376 //\r
cb33842e
LG		 1377 if ((Attributes & EFI_PCI_DEVICE_ENABLE) == EFI_PCI_DEVICE_ENABLE) {\r
1378 Attributes &= (PciIoDevice->Supports);\r
1379\r
1380 //\r
1381 // Raise the EFI_P_PC_ENABLE Status code\r
1382 //\r
1383 REPORT_STATUS_CODE_WITH_DEVICE_PATH (\r
1384 EFI_PROGRESS_CODE,\r
1385 EFI_IO_BUS_PCI | EFI_P_PC_ENABLE,\r
1386 PciIoDevice->DevicePath\r
1387 );\r
1388 }\r
ead42efc 1389\r
1390 //\r
1391 // If no attributes can be supported, then return.\r
1392 // Otherwise, set the attributes that it can support.\r
1393 //\r
1394 Supports = (PciIoDevice->Supports) & Attributes;\r
1395 if (Supports != Attributes) {\r
1396 return EFI_UNSUPPORTED;\r
1397 }\r
1398 \r
1399 //\r
1400 // For Root Bridge, just call RootBridgeIo to set attributes;\r
1401 //\r
1402 if (!PciIoDevice->Parent) {\r
1403 Status = ModifyRootBridgeAttributes (PciIoDevice, Attributes, Operation);\r
1404 return Status;\r
1405 }\r
1406\r
1407 Command = 0;\r
1408 BridgeControl = 0;\r
1409\r
1410 //\r
1411 // Check VGA and VGA16, they can not be set at the same time\r
1412 //\r
1413 if (((Attributes & EFI_PCI_IO_ATTRIBUTE_VGA_IO) &&\r
1414 (Attributes & EFI_PCI_IO_ATTRIBUTE_VGA_IO_16)) ||\r
1415 ((Attributes & EFI_PCI_IO_ATTRIBUTE_VGA_IO) &&\r
1416 (Attributes & EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16)) ||\r
1417 ((Attributes & EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO) &&\r
1418 (Attributes & EFI_PCI_IO_ATTRIBUTE_VGA_IO_16)) ||\r
1419 ((Attributes & EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO) &&\r
1420 (Attributes & EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16)) ) {\r
1421 return EFI_UNSUPPORTED;\r
1422 }\r
1423\r
1424 //\r
1425 // For PPB & P2C, set relevant attribute bits\r
1426 //\r
1427 if (IS_PCI_BRIDGE (&PciIoDevice->Pci) || IS_CARDBUS_BRIDGE (&PciIoDevice->Pci)) {\r
1428\r
1429 if (Attributes & (EFI_PCI_IO_ATTRIBUTE_VGA_IO | EFI_PCI_IO_ATTRIBUTE_VGA_IO_16)) {\r
1430 BridgeControl |= EFI_PCI_BRIDGE_CONTROL_VGA;\r
1431 }\r
1432\r
1433 if (Attributes & EFI_PCI_IO_ATTRIBUTE_ISA_IO) {\r
1434 BridgeControl |= EFI_PCI_BRIDGE_CONTROL_ISA;\r
1435 }\r
1436\r
1437 if (Attributes & (EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO | EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16)) {\r
1438 Command |= EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO;\r
1439 }\r
1440\r
1441 if (Attributes & (EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16 | EFI_PCI_IO_ATTRIBUTE_VGA_IO_16)) {\r
1442 BridgeControl |= EFI_PCI_BRIDGE_CONTROL_VGA_16;\r
1443 }\r
1444\r
1445 } else {\r
1446 //\r
1447 // Do with the attributes on VGA\r
1448 // Only for VGA's legacy resource, we just can enable once.\r
1449 //\r
1450 if (Attributes &\r
1451 (EFI_PCI_IO_ATTRIBUTE_VGA_IO |\r
1452 EFI_PCI_IO_ATTRIBUTE_VGA_IO_16 |\r
1453 EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY)) {\r
1454 //\r
1455 // Check if a VGA has been enabled before enabling a new one\r
1456 //\r
1457 if (Operation == EfiPciIoAttributeOperationEnable) {\r
1458 //\r
1459 // Check if there have been an active VGA device on the same segment\r
1460 //\r
1461 Temp = ActiveVGADeviceOnTheSameSegment (PciIoDevice);\r
1462 if (Temp && Temp != PciIoDevice) {\r
1463 //\r
1464 // An active VGA has been detected, so can not enable another\r
1465 //\r
1466 return EFI_UNSUPPORTED;\r
1467 }\r
1468 }\r
1469 }\r
1470 \r
1471 //\r
1472 // Do with the attributes on GFX\r
1473 //\r
1474 if (Attributes & (EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO | EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16)) {\r
1475\r
1476 if (Operation == EfiPciIoAttributeOperationEnable) {\r
1477 //\r
1478 // Check if snoop can be enabled in current configuration\r
1479 //\r
1480 Status = SupportPaletteSnoopAttributes (PciIoDevice, Operation);\r
1481\r
1482 if (EFI_ERROR (Status)) {\r
1483 \r
1484 //\r
1485 // Enable operation is forbidden, so mask the bit in attributes\r
1486 // so as to keep consistent with the actual Status\r
1487 //\r
1488 // Attributes &= (~EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO);\r
1489 //\r
1490 //\r
1491 //\r
1492 return EFI_UNSUPPORTED;\r
1493\r
1494 }\r
1495 }\r
1496\r
1497 //\r
1498 // It can be supported, so get ready to set the bit\r
1499 //\r
1500 Command |= EFI_PCI_COMMAND_VGA_PALETTE_SNOOP;\r
1501 }\r
1502 }\r
1503\r
1504 if (Attributes & EFI_PCI_IO_ATTRIBUTE_IO) {\r
1505 Command |= EFI_PCI_COMMAND_IO_SPACE;\r
1506 }\r
1507\r
1508 if (Attributes & EFI_PCI_IO_ATTRIBUTE_MEMORY) {\r
1509 Command |= EFI_PCI_COMMAND_MEMORY_SPACE;\r
1510 }\r
1511\r
1512 if (Attributes & EFI_PCI_IO_ATTRIBUTE_BUS_MASTER) {\r
1513 Command |= EFI_PCI_COMMAND_BUS_MASTER;\r
1514 }\r
1515 //\r
1516 // The upstream bridge should be also set to revelant attribute\r
1517 // expect for IO, Mem and BusMaster\r
1518 //\r
1519 UpStreamAttributes = Attributes & \r
1520 (~(EFI_PCI_IO_ATTRIBUTE_IO |\r
1521 EFI_PCI_IO_ATTRIBUTE_MEMORY |\r
1522 EFI_PCI_IO_ATTRIBUTE_BUS_MASTER\r
1523 )\r
1524 );\r
1525 UpStreamBridge = PciIoDevice->Parent;\r
1526\r
1527 if (Operation == EfiPciIoAttributeOperationEnable) {\r
1528 //\r
1529 // Enable relevant attributes to command register and bridge control register\r
1530 //\r
1531 Status = PciEnableCommandRegister (PciIoDevice, Command);\r
1532 if (BridgeControl) {\r
1533 Status = PciEnableBridgeControlRegister (PciIoDevice, BridgeControl);\r
1534 }\r
1535\r
1536 PciIoDevice->Attributes |= Attributes;\r
1537\r
1538 //\r
1539 // Enable attributes of the upstream bridge\r
1540 //\r
1541 Status = UpStreamBridge->PciIo.Attributes (\r
1542 &(UpStreamBridge->PciIo),\r
1543 EfiPciIoAttributeOperationEnable,\r
1544 UpStreamAttributes,\r
1545 NULL\r
1546 );\r
1547 } else {\r
1548 \r
1549 //\r
1550 // Disable relevant attributes to command register and bridge control register\r
1551 //\r
1552 Status = PciDisableCommandRegister (PciIoDevice, Command);\r
1553 if (BridgeControl) {\r
1554 Status = PciDisableBridgeControlRegister (PciIoDevice, BridgeControl);\r
1555 }\r
1556\r
1557 PciIoDevice->Attributes &= (~Attributes);\r
1558 Status = EFI_SUCCESS;\r
1559\r
1560 }\r
1561\r
1562 if (EFI_ERROR (Status)) {\r
1563 ReportErrorStatusCode (PciIoDevice, EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR);\r
1564 }\r
1565\r
1566 return Status;\r
1567}\r
1568\r
57076f45 1569/** \r
1570 Gets the attributes that this PCI controller supports setting on a BAR using\r
1571 SetBarAttributes(), and retrieves the list of resource descriptors for a BAR.\r
1572 \r
1573 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. \r
1574 @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r
1575 base address for resource range. The legal range for this field is 0..5.\r
1576 @param Supports A pointer to the mask of attributes that this PCI controller supports\r
1577 setting for this BAR with SetBarAttributes(). \r
1578 @param Resources A pointer to the ACPI 2.0 resource descriptors that describe the current\r
1579 configuration of this BAR of the PCI controller. \r
1580 \r
1581 @retval EFI_SUCCESS If Supports is not NULL, then the attributes that the PCI \r
1582 controller supports are returned in Supports. If Resources \r
1583 is not NULL, then the ACPI 2.0 resource descriptors that the PCI\r
1584 controller is currently using are returned in Resources. \r
1585 @retval EFI_INVALID_PARAMETER Both Supports and Attributes are NULL.\r
1586 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r
1587 @retval EFI_OUT_OF_RESOURCES There are not enough resources available to allocate\r
1588 Resources. \r
1589 \r
1590**/\r
ead42efc 1591EFI_STATUS\r
1592EFIAPI\r
1593PciIoGetBarAttributes (\r
1594 IN EFI_PCI_IO_PROTOCOL * This,\r
1595 IN UINT8 BarIndex,\r
1596 OUT UINT64 *Supports, OPTIONAL\r
1597 OUT VOID **Resources OPTIONAL\r
1598 )\r
ead42efc 1599{\r
1600\r
1601 UINT8 *Configuration;\r
1602 UINT8 NumConfig;\r
1603 PCI_IO_DEVICE *PciIoDevice;\r
1604 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Ptr;\r
1605 EFI_ACPI_END_TAG_DESCRIPTOR *PtrEnd;\r
1606\r
1607 NumConfig = 0;\r
1608\r
1609 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);\r
1610\r
1611 if (Supports == NULL && Resources == NULL) {\r
1612 return EFI_INVALID_PARAMETER;\r
1613 }\r
1614\r
1615 if (BarIndex >= PCI_MAX_BAR) {\r
1616 return EFI_UNSUPPORTED;\r
1617 }\r
1618\r
1619 //\r
1620 // This driver does not support modifications to the WRITE_COMBINE or\r
1621 // CACHED attributes for BAR ranges.\r
1622 //\r
1623 if (Supports != NULL) {\r
1624 *Supports = PciIoDevice->Supports & EFI_PCI_IO_ATTRIBUTE_MEMORY_CACHED & EFI_PCI_IO_ATTRIBUTE_MEMORY_WRITE_COMBINE;\r
1625 }\r
1626\r
1627 if (Resources != NULL) {\r
1628\r
1629 if (PciIoDevice->PciBar[BarIndex].BarType != PciBarTypeUnknown) {\r
1630 NumConfig = 1;\r
1631 }\r
1632\r
1633 Configuration = AllocatePool (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) * NumConfig + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR));\r
1634 if (Configuration == NULL) {\r
1635 return EFI_OUT_OF_RESOURCES;\r
1636 }\r
1637\r
1638 ZeroMem (\r
1639 Configuration,\r
1640 sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) * NumConfig + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR)\r
1641 );\r
1642\r
1643 Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration;\r
1644\r
1645 if (NumConfig == 1) {\r
1646 Ptr->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;\r
1647 Ptr->Len = sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3;\r
1648\r
1649 Ptr->AddrRangeMin = PciIoDevice->PciBar[BarIndex].BaseAddress;\r
1650 Ptr->AddrLen = PciIoDevice->PciBar[BarIndex].Length;\r
1651 Ptr->AddrRangeMax = PciIoDevice->PciBar[BarIndex].Alignment;\r
1652\r
1653 switch (PciIoDevice->PciBar[BarIndex].BarType) {\r
1654 case PciBarTypeIo16:\r
1655 case PciBarTypeIo32:\r
1656 //\r
1657 // Io\r
1658 //\r
1659 Ptr->ResType = ACPI_ADDRESS_SPACE_TYPE_IO;\r
1660 break;\r
1661\r
1662 case PciBarTypeMem32:\r
1663 //\r
1664 // Mem\r
1665 //\r
1666 Ptr->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;\r
1667 //\r
1668 // 32 bit\r
1669 //\r
1670 Ptr->AddrSpaceGranularity = 32;\r
1671 break;\r
1672\r
1673 case PciBarTypePMem32:\r
1674 //\r
1675 // Mem\r
1676 //\r
1677 Ptr->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;\r
1678 //\r
1679 // prefechable\r
1680 //\r
1681 Ptr->SpecificFlag = 0x6;\r
1682 //\r
1683 // 32 bit\r
1684 //\r
1685 Ptr->AddrSpaceGranularity = 32;\r
1686 break;\r
1687\r
1688 case PciBarTypeMem64:\r
1689 //\r
1690 // Mem\r
1691 //\r
1692 Ptr->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;\r
1693 //\r
1694 // 64 bit\r
1695 //\r
1696 Ptr->AddrSpaceGranularity = 64;\r
1697 break;\r
1698\r
1699 case PciBarTypePMem64:\r
1700 //\r
1701 // Mem\r
1702 //\r
1703 Ptr->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;\r
1704 //\r
1705 // prefechable\r
1706 //\r
1707 Ptr->SpecificFlag = 0x6;\r
1708 //\r
1709 // 64 bit\r
1710 //\r
1711 Ptr->AddrSpaceGranularity = 64;\r
1712 break;\r
1713\r
1714 default:\r
1715 break;\r
1716 }\r
1717\r
1718 Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) ((UINT8 *) Ptr + sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR));\r
1719 }\r
1720 \r
1721 //\r
1722 // put the checksum\r
1723 //\r
1724 PtrEnd = (EFI_ACPI_END_TAG_DESCRIPTOR *) ((UINT8 *) Ptr);\r
1725 PtrEnd->Desc = ACPI_END_TAG_DESCRIPTOR;\r
1726 PtrEnd->Checksum = 0;\r
1727\r
1728 *Resources = Configuration;\r
1729 }\r
1730\r
1731 return EFI_SUCCESS;\r
1732}\r
1733\r
57076f45 1734/** \r
1735 Sets the attributes for a range of a BAR on a PCI controller.\r
1736 \r
1737 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. \r
1738 @param Attributes The mask of attributes to set for the resource range specified by\r
1739 BarIndex, Offset, and Length. \r
1740 @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r
1741 base address for resource range. The legal range for this field is 0..5.\r
1742 @param Offset A pointer to the BAR relative base address of the resource range to be\r
1743 modified by the attributes specified by Attributes. \r
1744 @param Length A pointer to the length of the resource range to be modified by the\r
1745 attributes specified by Attributes. \r
1746 \r
1747 @retval EFI_SUCCESS The set of attributes specified by Attributes for the resource \r
1748 range specified by BarIndex, Offset, and Length were \r
1749 set on the PCI controller, and the actual resource range is returned\r
1750 in Offset and Length. \r
1751 @retval EFI_INVALID_PARAMETER Offset or Length is NULL.\r
1752 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r
1753 @retval EFI_OUT_OF_RESOURCES There are not enough resources to set the attributes on the\r
1754 resource range specified by BarIndex, Offset, and \r
1755 Length. \r
1756 \r
1757**/\r
ead42efc 1758EFI_STATUS\r
1759EFIAPI\r
1760PciIoSetBarAttributes (\r
1761 IN EFI_PCI_IO_PROTOCOL *This,\r
1762 IN UINT64 Attributes,\r
1763 IN UINT8 BarIndex,\r
1764 IN OUT UINT64 *Offset,\r
1765 IN OUT UINT64 *Length\r
1766 )\r
ead42efc 1767{\r
1768 EFI_STATUS Status;\r
1769 PCI_IO_DEVICE *PciIoDevice;\r
1770 UINT64 NonRelativeOffset;\r
1771 UINT64 Supports;\r
1772\r
1773 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);\r
1774\r
1775 //\r
1776 // Make sure Offset and Length are not NULL\r
1777 //\r
1778 if (Offset == NULL || Length == NULL) {\r
1779 return EFI_INVALID_PARAMETER;\r
1780 }\r
1781\r
1782 if (PciIoDevice->PciBar[BarIndex].BarType == PciBarTypeUnknown) {\r
1783 return EFI_UNSUPPORTED;\r
1784 }\r
1785 //\r
1786 // This driver does not support setting the WRITE_COMBINE or the CACHED attributes.\r
1787 // If Attributes is not 0, then return EFI_UNSUPPORTED.\r
1788 //\r
1789 Supports = PciIoDevice->Supports & EFI_PCI_IO_ATTRIBUTE_MEMORY_CACHED & EFI_PCI_IO_ATTRIBUTE_MEMORY_WRITE_COMBINE;\r
1790\r
1791 if (Attributes != (Attributes & Supports)) {\r
1792 return EFI_UNSUPPORTED;\r
1793 }\r
1794 //\r
1795 // Attributes must be supported. Make sure the BAR range describd by BarIndex, Offset, and\r
1796 // Length are valid for this PCI device.\r
1797 //\r
1798 NonRelativeOffset = *Offset;\r
1799 Status = PciIoVerifyBarAccess (\r
1800 PciIoDevice,\r
1801 BarIndex,\r
1802 PciBarTypeMem,\r
1803 EfiPciIoWidthUint8,\r
1804 (UINT32) *Length,\r
1805 &NonRelativeOffset\r
1806 );\r
1807 if (EFI_ERROR (Status)) {\r
1808 return EFI_UNSUPPORTED;\r
1809 }\r
1810\r
1811 return EFI_SUCCESS;\r
1812}\r
1813\r
57076f45 1814/**\r
1815 Program parent bridge's attribute recurrently.\r
1816 \r
1817 @param PciIoDevice Child Pci device instance\r
1818 @param Operation The operation to perform on the attributes for this PCI controller.\r
1819 @param Attributes The mask of attributes that are used for Set, Enable, and Disable\r
1820 operations.\r
1821 \r
1822 @retval EFI_SUCCESS The operation on the PCI controller's attributes was completed.\r
1823 @retval EFI_INVALID_PARAMETER One or more parameters are invalid. \r
1824 @retval EFI_UNSUPPORTED one or more of the bits set in \r
1825 Attributes are not supported by this PCI controller or one of\r
1826 its parent bridges when Operation is Set, Enable or Disable.\r
1827 \r
1828**/\r
ead42efc 1829EFI_STATUS\r
1830UpStreamBridgesAttributes (\r
1831 IN PCI_IO_DEVICE *PciIoDevice,\r
1832 IN EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION Operation,\r
1833 IN UINT64 Attributes\r
1834 )\r
ead42efc 1835{\r
1836 PCI_IO_DEVICE *Parent;\r
1837 EFI_PCI_IO_PROTOCOL *PciIo;\r
1838\r
1839 Parent = PciIoDevice->Parent;\r
1840\r
1841 while (Parent && IS_PCI_BRIDGE (&Parent->Pci)) {\r
1842\r
1843 //\r
1844 // Get the PciIo Protocol\r
1845 //\r
1846 PciIo = &Parent->PciIo;\r
1847\r
1848 PciIo->Attributes (PciIo, Operation, Attributes, NULL);\r
1849\r
1850 Parent = Parent->Parent;\r
1851 }\r
1852\r
1853 return EFI_SUCCESS;\r
1854}\r
1855\r
57076f45 1856/**\r
1857 Test whether two Pci device has same parent bridge.\r
1858 \r
1859 @param PciDevice1 the frist pci device for testing\r
1860 @param PciDevice2 the second pci device for testing\r
1861 \r
1862 @return whether two Pci device has same parent bridge.\r
1863**/\r
ead42efc 1864BOOLEAN\r
1865PciDevicesOnTheSamePath (\r
1866 IN PCI_IO_DEVICE *PciDevice1,\r
1867 IN PCI_IO_DEVICE *PciDevice2\r
1868 )\r
ead42efc 1869{\r
1870 BOOLEAN Existed1;\r
1871 BOOLEAN Existed2;\r
1872\r
1873 if (PciDevice1->Parent == PciDevice2->Parent) {\r
1874 return TRUE;\r
1875 }\r
1876\r
1877 Existed1 = PciDeviceExisted (PciDevice1->Parent, PciDevice2);\r
1878 Existed2 = PciDeviceExisted (PciDevice2->Parent, PciDevice1);\r
1879\r
1880 return (BOOLEAN) (Existed1 || Existed2);\r
1881}\r
57076f45 1882\r
EFI Development Kit II mirror for PVE