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3db51098 | 1 | /**@file\r |
ead42efc | 2 | \r |
3 | Copyright (c) 2006, Intel Corporation \r | |
4 | All rights reserved. This program and the accompanying materials \r | |
5 | are licensed and made available under the terms and conditions of the BSD License \r | |
6 | which accompanies this distribution. The full text of the license may be found at \r | |
7 | http://opensource.org/licenses/bsd-license.php \r | |
8 | \r | |
9 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r | |
10 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r | |
11 | \r | |
3db51098 | 12 | **/\r |
ead42efc | 13 | \r |
ead42efc | 14 | \r |
15 | #ifndef _EFI_PCI_IO_PROTOCOL_H\r | |
16 | #define _EFI_PCI_IO_PROTOCOL_H\r | |
17 | \r | |
57076f45 | 18 | /**\r |
19 | Initializes a PCI I/O Instance\r | |
20 | \r | |
21 | @param PciIoDevice Pci device instance\r | |
22 | \r | |
23 | @retval EFI_SUCCESS Success operation\r | |
24 | **/\r | |
ead42efc | 25 | EFI_STATUS\r |
26 | InitializePciIoInstance (\r | |
27 | PCI_IO_DEVICE *PciIoDevice\r | |
28 | )\r | |
ead42efc | 29 | ;\r |
30 | \r | |
57076f45 | 31 | /**\r |
32 | Verifies access to a PCI Base Address Register (BAR)\r | |
33 | \r | |
34 | @param PciIoDevice Pci device instance\r | |
35 | @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r | |
36 | base address for the memory or I/O operation to perform. \r | |
37 | @param Type Operation type could be memory or I/O\r | |
38 | @param Width Signifies the width of the memory or I/O operations.\r | |
39 | @param Count The number of memory or I/O operations to perform.\r | |
40 | @param Offset The offset within the PCI configuration space for the PCI controller.\r | |
41 | \r | |
42 | @retval EFI_INVALID_PARAMETER Invalid Width/BarIndex or Bar type.\r | |
43 | @retval EFI_SUCCESS Success Operation.\r | |
44 | **/\r | |
ead42efc | 45 | EFI_STATUS\r |
46 | PciIoVerifyBarAccess (\r | |
47 | PCI_IO_DEVICE *PciIoDevice,\r | |
48 | UINT8 BarIndex,\r | |
49 | PCI_BAR_TYPE Type,\r | |
50 | IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r | |
51 | IN UINTN Count,\r | |
52 | UINT64 *Offset\r | |
53 | )\r | |
ead42efc | 54 | ;\r |
55 | \r | |
57076f45 | 56 | /**\r |
57 | Verifies access to a PCI Config Header\r | |
58 | \r | |
59 | @param PciIoDevice Pci device instance\r | |
60 | @param Width Signifies the width of the memory or I/O operations.\r | |
61 | @param Count The number of memory or I/O operations to perform.\r | |
62 | @param Offset The offset within the PCI configuration space for the PCI controller.\r | |
63 | \r | |
64 | @retval EFI_INVALID_PARAMETER Invalid Width\r | |
65 | @retval EFI_UNSUPPORTED Offset overflow\r | |
66 | @retval EFI_SUCCESS Success operation\r | |
67 | **/\r | |
ead42efc | 68 | EFI_STATUS\r |
69 | PciIoVerifyConfigAccess (\r | |
70 | PCI_IO_DEVICE *PciIoDevice,\r | |
71 | IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r | |
72 | IN UINTN Count,\r | |
73 | IN UINT64 *Offset\r | |
74 | )\r | |
ead42efc | 75 | ;\r |
76 | \r | |
57076f45 | 77 | /**\r |
78 | Reads from the I/O space of a PCI Root Bridge. Returns when either the polling exit criteria is\r | |
79 | satisfied or after a defined duration.\r | |
80 | \r | |
81 | @param This Pointer to protocol instance of EFI_PCI_IO_PROTOCOL\r | |
82 | @param Width Signifies the width of the memory or I/O operations.\r | |
83 | @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r | |
84 | base address for the memory or I/O operation to perform. \r | |
85 | @param Offset The offset within the PCI configuration space for the PCI controller.\r | |
86 | @param Mask Mask used for the polling criteria.\r | |
87 | @param Value The comparison value used for the polling exit criteria.\r | |
88 | @param Delay The number of 100 ns units to poll.\r | |
89 | @param Result Pointer to the last value read from the memory location.\r | |
90 | \r | |
91 | @retval EFI_SUCCESS The last data returned from the access matched the poll exit criteria.\r | |
92 | @retval EFI_TIMEOUT Delay expired before a match occurred.\r | |
93 | @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r | |
94 | @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r | |
95 | **/\r | |
ead42efc | 96 | EFI_STATUS\r |
97 | EFIAPI\r | |
98 | PciIoPollMem (\r | |
99 | IN EFI_PCI_IO_PROTOCOL *This,\r | |
100 | IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r | |
101 | IN UINT8 BarIndex,\r | |
102 | IN UINT64 Offset,\r | |
103 | IN UINT64 Mask,\r | |
104 | IN UINT64 Value,\r | |
105 | IN UINT64 Delay,\r | |
106 | OUT UINT64 *Result\r | |
107 | )\r | |
ead42efc | 108 | ;\r |
109 | \r | |
57076f45 | 110 | /** \r |
111 | Reads from the I/O space of a PCI Root Bridge. Returns when either the polling exit criteria is\r | |
112 | satisfied or after a defined duration.\r | |
113 | \r | |
114 | @param This A pointer to the EFI_PCI_IO_PROTOCOL.\r | |
115 | @param Width Signifies the width of the memory or I/O operations.\r | |
116 | @param Address The base address of the memory or I/O operations. \r | |
117 | @param Mask Mask used for the polling criteria.\r | |
118 | @param Value The comparison value used for the polling exit criteria.\r | |
119 | @param Delay The number of 100 ns units to poll.\r | |
120 | @param Result Pointer to the last value read from the memory location.\r | |
121 | \r | |
122 | @retval EFI_SUCCESS The last data returned from the access matched the poll exit criteria.\r | |
123 | @retval EFI_TIMEOUT Delay expired before a match occurred.\r | |
124 | @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r | |
125 | @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r | |
126 | \r | |
127 | **/\r | |
ead42efc | 128 | EFI_STATUS\r |
129 | EFIAPI\r | |
130 | PciIoPollIo (\r | |
131 | IN EFI_PCI_IO_PROTOCOL *This,\r | |
132 | IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r | |
133 | IN UINT8 BarIndex,\r | |
134 | IN UINT64 Offset,\r | |
135 | IN UINT64 Mask,\r | |
136 | IN UINT64 Value,\r | |
137 | IN UINT64 Delay,\r | |
138 | OUT UINT64 *Result\r | |
139 | )\r | |
ead42efc | 140 | ;\r |
141 | \r | |
57076f45 | 142 | /** \r |
143 | Enable a PCI driver to access PCI controller registers in the PCI memory or I/O space.\r | |
144 | \r | |
145 | @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r | |
146 | @param Width Signifies the width of the memory or I/O operations.\r | |
147 | @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r | |
148 | base address for the memory or I/O operation to perform. \r | |
149 | @param Offset The offset within the selected BAR to start the memory or I/O operation. \r | |
150 | @param Count The number of memory or I/O operations to perform.\r | |
151 | @param Buffer For read operations, the destination buffer to store the results. For write\r | |
152 | operations, the source buffer to write data from. \r | |
153 | \r | |
154 | @retval EFI_SUCCESS The data was read from or written to the PCI controller.\r | |
155 | @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r | |
156 | @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not\r | |
157 | valid for the PCI BAR specified by BarIndex. \r | |
158 | @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r | |
159 | @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r | |
160 | \r | |
161 | **/\r | |
ead42efc | 162 | EFI_STATUS\r |
163 | EFIAPI\r | |
164 | PciIoMemRead (\r | |
165 | IN EFI_PCI_IO_PROTOCOL *This,\r | |
166 | IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r | |
167 | IN UINT8 BarIndex,\r | |
168 | IN UINT64 Offset,\r | |
169 | IN UINTN Count,\r | |
170 | IN OUT VOID *Buffer\r | |
171 | )\r | |
ead42efc | 172 | ;\r |
173 | \r | |
57076f45 | 174 | /** \r |
175 | Enable a PCI driver to access PCI controller registers in the PCI memory or I/O space.\r | |
176 | \r | |
177 | @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r | |
178 | @param Width Signifies the width of the memory or I/O operations.\r | |
179 | @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r | |
180 | base address for the memory or I/O operation to perform. \r | |
181 | @param Offset The offset within the selected BAR to start the memory or I/O operation. \r | |
182 | @param Count The number of memory or I/O operations to perform.\r | |
183 | @param Buffer For read operations, the destination buffer to store the results. For write\r | |
184 | operations, the source buffer to write data from. \r | |
185 | \r | |
186 | @retval EFI_SUCCESS The data was read from or written to the PCI controller.\r | |
187 | @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r | |
188 | @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not\r | |
189 | valid for the PCI BAR specified by BarIndex. \r | |
190 | @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r | |
191 | @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r | |
192 | \r | |
193 | **/\r | |
ead42efc | 194 | EFI_STATUS\r |
195 | EFIAPI\r | |
196 | PciIoMemWrite (\r | |
197 | IN EFI_PCI_IO_PROTOCOL *This,\r | |
198 | IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r | |
199 | IN UINT8 BarIndex,\r | |
200 | IN UINT64 Offset,\r | |
201 | IN UINTN Count,\r | |
202 | IN OUT VOID *Buffer\r | |
203 | )\r | |
ead42efc | 204 | ;\r |
205 | \r | |
57076f45 | 206 | /** \r |
207 | Enable a PCI driver to access PCI controller registers in the PCI memory or I/O space.\r | |
208 | \r | |
209 | @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r | |
210 | @param Width Signifies the width of the memory or I/O operations.\r | |
211 | @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r | |
212 | base address for the memory or I/O operation to perform. \r | |
213 | @param Offset The offset within the selected BAR to start the memory or I/O operation. \r | |
214 | @param Count The number of memory or I/O operations to perform.\r | |
215 | @param Buffer For read operations, the destination buffer to store the results. For write\r | |
216 | operations, the source buffer to write data from. \r | |
217 | \r | |
218 | @retval EFI_SUCCESS The data was read from or written to the PCI controller.\r | |
219 | @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r | |
220 | @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not\r | |
221 | valid for the PCI BAR specified by BarIndex. \r | |
222 | @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r | |
223 | @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r | |
224 | \r | |
225 | **/\r | |
ead42efc | 226 | EFI_STATUS\r |
227 | EFIAPI\r | |
228 | PciIoIoRead (\r | |
229 | IN EFI_PCI_IO_PROTOCOL *This,\r | |
230 | IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r | |
231 | IN UINT8 BarIndex,\r | |
232 | IN UINT64 Offset,\r | |
233 | IN UINTN Count,\r | |
234 | IN OUT VOID *Buffer\r | |
235 | )\r | |
ead42efc | 236 | ;\r |
237 | \r | |
57076f45 | 238 | /** \r |
239 | Enable a PCI driver to access PCI controller registers in the PCI memory or I/O space.\r | |
240 | \r | |
241 | @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r | |
242 | @param Width Signifies the width of the memory or I/O operations.\r | |
243 | @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r | |
244 | base address for the memory or I/O operation to perform. \r | |
245 | @param Offset The offset within the selected BAR to start the memory or I/O operation. \r | |
246 | @param Count The number of memory or I/O operations to perform.\r | |
247 | @param Buffer For read operations, the destination buffer to store the results. For write\r | |
248 | operations, the source buffer to write data from. \r | |
249 | \r | |
250 | @retval EFI_SUCCESS The data was read from or written to the PCI controller.\r | |
251 | @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r | |
252 | @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not\r | |
253 | valid for the PCI BAR specified by BarIndex. \r | |
254 | @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r | |
255 | @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r | |
256 | \r | |
257 | **/\r | |
ead42efc | 258 | EFI_STATUS\r |
259 | EFIAPI\r | |
260 | PciIoIoWrite (\r | |
261 | IN EFI_PCI_IO_PROTOCOL *This,\r | |
262 | IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r | |
263 | IN UINT8 BarIndex,\r | |
264 | IN UINT64 Offset,\r | |
265 | IN UINTN Count,\r | |
266 | IN OUT VOID *Buffer\r | |
267 | )\r | |
ead42efc | 268 | ;\r |
269 | \r | |
57076f45 | 270 | /** \r |
271 | Enable a PCI driver to access PCI controller registers in PCI configuration space.\r | |
272 | \r | |
273 | @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. \r | |
274 | @param Width Signifies the width of the memory operations.\r | |
275 | @param Offset The offset within the PCI configuration space for the PCI controller.\r | |
276 | @param Count The number of PCI configuration operations to perform.\r | |
277 | @param Buffer For read operations, the destination buffer to store the results. For write\r | |
278 | operations, the source buffer to write data from.\r | |
279 | \r | |
280 | \r | |
281 | @retval EFI_SUCCESS The data was read from or written to the PCI controller.\r | |
282 | @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not\r | |
283 | valid for the PCI configuration header of the PCI controller.\r | |
284 | @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. \r | |
285 | @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid. \r | |
286 | \r | |
287 | **/\r | |
ead42efc | 288 | EFI_STATUS\r |
289 | EFIAPI\r | |
290 | PciIoConfigRead (\r | |
291 | IN EFI_PCI_IO_PROTOCOL *This,\r | |
292 | IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r | |
293 | IN UINT32 Offset,\r | |
294 | IN UINTN Count,\r | |
295 | IN OUT VOID *Buffer\r | |
296 | )\r | |
ead42efc | 297 | ;\r |
298 | \r | |
57076f45 | 299 | /** \r |
300 | Enable a PCI driver to access PCI controller registers in PCI configuration space.\r | |
301 | \r | |
302 | @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. \r | |
303 | @param Width Signifies the width of the memory operations.\r | |
304 | @param Offset The offset within the PCI configuration space for the PCI controller.\r | |
305 | @param Count The number of PCI configuration operations to perform.\r | |
306 | @param Buffer For read operations, the destination buffer to store the results. For write\r | |
307 | operations, the source buffer to write data from.\r | |
308 | \r | |
309 | \r | |
310 | @retval EFI_SUCCESS The data was read from or written to the PCI controller.\r | |
311 | @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not\r | |
312 | valid for the PCI configuration header of the PCI controller.\r | |
313 | @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. \r | |
314 | @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid. \r | |
315 | \r | |
316 | **/\r | |
ead42efc | 317 | EFI_STATUS\r |
318 | EFIAPI\r | |
319 | PciIoConfigWrite (\r | |
320 | IN EFI_PCI_IO_PROTOCOL *This,\r | |
321 | IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r | |
322 | IN UINT32 Offset,\r | |
323 | IN UINTN Count,\r | |
324 | IN OUT VOID *Buffer\r | |
325 | )\r | |
ead42efc | 326 | ;\r |
327 | \r | |
57076f45 | 328 | /** \r |
329 | Enables a PCI driver to copy one region of PCI memory space to another region of PCI\r | |
330 | memory space.\r | |
331 | \r | |
332 | @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r | |
333 | @param Width Signifies the width of the memory operations.\r | |
334 | @param DestBarIndex The BAR index in the standard PCI Configuration header to use as the\r | |
335 | base address for the memory operation to perform. \r | |
336 | @param DestOffset The destination offset within the BAR specified by DestBarIndex to\r | |
337 | start the memory writes for the copy operation. \r | |
338 | @param SrcBarIndex The BAR index in the standard PCI Configuration header to use as the\r | |
339 | base address for the memory operation to perform. \r | |
340 | @param SrcOffset The source offset within the BAR specified by SrcBarIndex to start\r | |
341 | the memory reads for the copy operation. \r | |
342 | @param Count The number of memory operations to perform. Bytes moved is Width\r | |
343 | size * Count, starting at DestOffset and SrcOffset. \r | |
344 | \r | |
345 | @retval EFI_SUCCESS The data was copied from one memory region to another memory region.\r | |
346 | @retval EFI_UNSUPPORTED DestBarIndex not valid for this PCI controller.\r | |
347 | @retval EFI_UNSUPPORTED SrcBarIndex not valid for this PCI controller.\r | |
348 | @retval EFI_UNSUPPORTED The address range specified by DestOffset, Width, and Count\r | |
349 | is not valid for the PCI BAR specified by DestBarIndex. \r | |
350 | @retval EFI_UNSUPPORTED The address range specified by SrcOffset, Width, and Count is\r | |
351 | not valid for the PCI BAR specified by SrcBarIndex. \r | |
352 | @retval EFI_INVALID_PARAMETER Width is invalid.\r | |
353 | @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r | |
354 | \r | |
355 | **/\r | |
ead42efc | 356 | EFI_STATUS\r |
357 | EFIAPI\r | |
358 | PciIoCopyMem (\r | |
359 | IN EFI_PCI_IO_PROTOCOL *This,\r | |
360 | IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r | |
361 | IN UINT8 DestBarIndex,\r | |
362 | IN UINT64 DestOffset,\r | |
363 | IN UINT8 SrcBarIndex,\r | |
364 | IN UINT64 SrcOffset,\r | |
365 | IN UINTN Count\r | |
366 | )\r | |
ead42efc | 367 | ;\r |
368 | \r | |
57076f45 | 369 | /** \r |
370 | Provides the PCI controller-Cspecific addresses needed to access system memory.\r | |
371 | \r | |
372 | @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r | |
373 | @param Operation Indicates if the bus master is going to read or write to system memory.\r | |
374 | @param HostAddress The system memory address to map to the PCI controller.\r | |
375 | @param NumberOfBytes On input the number of bytes to map. On output the number of bytes\r | |
376 | that were mapped. \r | |
377 | @param DeviceAddress The resulting map address for the bus master PCI controller to use to\r | |
378 | access the hosts HostAddress. \r | |
379 | @param Mapping A resulting value to pass to Unmap().\r | |
380 | \r | |
381 | @retval EFI_SUCCESS The range was mapped for the returned NumberOfBytes.\r | |
382 | @retval EFI_UNSUPPORTED The HostAddress cannot be mapped as a common buffer. \r | |
383 | @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r | |
384 | @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r | |
385 | @retval EFI_DEVICE_ERROR The system hardware could not map the requested address.\r | |
386 | \r | |
387 | **/\r | |
ead42efc | 388 | EFI_STATUS\r |
389 | EFIAPI\r | |
390 | PciIoMap (\r | |
391 | IN EFI_PCI_IO_PROTOCOL *This,\r | |
392 | IN EFI_PCI_IO_PROTOCOL_OPERATION Operation,\r | |
393 | IN VOID *HostAddress,\r | |
394 | IN OUT UINTN *NumberOfBytes,\r | |
395 | OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,\r | |
396 | OUT VOID **Mapping\r | |
397 | )\r | |
ead42efc | 398 | ;\r |
399 | \r | |
57076f45 | 400 | /** \r |
401 | Completes the Map() operation and releases any corresponding resources.\r | |
402 | \r | |
403 | @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. \r | |
404 | @param Mapping The mapping value returned from Map().\r | |
405 | \r | |
406 | @retval EFI_SUCCESS The range was unmapped.\r | |
407 | @retval EFI_DEVICE_ERROR The data was not committed to the target system memory.\r | |
408 | \r | |
409 | **/\r | |
ead42efc | 410 | EFI_STATUS\r |
411 | EFIAPI\r | |
412 | PciIoUnmap (\r | |
413 | IN EFI_PCI_IO_PROTOCOL *This,\r | |
414 | IN VOID *Mapping\r | |
415 | )\r | |
ead42efc | 416 | ;\r |
417 | \r | |
57076f45 | 418 | /** \r |
419 | Allocates pages that are suitable for an EfiPciIoOperationBusMasterCommonBuffer\r | |
420 | mapping. \r | |
421 | \r | |
422 | @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r | |
423 | @param Type This parameter is not used and must be ignored.\r | |
424 | @param MemoryType The type of memory to allocate, EfiBootServicesData or\r | |
425 | EfiRuntimeServicesData. \r | |
426 | @param Pages The number of pages to allocate. \r | |
427 | @param HostAddress A pointer to store the base system memory address of the\r | |
428 | allocated range. \r | |
429 | @param Attributes The requested bit mask of attributes for the allocated range.\r | |
430 | \r | |
431 | @retval EFI_SUCCESS The requested memory pages were allocated.\r | |
432 | @retval EFI_UNSUPPORTED Attributes is unsupported. The only legal attribute bits are\r | |
433 | MEMORY_WRITE_COMBINE and MEMORY_CACHED. \r | |
434 | @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r | |
435 | @retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated. \r | |
436 | \r | |
437 | **/\r | |
ead42efc | 438 | EFI_STATUS\r |
439 | EFIAPI\r | |
440 | PciIoAllocateBuffer (\r | |
441 | IN EFI_PCI_IO_PROTOCOL *This,\r | |
442 | IN EFI_ALLOCATE_TYPE Type,\r | |
443 | IN EFI_MEMORY_TYPE MemoryType,\r | |
444 | IN UINTN Pages,\r | |
445 | OUT VOID **HostAddress,\r | |
446 | IN UINT64 Attributes\r | |
447 | )\r | |
ead42efc | 448 | ;\r |
449 | \r | |
57076f45 | 450 | /** \r |
451 | Frees memory that was allocated with AllocateBuffer().\r | |
452 | \r | |
453 | @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. \r | |
454 | @param Pages The number of pages to free. \r | |
455 | @param HostAddress The base system memory address of the allocated range. \r | |
456 | \r | |
457 | @retval EFI_SUCCESS The requested memory pages were freed.\r | |
458 | @retval EFI_INVALID_PARAMETER The memory range specified by HostAddress and Pages\r | |
459 | was not allocated with AllocateBuffer().\r | |
460 | \r | |
461 | **/\r | |
ead42efc | 462 | EFI_STATUS\r |
463 | EFIAPI\r | |
464 | PciIoFreeBuffer (\r | |
465 | IN EFI_PCI_IO_PROTOCOL *This,\r | |
466 | IN UINTN Pages,\r | |
467 | IN VOID *HostAddress\r | |
468 | )\r | |
ead42efc | 469 | ;\r |
470 | \r | |
57076f45 | 471 | /** \r |
472 | Flushes all PCI posted write transactions from a PCI host bridge to system memory.\r | |
473 | \r | |
474 | @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. \r | |
475 | \r | |
476 | @retval EFI_SUCCESS The PCI posted write transactions were flushed from the PCI host\r | |
477 | bridge to system memory. \r | |
478 | @retval EFI_DEVICE_ERROR The PCI posted write transactions were not flushed from the PCI\r | |
479 | host bridge due to a hardware error. \r | |
480 | \r | |
481 | **/\r | |
ead42efc | 482 | EFI_STATUS\r |
483 | EFIAPI\r | |
484 | PciIoFlush (\r | |
485 | IN EFI_PCI_IO_PROTOCOL *This\r | |
486 | )\r | |
ead42efc | 487 | ;\r |
488 | \r | |
57076f45 | 489 | /** \r |
490 | Retrieves this PCI controller's current PCI bus number, device number, and function number.\r | |
491 | \r | |
492 | @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. \r | |
493 | @param SegmentNumber The PCI controller's current PCI segment number.\r | |
494 | @param BusNumber The PCI controller's current PCI bus number.\r | |
495 | @param DeviceNumber The PCI controller's current PCI device number.\r | |
496 | @param FunctionNumber The PCI controller's current PCI function number.\r | |
497 | \r | |
498 | @retval EFI_SUCCESS The PCI controller location was returned. \r | |
499 | @retval EFI_INVALID_PARAMETER One or more parameters are invalid. \r | |
500 | \r | |
501 | **/\r | |
ead42efc | 502 | EFI_STATUS\r |
503 | EFIAPI\r | |
504 | PciIoGetLocation (\r | |
505 | IN EFI_PCI_IO_PROTOCOL *This,\r | |
506 | OUT UINTN *Segment,\r | |
507 | OUT UINTN *Bus,\r | |
508 | OUT UINTN *Device,\r | |
509 | OUT UINTN *Function\r | |
510 | )\r | |
ead42efc | 511 | ;\r |
512 | \r | |
57076f45 | 513 | /**\r |
514 | Check BAR type for PCI resource.\r | |
515 | \r | |
516 | @param PciIoDevice PCI device instance\r | |
517 | @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r | |
518 | base address for the memory or I/O operation to perform. \r | |
519 | @param BarType Memory or I/O\r | |
520 | \r | |
521 | @return whether Pci device's bar type is same with input BarType.\r | |
522 | **/\r | |
ead42efc | 523 | BOOLEAN\r |
524 | CheckBarType (\r | |
525 | IN PCI_IO_DEVICE *PciIoDevice,\r | |
526 | UINT8 BarIndex,\r | |
527 | PCI_BAR_TYPE BarType\r | |
528 | )\r | |
ead42efc | 529 | ;\r |
530 | \r | |
57076f45 | 531 | /**\r |
532 | Set/Disable new attributes to a Root Bridge\r | |
533 | \r | |
534 | @param PciIoDevice Pci device instance\r | |
535 | @param Attributes New attribute want to be set\r | |
536 | @param Operation Set or Disable\r | |
537 | \r | |
538 | @retval EFI_UNSUPPORTED If root bridge does not support change attribute\r | |
539 | @retval EFI_SUCCESS Success operation.\r | |
540 | **/\r | |
ead42efc | 541 | EFI_STATUS\r |
542 | ModifyRootBridgeAttributes (\r | |
543 | IN PCI_IO_DEVICE *PciIoDevice,\r | |
544 | IN UINT64 Attributes,\r | |
545 | IN EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION Operation\r | |
546 | )\r | |
ead42efc | 547 | ;\r |
548 | \r | |
57076f45 | 549 | /**\r |
550 | Check whether this device can be enable/disable to snoop\r | |
551 | \r | |
552 | @param PciIoDevice Pci device instance\r | |
553 | @param Operation Enable/Disable\r | |
554 | \r | |
555 | @retval EFI_UNSUPPORTED Pci device is not GFX device or not support snoop\r | |
556 | @retval EFI_SUCCESS Snoop can be supported.\r | |
557 | **/\r | |
ead42efc | 558 | EFI_STATUS\r |
559 | SupportPaletteSnoopAttributes (\r | |
560 | IN PCI_IO_DEVICE *PciIoDevice,\r | |
561 | IN EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION Operation\r | |
562 | )\r | |
ead42efc | 563 | ;\r |
564 | \r | |
57076f45 | 565 | /** \r |
566 | Performs an operation on the attributes that this PCI controller supports. The operations include\r | |
567 | getting the set of supported attributes, retrieving the current attributes, setting the current \r | |
568 | attributes, enabling attributes, and disabling attributes. \r | |
569 | \r | |
570 | @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. \r | |
571 | @param Operation The operation to perform on the attributes for this PCI controller.\r | |
572 | @param Attributes The mask of attributes that are used for Set, Enable, and Disable\r | |
573 | operations. \r | |
574 | @param Result A pointer to the result mask of attributes that are returned for the Get\r | |
575 | and Supported operations. \r | |
576 | \r | |
577 | @retval EFI_SUCCESS The operation on the PCI controller's attributes was completed.\r | |
578 | @retval EFI_INVALID_PARAMETER One or more parameters are invalid. \r | |
579 | @retval EFI_UNSUPPORTED one or more of the bits set in \r | |
580 | Attributes are not supported by this PCI controller or one of\r | |
581 | its parent bridges when Operation is Set, Enable or Disable.\r | |
582 | \r | |
583 | **/\r | |
ead42efc | 584 | EFI_STATUS\r |
585 | EFIAPI\r | |
586 | PciIoAttributes (\r | |
587 | IN EFI_PCI_IO_PROTOCOL * This,\r | |
588 | IN EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION Operation,\r | |
589 | IN UINT64 Attributes,\r | |
590 | OUT UINT64 *Result OPTIONAL\r | |
591 | )\r | |
ead42efc | 592 | ;\r |
593 | \r | |
57076f45 | 594 | /** \r |
595 | Gets the attributes that this PCI controller supports setting on a BAR using\r | |
596 | SetBarAttributes(), and retrieves the list of resource descriptors for a BAR.\r | |
597 | \r | |
598 | @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. \r | |
599 | @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r | |
600 | base address for resource range. The legal range for this field is 0..5.\r | |
601 | @param Supports A pointer to the mask of attributes that this PCI controller supports\r | |
602 | setting for this BAR with SetBarAttributes(). \r | |
603 | @param Resources A pointer to the ACPI 2.0 resource descriptors that describe the current\r | |
604 | configuration of this BAR of the PCI controller. \r | |
605 | \r | |
606 | @retval EFI_SUCCESS If Supports is not NULL, then the attributes that the PCI \r | |
607 | controller supports are returned in Supports. If Resources \r | |
608 | is not NULL, then the ACPI 2.0 resource descriptors that the PCI\r | |
609 | controller is currently using are returned in Resources. \r | |
610 | @retval EFI_INVALID_PARAMETER Both Supports and Attributes are NULL.\r | |
611 | @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r | |
612 | @retval EFI_OUT_OF_RESOURCES There are not enough resources available to allocate\r | |
613 | Resources. \r | |
614 | \r | |
615 | **/\r | |
ead42efc | 616 | EFI_STATUS\r |
617 | EFIAPI\r | |
618 | PciIoGetBarAttributes (\r | |
619 | IN EFI_PCI_IO_PROTOCOL * This,\r | |
620 | IN UINT8 BarIndex,\r | |
621 | OUT UINT64 *Supports, OPTIONAL\r | |
622 | OUT VOID **Resources OPTIONAL\r | |
623 | )\r | |
ead42efc | 624 | ;\r |
625 | \r | |
57076f45 | 626 | /** \r |
627 | Sets the attributes for a range of a BAR on a PCI controller.\r | |
628 | \r | |
629 | @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. \r | |
630 | @param Attributes The mask of attributes to set for the resource range specified by\r | |
631 | BarIndex, Offset, and Length. \r | |
632 | @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r | |
633 | base address for resource range. The legal range for this field is 0..5.\r | |
634 | @param Offset A pointer to the BAR relative base address of the resource range to be\r | |
635 | modified by the attributes specified by Attributes. \r | |
636 | @param Length A pointer to the length of the resource range to be modified by the\r | |
637 | attributes specified by Attributes. \r | |
638 | \r | |
639 | @retval EFI_SUCCESS The set of attributes specified by Attributes for the resource \r | |
640 | range specified by BarIndex, Offset, and Length were \r | |
641 | set on the PCI controller, and the actual resource range is returned\r | |
642 | in Offset and Length. \r | |
643 | @retval EFI_INVALID_PARAMETER Offset or Length is NULL.\r | |
644 | @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r | |
645 | @retval EFI_OUT_OF_RESOURCES There are not enough resources to set the attributes on the\r | |
646 | resource range specified by BarIndex, Offset, and \r | |
647 | Length. \r | |
648 | \r | |
649 | **/\r | |
ead42efc | 650 | EFI_STATUS\r |
651 | EFIAPI\r | |
652 | PciIoSetBarAttributes (\r | |
653 | IN EFI_PCI_IO_PROTOCOL *This,\r | |
654 | IN UINT64 Attributes,\r | |
655 | IN UINT8 BarIndex,\r | |
656 | IN OUT UINT64 *Offset,\r | |
657 | IN OUT UINT64 *Length\r | |
658 | )\r | |
ead42efc | 659 | ;\r |
660 | \r | |
57076f45 | 661 | /**\r |
662 | Program parent bridge's attribute recurrently.\r | |
663 | \r | |
664 | @param PciIoDevice Child Pci device instance\r | |
665 | @param Operation The operation to perform on the attributes for this PCI controller.\r | |
666 | @param Attributes The mask of attributes that are used for Set, Enable, and Disable\r | |
667 | operations.\r | |
668 | \r | |
669 | @retval EFI_SUCCESS The operation on the PCI controller's attributes was completed.\r | |
670 | @retval EFI_INVALID_PARAMETER One or more parameters are invalid. \r | |
671 | @retval EFI_UNSUPPORTED one or more of the bits set in \r | |
672 | Attributes are not supported by this PCI controller or one of\r | |
673 | its parent bridges when Operation is Set, Enable or Disable.\r | |
674 | \r | |
675 | **/\r | |
ead42efc | 676 | EFI_STATUS\r |
677 | UpStreamBridgesAttributes (\r | |
678 | IN PCI_IO_DEVICE *PciIoDevice,\r | |
679 | IN EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION Operation,\r | |
680 | IN UINT64 Attributes\r | |
681 | )\r | |
ead42efc | 682 | ;\r |
683 | \r | |
57076f45 | 684 | /**\r |
685 | Test whether two Pci device has same parent bridge.\r | |
686 | \r | |
687 | @param PciDevice1 the frist pci device for testing\r | |
688 | @param PciDevice2 the second pci device for testing\r | |
689 | \r | |
690 | @return whether two Pci device has same parent bridge.\r | |
691 | **/\r | |
ead42efc | 692 | BOOLEAN\r |
693 | PciDevicesOnTheSamePath (\r | |
694 | IN PCI_IO_DEVICE *PciDevice1,\r | |
695 | IN PCI_IO_DEVICE *PciDevice2\r | |
696 | )\r | |
ead42efc | 697 | ;\r |
698 | \r | |
699 | #endif\r |