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Enhanced the PCI Bus DXE module
[mirror_edk2.git] / IntelFrameworkModulePkg / Bus / Pci / PciBusDxe / pcibus.h
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3db51098 1/**@file\r
ead42efc 2\r
ea5632e5 3Copyright (c) 2006, Intel Corporation\r
4All rights reserved. This program and the accompanying materials\r
5are licensed and made available under the terms and conditions of the BSD License\r
6which accompanies this distribution. The full text of the license may be found at\r
7http://opensource.org/licenses/bsd-license.php\r
8\r
9THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
10WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
ead42efc 11\r
3db51098 12**/\r
ead42efc 13\r
ead42efc 14\r
15#ifndef _EFI_PCI_BUS_H\r
16#define _EFI_PCI_BUS_H\r
17\r
ed7748fe 18\r
694b922c 19#include <FrameworkDxe.h>\r
20\r
ed7748fe 21\r
ead42efc 22#include <Protocol/LoadedImage.h>\r
23#include <Protocol/PciHostBridgeResourceAllocation.h>\r
24#include <Protocol/PciIo.h>\r
25#include <Guid/PciHotplugDevice.h>\r
26#include <Protocol/PciRootBridgeIo.h>\r
27#include <Protocol/PciHotPlugRequest.h>\r
28#include <Protocol/DevicePath.h>\r
29#include <Protocol/PciPlatform.h>\r
30#include <Protocol/PciHotPlugInit.h>\r
31#include <Protocol/Decompress.h>\r
32#include <Guid/PciOptionRomTable.h>\r
33#include <Protocol/BusSpecificDriverOverride.h>\r
34#include <Protocol/UgaIo.h>\r
ea5632e5 35#include <Protocol/IncompatiblePciDeviceSupport.h>\r
ed7748fe 36\r
ead42efc 37#include <Library/DebugLib.h>\r
38#include <Library/UefiDriverEntryPoint.h>\r
39#include <Library/BaseLib.h>\r
40#include <Library/UefiLib.h>\r
41#include <Library/BaseMemoryLib.h>\r
42#include <Library/ReportStatusCodeLib.h>\r
43#include <Library/MemoryAllocationLib.h>\r
44#include <Library/UefiBootServicesTableLib.h>\r
45#include <Library/DevicePathLib.h>\r
46#include <Library/PcdLib.h>\r
47#include <Library/PciIncompatibleDeviceSupportLib.h>\r
48\r
b1ef4015 49#include <IndustryStandard/Pci23.h>\r
50#include <IndustryStandard/PeImage.h>\r
ead42efc 51#include <IndustryStandard/Acpi.h>\r
52#include "ComponentName.h"\r
53\r
54//\r
55// Driver Produced Protocol Prototypes\r
56//\r
57\r
58#define VGABASE1 0x3B0\r
59#define VGALIMIT1 0x3BB\r
60\r
61#define VGABASE2 0x3C0\r
62#define VGALIMIT2 0x3DF\r
63\r
64#define ISABASE 0x100\r
65#define ISALIMIT 0x3FF\r
66\r
67typedef enum {\r
68 PciBarTypeUnknown = 0,\r
69 PciBarTypeIo16,\r
70 PciBarTypeIo32,\r
71 PciBarTypeMem32,\r
72 PciBarTypePMem32,\r
73 PciBarTypeMem64,\r
74 PciBarTypePMem64,\r
75 PciBarTypeIo,\r
76 PciBarTypeMem,\r
77 PciBarTypeMaxType\r
78} PCI_BAR_TYPE;\r
79\r
80typedef struct {\r
81 UINT64 BaseAddress;\r
82 UINT64 Length;\r
83 UINT64 Alignment;\r
84 PCI_BAR_TYPE BarType;\r
85 BOOLEAN Prefetchable;\r
86 UINT8 MemType;\r
87 UINT8 Offset;\r
88} PCI_BAR;\r
89\r
90#define PPB_BAR_0 0\r
91#define PPB_BAR_1 1\r
92#define PPB_IO_RANGE 2\r
93#define PPB_MEM32_RANGE 3\r
94#define PPB_PMEM32_RANGE 4\r
95#define PPB_PMEM64_RANGE 5\r
96#define PPB_MEM64_RANGE 0xFF\r
97\r
98#define P2C_BAR_0 0\r
99#define P2C_MEM_1 1\r
100#define P2C_MEM_2 2\r
101#define P2C_IO_1 3\r
102#define P2C_IO_2 4\r
103\r
104#define PCI_IO_DEVICE_SIGNATURE EFI_SIGNATURE_32 ('p', 'c', 'i', 'o')\r
105\r
106#define EFI_BRIDGE_IO32_DECODE_SUPPORTED 0x0001\r
107#define EFI_BRIDGE_PMEM32_DECODE_SUPPORTED 0x0002\r
108#define EFI_BRIDGE_PMEM64_DECODE_SUPPORTED 0x0004\r
109#define EFI_BRIDGE_IO16_DECODE_SUPPORTED 0x0008\r
110#define EFI_BRIDGE_PMEM_MEM_COMBINE_SUPPORTED 0x0010\r
111#define EFI_BRIDGE_MEM64_DECODE_SUPPORTED 0x0020\r
112#define EFI_BRIDGE_MEM32_DECODE_SUPPORTED 0x0040\r
31bbf49f 113#define EFI_BRIDGE_IOEN1K_DECODE_SUPPORTED 0x0080\r
ead42efc 114\r
115#define PCI_MAX_HOST_BRIDGE_NUM 0x0010\r
116//\r
117// Define resource status constant\r
118//\r
119#define EFI_RESOURCE_NONEXISTENT 0xFFFFFFFFFFFFFFFFULL\r
120#define EFI_RESOURCE_LESS 0xFFFFFFFFFFFFFFFEULL\r
121#define EFI_RESOURCE_SATISFIED 0x0000000000000000ULL\r
122\r
123//\r
124// Define option for attribute\r
125//\r
126#define EFI_SET_SUPPORTS 0\r
127#define EFI_SET_ATTRIBUTES 1\r
128\r
129typedef struct _PCI_IO_DEVICE {\r
130 UINT32 Signature;\r
131 EFI_HANDLE Handle;\r
132 EFI_PCI_IO_PROTOCOL PciIo;\r
133 LIST_ENTRY Link;\r
134\r
135 EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL PciDriverOverride;\r
136 EFI_DEVICE_PATH_PROTOCOL *DevicePath;\r
137 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;\r
138\r
139 //\r
140 // PCI configuration space header type\r
141 //\r
142 PCI_TYPE00 Pci;\r
143\r
144 //\r
145 // Bus number, Device number, Function number\r
146 //\r
147 UINT8 BusNumber;\r
148 UINT8 DeviceNumber;\r
149 UINT8 FunctionNumber;\r
150\r
151 //\r
152 // BAR for this PCI Device\r
153 //\r
154 PCI_BAR PciBar[PCI_MAX_BAR];\r
155\r
156 //\r
157 // The bridge device this pci device is subject to\r
158 //\r
159 struct _PCI_IO_DEVICE *Parent;\r
160\r
161 //\r
162 // A linked list for children Pci Device if it is bridge device\r
163 //\r
164 LIST_ENTRY ChildList;\r
165\r
166 //\r
167 // TURE if the PCI bus driver creates the handle for this PCI device\r
168 //\r
169 BOOLEAN Registered;\r
170\r
171 //\r
172 // TRUE if the PCI bus driver successfully allocates the resource required by\r
173 // this PCI device\r
174 //\r
175 BOOLEAN Allocated;\r
176\r
177 //\r
178 // The attribute this PCI device currently set\r
179 //\r
180 UINT64 Attributes;\r
181\r
182 //\r
183 // The attributes this PCI device actually supports\r
184 //\r
185 UINT64 Supports;\r
186\r
187 //\r
188 // The resource decode the bridge supports\r
189 //\r
190 UINT32 Decodes;\r
191\r
192 //\r
193 // The OptionRom Size\r
194 //\r
195 UINT64 RomSize;\r
196\r
197 //\r
198 // The OptionRom Size\r
199 //\r
200 UINT64 RomBase;\r
201\r
202 //\r
203 // TRUE if all OpROM (in device or in platform specific position) have been processed\r
204 //\r
205 BOOLEAN AllOpRomProcessed;\r
206\r
207 //\r
208 // TRUE if there is any EFI driver in the OptionRom\r
209 //\r
210 BOOLEAN BusOverride;\r
211\r
212 //\r
213 // A list tracking reserved resource on a bridge device\r
214 //\r
215 LIST_ENTRY ReservedResourceList;\r
216\r
217 //\r
218 // A list tracking image handle of platform specific overriding driver\r
219 //\r
220 LIST_ENTRY OptionRomDriverList;\r
221\r
222 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *ResourcePaddingDescriptors;\r
223 EFI_HPC_PADDING_ATTRIBUTES PaddingAttributes;\r
224\r
225 BOOLEAN IsPciExp;\r
226\r
227} PCI_IO_DEVICE;\r
228\r
229\r
230#define PCI_IO_DEVICE_FROM_PCI_IO_THIS(a) \\r
231 CR (a, PCI_IO_DEVICE, PciIo, PCI_IO_DEVICE_SIGNATURE)\r
232\r
233#define PCI_IO_DEVICE_FROM_PCI_DRIVER_OVERRIDE_THIS(a) \\r
234 CR (a, PCI_IO_DEVICE, PciDriverOverride, PCI_IO_DEVICE_SIGNATURE)\r
235\r
236#define PCI_IO_DEVICE_FROM_LINK(a) \\r
237 CR (a, PCI_IO_DEVICE, Link, PCI_IO_DEVICE_SIGNATURE)\r
238\r
239//\r
240// Global Variables\r
241//\r
ea5632e5 242extern EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL *gEfiIncompatiblePciDeviceSupport;\r
ead42efc 243extern EFI_DRIVER_BINDING_PROTOCOL gPciBusDriverBinding;\r
244extern EFI_COMPONENT_NAME_PROTOCOL gPciBusComponentName;\r
733f03aa 245extern EFI_COMPONENT_NAME2_PROTOCOL gPciBusComponentName2;\r
ead42efc 246extern LIST_ENTRY gPciDevicePool;\r
247extern BOOLEAN gFullEnumeration;\r
248extern UINTN gPciHostBridgeNumber;\r
249extern EFI_HANDLE gPciHostBrigeHandles[PCI_MAX_HOST_BRIDGE_NUM];\r
250extern UINT64 gAllOne;\r
251extern UINT64 gAllZero;\r
252\r
253extern EFI_PCI_PLATFORM_PROTOCOL *gPciPlatformProtocol;\r
254\r
255#include "PciIo.h"\r
256#include "PciCommand.h"\r
257#include "PciDeviceSupport.h"\r
258#include "PciEnumerator.h"\r
259#include "PciEnumeratorSupport.h"\r
260#include "PciDriverOverride.h"\r
261#include "PciRomTable.h"\r
262#include "PciOptionRomSupport.h"\r
263#include "PciPowerManagement.h"\r
264#include "PciHotPlugSupport.h"\r
265#include "PciLib.h"\r
266\r
267//\r
268// PCI Bus Support Function Prototypes\r
269//\r
270EFI_STATUS\r
271EFIAPI\r
272PciBusDriverBindingSupported (\r
273 IN EFI_DRIVER_BINDING_PROTOCOL *This,\r
274 IN EFI_HANDLE Controller,\r
275 IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath\r
276 );\r
277\r
278EFI_STATUS\r
279EFIAPI\r
280PciBusDriverBindingStart (\r
281 IN EFI_DRIVER_BINDING_PROTOCOL *This,\r
282 IN EFI_HANDLE Controller,\r
283 IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath\r
284 );\r
285\r
286EFI_STATUS\r
287EFIAPI\r
288PciBusDriverBindingStop (\r
289 IN EFI_DRIVER_BINDING_PROTOCOL *This,\r
290 IN EFI_HANDLE Controller,\r
291 IN UINTN NumberOfChildren,\r
292 IN EFI_HANDLE *ChildHandleBuffer\r
293 );\r
294\r
295#endif\r
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