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bcecde14 | 1 | /** @file\r |
2 | \r | |
4ff5fd20 | 3 | Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>\r |
bcecde14 | 4 | \r |
5 | This program and the accompanying materials\r | |
6 | are licensed and made available under the terms and conditions\r | |
7 | of the BSD License which accompanies this distribution. The\r | |
8 | full text of the license may be found at\r | |
9 | http://opensource.org/licenses/bsd-license.php\r | |
10 | \r | |
11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
13 | \r | |
14 | **/\r | |
15 | \r | |
16 | #include "LegacyBiosInterface.h"\r | |
17 | #include <IndustryStandard/Pci30.h>\r | |
18 | \r | |
19 | #define PCI_START_ADDRESS(x) (((x) + 0x7ff) & ~0x7ff)\r | |
20 | \r | |
21 | #define MAX_BRIDGE_INDEX 0x20\r | |
22 | typedef struct {\r | |
23 | UINTN PciSegment;\r | |
24 | UINTN PciBus;\r | |
25 | UINTN PciDevice;\r | |
26 | UINTN PciFunction;\r | |
27 | UINT8 PrimaryBus;\r | |
28 | UINT8 SecondaryBus;\r | |
29 | UINT8 SubordinateBus;\r | |
30 | } BRIDGE_TABLE;\r | |
31 | \r | |
32 | #define ROM_MAX_ENTRIES 24\r | |
33 | BRIDGE_TABLE Bridges[MAX_BRIDGE_INDEX];\r | |
34 | UINTN SortedBridgeIndex[MAX_BRIDGE_INDEX];\r | |
35 | UINTN NumberOfBridges;\r | |
36 | LEGACY_PNP_EXPANSION_HEADER *mBasePnpPtr;\r | |
37 | UINT16 mBbsRomSegment;\r | |
38 | UINTN mHandleCount;\r | |
39 | EFI_HANDLE mVgaHandle;\r | |
40 | BOOLEAN mIgnoreBbsUpdateFlag;\r | |
41 | BOOLEAN mVgaInstallationInProgress = FALSE;\r | |
42 | UINT32 mRomCount = 0x00;\r | |
43 | ROM_INSTANCE_ENTRY mRomEntry[ROM_MAX_ENTRIES];\r | |
60794ee6 | 44 | EDKII_IOMMU_PROTOCOL *mIoMmu;\r |
bcecde14 | 45 | \r |
46 | /**\r | |
47 | Query shadowed legacy ROM parameters registered by RomShadow() previously.\r | |
48 | \r | |
49 | @param PciHandle PCI device whos ROM has been shadowed\r | |
50 | @param DiskStart DiskStart value from EFI_LEGACY_BIOS_PROTOCOL.InstallPciRom\r | |
51 | @param DiskEnd DiskEnd value from EFI_LEGACY_BIOS_PROTOCOL.InstallPciRom\r | |
52 | @param RomShadowAddress Address where ROM was shadowed\r | |
53 | @param ShadowedSize Runtime size of ROM\r | |
54 | \r | |
55 | @retval EFI_SUCCESS Query Logging successful.\r | |
56 | @retval EFI_NOT_FOUND No logged data found about PciHandle.\r | |
57 | \r | |
58 | **/\r | |
59 | EFI_STATUS\r | |
60 | GetShadowedRomParameters (\r | |
61 | IN EFI_HANDLE PciHandle,\r | |
62 | OUT UINT8 *DiskStart, OPTIONAL\r | |
63 | OUT UINT8 *DiskEnd, OPTIONAL\r | |
64 | OUT VOID **RomShadowAddress, OPTIONAL\r | |
65 | OUT UINTN *ShadowedSize OPTIONAL\r | |
66 | )\r | |
67 | {\r | |
68 | EFI_STATUS Status;\r | |
69 | EFI_PCI_IO_PROTOCOL *PciIo;\r | |
70 | UINTN Index;\r | |
71 | UINTN PciSegment;\r | |
72 | UINTN PciBus;\r | |
73 | UINTN PciDevice;\r | |
74 | UINTN PciFunction;\r | |
75 | \r | |
76 | //\r | |
77 | // Get the PCI I/O Protocol on PciHandle\r | |
78 | //\r | |
79 | Status = gBS->HandleProtocol (\r | |
80 | PciHandle,\r | |
81 | &gEfiPciIoProtocolGuid,\r | |
82 | (VOID **) &PciIo\r | |
83 | );\r | |
84 | if (EFI_ERROR (Status)) {\r | |
85 | return Status;\r | |
86 | }\r | |
87 | \r | |
88 | //\r | |
89 | // Get the location of the PCI device\r | |
90 | //\r | |
91 | PciIo->GetLocation (\r | |
92 | PciIo,\r | |
93 | &PciSegment,\r | |
94 | &PciBus,\r | |
95 | &PciDevice,\r | |
96 | &PciFunction\r | |
97 | );\r | |
98 | \r | |
99 | for(Index = 0; Index < mRomCount; Index++) {\r | |
100 | if ((mRomEntry[Index].PciSegment == PciSegment) &&\r | |
101 | (mRomEntry[Index].PciBus == PciBus) &&\r | |
102 | (mRomEntry[Index].PciDevice == PciDevice) &&\r | |
103 | (mRomEntry[Index].PciFunction == PciFunction)) {\r | |
104 | break;\r | |
105 | }\r | |
106 | }\r | |
107 | \r | |
108 | if (Index == mRomCount) {\r | |
109 | return EFI_NOT_FOUND;\r | |
110 | }\r | |
111 | \r | |
112 | if (DiskStart != NULL) {\r | |
113 | *DiskStart = mRomEntry[Index].DiskStart;\r | |
114 | }\r | |
115 | \r | |
116 | if (DiskEnd != NULL) {\r | |
117 | *DiskEnd = mRomEntry[Index].DiskEnd;\r | |
118 | }\r | |
119 | \r | |
120 | if (RomShadowAddress != NULL) {\r | |
121 | *RomShadowAddress = (VOID *)(UINTN)mRomEntry[Index].ShadowAddress;\r | |
122 | }\r | |
123 | \r | |
124 | if (ShadowedSize != NULL) {\r | |
125 | *ShadowedSize = mRomEntry[Index].ShadowedSize;\r | |
126 | }\r | |
127 | \r | |
128 | return EFI_SUCCESS;\r | |
129 | }\r | |
130 | \r | |
131 | /**\r | |
132 | Every legacy ROM that is shadowed by the Legacy BIOS driver will be\r | |
133 | registered into this API so that the policy code can know what has\r | |
134 | happend\r | |
135 | \r | |
136 | @param PciHandle PCI device whos ROM is being shadowed\r | |
137 | @param ShadowAddress Address that ROM was shadowed\r | |
138 | @param ShadowedSize Runtime size of ROM\r | |
139 | @param DiskStart DiskStart value from\r | |
140 | EFI_LEGACY_BIOS_PROTOCOL.InstallPciRom\r | |
141 | @param DiskEnd DiskEnd value from\r | |
142 | EFI_LEGACY_BIOS_PROTOCOL.InstallPciRom\r | |
143 | \r | |
144 | @retval EFI_SUCCESS Logging successful.\r | |
145 | @retval EFI_OUT_OF_RESOURCES No remaining room for registering another option\r | |
146 | ROM.\r | |
147 | \r | |
148 | **/\r | |
149 | EFI_STATUS\r | |
150 | RomShadow (\r | |
151 | IN EFI_HANDLE PciHandle,\r | |
152 | IN UINT32 ShadowAddress,\r | |
153 | IN UINT32 ShadowedSize, \r | |
154 | IN UINT8 DiskStart,\r | |
155 | IN UINT8 DiskEnd\r | |
156 | )\r | |
157 | {\r | |
158 | EFI_STATUS Status;\r | |
159 | EFI_PCI_IO_PROTOCOL *PciIo;\r | |
160 | \r | |
161 | //\r | |
162 | // See if there is room to register another option ROM\r | |
163 | //\r | |
164 | if (mRomCount >= ROM_MAX_ENTRIES) {\r | |
165 | return EFI_OUT_OF_RESOURCES;\r | |
166 | }\r | |
167 | //\r | |
168 | // Get the PCI I/O Protocol on PciHandle\r | |
169 | //\r | |
170 | Status = gBS->HandleProtocol (\r | |
171 | PciHandle,\r | |
172 | &gEfiPciIoProtocolGuid,\r | |
173 | (VOID **) &PciIo\r | |
174 | );\r | |
175 | if (EFI_ERROR (Status)) {\r | |
176 | return Status;\r | |
177 | }\r | |
178 | //\r | |
179 | // Get the location of the PCI device\r | |
180 | //\r | |
181 | PciIo->GetLocation (\r | |
182 | PciIo,\r | |
183 | &mRomEntry[mRomCount].PciSegment,\r | |
184 | &mRomEntry[mRomCount].PciBus,\r | |
185 | &mRomEntry[mRomCount].PciDevice,\r | |
186 | &mRomEntry[mRomCount].PciFunction\r | |
187 | );\r | |
188 | mRomEntry[mRomCount].ShadowAddress = ShadowAddress;\r | |
189 | mRomEntry[mRomCount].ShadowedSize = ShadowedSize;\r | |
190 | mRomEntry[mRomCount].DiskStart = DiskStart;\r | |
191 | mRomEntry[mRomCount].DiskEnd = DiskEnd;\r | |
192 | \r | |
193 | mRomCount++;\r | |
194 | \r | |
195 | return EFI_SUCCESS;\r | |
196 | }\r | |
197 | \r | |
198 | \r | |
199 | /**\r | |
200 | Return EFI_SUCCESS if PciHandle has had a legacy BIOS ROM shadowed. This\r | |
201 | information represents every call to RomShadow ()\r | |
202 | \r | |
203 | @param PciHandle PCI device to get status for\r | |
204 | \r | |
205 | @retval EFI_SUCCESS Legacy ROM loaded for this device\r | |
206 | @retval EFI_NOT_FOUND No Legacy ROM loaded for this device\r | |
207 | \r | |
208 | **/\r | |
209 | EFI_STATUS\r | |
210 | IsLegacyRom (\r | |
211 | IN EFI_HANDLE PciHandle\r | |
212 | )\r | |
213 | {\r | |
214 | EFI_STATUS Status;\r | |
215 | EFI_PCI_IO_PROTOCOL *PciIo;\r | |
216 | UINTN Index;\r | |
217 | UINTN Segment;\r | |
218 | UINTN Bus;\r | |
219 | UINTN Device;\r | |
220 | UINTN Function;\r | |
221 | \r | |
222 | //\r | |
223 | // Get the PCI I/O Protocol on PciHandle\r | |
224 | //\r | |
225 | Status = gBS->HandleProtocol (\r | |
226 | PciHandle,\r | |
227 | &gEfiPciIoProtocolGuid,\r | |
228 | (VOID **) &PciIo\r | |
229 | );\r | |
230 | if (EFI_ERROR (Status)) {\r | |
231 | return Status;\r | |
232 | }\r | |
233 | //\r | |
234 | // Get the location of the PCI device\r | |
235 | //\r | |
236 | PciIo->GetLocation (\r | |
237 | PciIo,\r | |
238 | &Segment,\r | |
239 | &Bus,\r | |
240 | &Device,\r | |
241 | &Function\r | |
242 | );\r | |
243 | \r | |
244 | //\r | |
245 | // See if the option ROM from PciHandle has been previously posted\r | |
246 | //\r | |
247 | for (Index = 0; Index < mRomCount; Index++) {\r | |
248 | if (mRomEntry[Index].PciSegment == Segment &&\r | |
249 | mRomEntry[Index].PciBus == Bus &&\r | |
250 | mRomEntry[Index].PciDevice == Device &&\r | |
251 | mRomEntry[Index].PciFunction == Function\r | |
252 | ) {\r | |
253 | return EFI_SUCCESS;\r | |
254 | }\r | |
255 | }\r | |
256 | \r | |
257 | return EFI_NOT_FOUND;\r | |
258 | }\r | |
259 | \r | |
260 | /**\r | |
261 | Find the PC-AT ROM Image in the raw PCI Option ROM. Also return the \r | |
262 | related information from the header.\r | |
263 | \r | |
264 | @param Csm16Revision The PCI interface version of underlying CSM16\r | |
265 | @param VendorId Vendor ID of the PCI device\r | |
266 | @param DeviceId Device ID of the PCI device\r | |
267 | @param Rom On input pointing to beginning of the raw PCI OpROM\r | |
268 | On output pointing to the first legacy PCI OpROM\r | |
269 | @param ImageSize On input is the size of Raw PCI Rom\r | |
270 | On output is the size of the first legacy PCI ROM\r | |
271 | @param MaxRuntimeImageLength The max runtime image length only valid if OpRomRevision >= 3\r | |
272 | @param OpRomRevision Revision of the PCI Rom\r | |
273 | @param ConfigUtilityCodeHeader Pointer to Configuration Utility Code Header\r | |
274 | \r | |
275 | @retval EFI_SUCCESS Successfully find the legacy PCI ROM\r | |
276 | @retval EFI_NOT_FOUND Failed to find the legacy PCI ROM\r | |
277 | \r | |
278 | **/\r | |
279 | EFI_STATUS\r | |
280 | GetPciLegacyRom (\r | |
281 | IN UINT16 Csm16Revision,\r | |
282 | IN UINT16 VendorId,\r | |
283 | IN UINT16 DeviceId,\r | |
284 | IN OUT VOID **Rom,\r | |
285 | IN OUT UINTN *ImageSize,\r | |
286 | OUT UINTN *MaxRuntimeImageLength, OPTIONAL\r | |
287 | OUT UINT8 *OpRomRevision, OPTIONAL\r | |
288 | OUT VOID **ConfigUtilityCodeHeader OPTIONAL\r | |
289 | )\r | |
290 | {\r | |
291 | BOOLEAN Match;\r | |
292 | UINT16 *DeviceIdList;\r | |
293 | EFI_PCI_ROM_HEADER RomHeader;\r | |
294 | PCI_3_0_DATA_STRUCTURE *Pcir;\r | |
295 | VOID *BackupImage;\r | |
296 | VOID *BestImage;\r | |
297 | \r | |
298 | \r | |
299 | if (*ImageSize < sizeof (EFI_PCI_ROM_HEADER)) {\r | |
300 | return EFI_NOT_FOUND;\r | |
301 | }\r | |
302 | \r | |
303 | BestImage = NULL;\r | |
304 | BackupImage = NULL;\r | |
305 | RomHeader.Raw = *Rom;\r | |
306 | while (RomHeader.Generic->Signature == PCI_EXPANSION_ROM_HEADER_SIGNATURE) {\r | |
94020bb4 | 307 | if (RomHeader.Generic->PcirOffset == 0 ||\r |
308 | (RomHeader.Generic->PcirOffset & 3) !=0 ||\r | |
309 | *ImageSize < RomHeader.Raw - (UINT8 *) *Rom + RomHeader.Generic->PcirOffset + sizeof (PCI_DATA_STRUCTURE)) {\r | |
310 | break;\r | |
bcecde14 | 311 | }\r |
312 | \r | |
313 | Pcir = (PCI_3_0_DATA_STRUCTURE *) (RomHeader.Raw + RomHeader.Generic->PcirOffset);\r | |
94020bb4 | 314 | //\r |
315 | // Check signature in the PCI Data Structure.\r | |
316 | //\r | |
317 | if (Pcir->Signature != PCI_DATA_STRUCTURE_SIGNATURE) {\r | |
318 | break;\r | |
319 | }\r | |
bcecde14 | 320 | \r |
4ff5fd20 | 321 | if (((UINTN)RomHeader.Raw - (UINTN)*Rom) + Pcir->ImageLength * 512 > *ImageSize) {\r |
94020bb4 | 322 | break;\r |
323 | }\r | |
324 | \r | |
bcecde14 | 325 | if (Pcir->CodeType == PCI_CODE_TYPE_PCAT_IMAGE) {\r |
326 | Match = FALSE;\r | |
327 | if (Pcir->VendorId == VendorId) {\r | |
328 | if (Pcir->DeviceId == DeviceId) {\r | |
329 | Match = TRUE;\r | |
330 | } else if ((Pcir->Revision >= 3) && (Pcir->DeviceListOffset != 0)) {\r | |
331 | DeviceIdList = (UINT16 *)(((UINT8 *) Pcir) + Pcir->DeviceListOffset);\r | |
332 | //\r | |
333 | // Checking the device list\r | |
334 | //\r | |
335 | while (*DeviceIdList != 0) {\r | |
336 | if (*DeviceIdList == DeviceId) {\r | |
337 | Match = TRUE;\r | |
338 | break;\r | |
339 | }\r | |
340 | DeviceIdList ++;\r | |
341 | }\r | |
342 | }\r | |
343 | }\r | |
344 | \r | |
345 | if (Match) {\r | |
346 | if (Csm16Revision >= 0x0300) {\r | |
347 | //\r | |
348 | // Case 1: CSM16 3.0\r | |
349 | //\r | |
350 | if (Pcir->Revision >= 3) {\r | |
351 | //\r | |
352 | // case 1.1: meets OpRom 3.0\r | |
353 | // Perfect!!!\r | |
354 | //\r | |
355 | BestImage = RomHeader.Raw;\r | |
356 | break;\r | |
357 | } else {\r | |
358 | //\r | |
359 | // case 1.2: meets OpRom 2.x\r | |
360 | // Store it and try to find the OpRom 3.0\r | |
361 | //\r | |
362 | BackupImage = RomHeader.Raw;\r | |
363 | }\r | |
364 | } else {\r | |
365 | //\r | |
366 | // Case 2: CSM16 2.x\r | |
367 | //\r | |
368 | if (Pcir->Revision >= 3) {\r | |
369 | //\r | |
370 | // case 2.1: meets OpRom 3.0\r | |
371 | // Store it and try to find the OpRom 2.x\r | |
372 | //\r | |
373 | BackupImage = RomHeader.Raw;\r | |
374 | } else {\r | |
375 | //\r | |
376 | // case 2.2: meets OpRom 2.x\r | |
377 | // Perfect!!!\r | |
378 | //\r | |
379 | BestImage = RomHeader.Raw;\r | |
380 | break;\r | |
381 | }\r | |
382 | }\r | |
383 | } else {\r | |
384 | DEBUG ((EFI_D_ERROR, "GetPciLegacyRom - OpRom not match (%04x-%04x)\n", (UINTN)VendorId, (UINTN)DeviceId));\r | |
385 | }\r | |
386 | }\r | |
387 | \r | |
388 | if ((Pcir->Indicator & 0x80) == 0x80) {\r | |
389 | break;\r | |
390 | } else {\r | |
391 | RomHeader.Raw += 512 * Pcir->ImageLength;\r | |
392 | }\r | |
393 | }\r | |
394 | \r | |
395 | if (BestImage == NULL) {\r | |
396 | if (BackupImage == NULL) {\r | |
397 | return EFI_NOT_FOUND;\r | |
398 | }\r | |
399 | //\r | |
400 | // The versions of CSM16 and OpRom don't match exactly\r | |
401 | //\r | |
402 | BestImage = BackupImage;\r | |
403 | }\r | |
404 | RomHeader.Raw = BestImage;\r | |
405 | Pcir = (PCI_3_0_DATA_STRUCTURE *) (RomHeader.Raw + RomHeader.Generic->PcirOffset);\r | |
406 | *Rom = BestImage;\r | |
407 | *ImageSize = Pcir->ImageLength * 512;\r | |
408 | \r | |
409 | if (MaxRuntimeImageLength != NULL) {\r | |
410 | if (Pcir->Revision < 3) {\r | |
411 | *MaxRuntimeImageLength = 0;\r | |
412 | } else {\r | |
413 | *MaxRuntimeImageLength = Pcir->MaxRuntimeImageLength * 512;\r | |
414 | }\r | |
415 | }\r | |
416 | \r | |
417 | if (OpRomRevision != NULL) {\r | |
418 | // \r | |
419 | // Optional return PCI Data Structure revision\r | |
420 | //\r | |
421 | if (Pcir->Length >= 0x1C) {\r | |
422 | *OpRomRevision = Pcir->Revision;\r | |
423 | } else {\r | |
424 | *OpRomRevision = 0;\r | |
425 | }\r | |
426 | }\r | |
427 | \r | |
428 | if (ConfigUtilityCodeHeader != NULL) {\r | |
429 | //\r | |
430 | // Optional return ConfigUtilityCodeHeaderOffset supported by the PC-AT ROM\r | |
431 | //\r | |
432 | if ((Pcir->Revision < 3) || (Pcir->ConfigUtilityCodeHeaderOffset == 0)) {\r | |
433 | *ConfigUtilityCodeHeader = NULL;\r | |
434 | } else {\r | |
435 | *ConfigUtilityCodeHeader = RomHeader.Raw + Pcir->ConfigUtilityCodeHeaderOffset;\r | |
436 | }\r | |
437 | }\r | |
438 | \r | |
439 | return EFI_SUCCESS;\r | |
440 | }\r | |
441 | \r | |
442 | /**\r | |
443 | Build a table of bridge info for PIRQ translation.\r | |
444 | \r | |
445 | @param RoutingTable RoutingTable obtained from Platform.\r | |
446 | @param RoutingTableEntries Number of RoutingTable entries.\r | |
447 | \r | |
448 | @retval EFI_SUCCESS New Subordinate bus.\r | |
449 | @retval EFI_NOT_FOUND No more Subordinate busses.\r | |
450 | \r | |
451 | **/\r | |
452 | EFI_STATUS\r | |
453 | CreateBridgeTable (\r | |
454 | IN EFI_LEGACY_IRQ_ROUTING_ENTRY *RoutingTable,\r | |
455 | IN UINTN RoutingTableEntries\r | |
456 | )\r | |
457 | {\r | |
458 | EFI_STATUS Status;\r | |
459 | UINTN HandleCount;\r | |
460 | EFI_HANDLE *HandleBuffer;\r | |
461 | UINTN BridgeIndex;\r | |
462 | UINTN Index;\r | |
463 | UINTN Index1;\r | |
464 | EFI_PCI_IO_PROTOCOL *PciIo;\r | |
465 | PCI_TYPE01 PciConfigHeader;\r | |
466 | BRIDGE_TABLE SlotBridges[MAX_BRIDGE_INDEX];\r | |
467 | UINTN SlotBridgeIndex;\r | |
468 | \r | |
469 | BridgeIndex = 0x00;\r | |
470 | SlotBridgeIndex = 0x00;\r | |
471 | \r | |
472 | //\r | |
473 | // Assumption is table is built from low bus to high bus numbers.\r | |
474 | //\r | |
475 | Status = gBS->LocateHandleBuffer (\r | |
476 | ByProtocol,\r | |
477 | &gEfiPciIoProtocolGuid,\r | |
478 | NULL,\r | |
479 | &HandleCount,\r | |
480 | &HandleBuffer\r | |
481 | );\r | |
482 | if (EFI_ERROR (Status)) {\r | |
483 | return EFI_NOT_FOUND;\r | |
484 | }\r | |
485 | for (Index = 0; Index < HandleCount; Index++) {\r | |
486 | Status = gBS->HandleProtocol (\r | |
487 | HandleBuffer[Index],\r | |
488 | &gEfiPciIoProtocolGuid,\r | |
489 | (VOID **) &PciIo\r | |
490 | );\r | |
491 | if (EFI_ERROR (Status)) {\r | |
492 | continue;\r | |
493 | }\r | |
494 | \r | |
495 | PciIo->Pci.Read (\r | |
496 | PciIo,\r | |
497 | EfiPciIoWidthUint32,\r | |
498 | 0,\r | |
499 | sizeof (PciConfigHeader) / sizeof (UINT32),\r | |
500 | &PciConfigHeader\r | |
501 | );\r | |
502 | \r | |
503 | if (IS_PCI_P2P (&PciConfigHeader) && (BridgeIndex < MAX_BRIDGE_INDEX)) {\r | |
504 | PciIo->GetLocation (\r | |
505 | PciIo,\r | |
506 | &Bridges[BridgeIndex].PciSegment,\r | |
507 | &Bridges[BridgeIndex].PciBus,\r | |
508 | &Bridges[BridgeIndex].PciDevice,\r | |
509 | &Bridges[BridgeIndex].PciFunction\r | |
510 | );\r | |
511 | \r | |
512 | Bridges[BridgeIndex].PrimaryBus = PciConfigHeader.Bridge.PrimaryBus;\r | |
513 | \r | |
514 | Bridges[BridgeIndex].SecondaryBus = PciConfigHeader.Bridge.SecondaryBus;\r | |
515 | \r | |
516 | Bridges[BridgeIndex].SubordinateBus = PciConfigHeader.Bridge.SubordinateBus;\r | |
517 | \r | |
518 | for (Index1 = 0; Index1 < RoutingTableEntries; Index1++){\r | |
519 | //\r | |
520 | // Test whether we have found the Bridge in the slot, must be the one that directly interfaced to the board\r | |
521 | // Once we find one, store it in the SlotBridges[]\r | |
522 | //\r | |
523 | if ((RoutingTable[Index1].Slot != 0) && (Bridges[BridgeIndex].PrimaryBus == RoutingTable[Index1].Bus)\r | |
524 | && ((Bridges[BridgeIndex].PciDevice << 3) == RoutingTable[Index1].Device)) {\r | |
525 | CopyMem (&SlotBridges[SlotBridgeIndex], &Bridges[BridgeIndex], sizeof (BRIDGE_TABLE));\r | |
526 | SlotBridgeIndex++;\r | |
527 | \r | |
528 | break;\r | |
529 | }\r | |
530 | }\r | |
531 | \r | |
532 | ++BridgeIndex;\r | |
533 | }\r | |
534 | }\r | |
535 | \r | |
536 | //\r | |
537 | // Pack up Bridges by removing those useless ones\r | |
538 | //\r | |
539 | for (Index = 0; Index < BridgeIndex;){\r | |
540 | for (Index1 = 0; Index1 < SlotBridgeIndex; Index1++) {\r | |
541 | if (((Bridges[Index].PciBus == SlotBridges[Index1].PrimaryBus) && (Bridges[Index].PciDevice == SlotBridges[Index1].PciDevice)) ||\r | |
542 | ((Bridges[Index].PciBus >= SlotBridges[Index1].SecondaryBus) && (Bridges[Index].PciBus <= SlotBridges[Index1].SubordinateBus))) {\r | |
543 | //\r | |
544 | // We have found one that meets our criteria\r | |
545 | //\r | |
546 | Index++;\r | |
547 | break;\r | |
548 | }\r | |
549 | }\r | |
550 | \r | |
551 | //\r | |
552 | // This one doesn't meet criteria, pack it\r | |
553 | //\r | |
554 | if (Index1 >= SlotBridgeIndex) {\r | |
555 | for (Index1 = Index; BridgeIndex > 1 && Index1 < BridgeIndex - 1 ; Index1++) {\r | |
556 | CopyMem (&Bridges[Index1], &Bridges[Index1 + 1], sizeof (BRIDGE_TABLE));\r | |
557 | }\r | |
558 | \r | |
559 | BridgeIndex--;\r | |
560 | }\r | |
561 | }\r | |
562 | \r | |
563 | NumberOfBridges = BridgeIndex;\r | |
564 | \r | |
565 | //\r | |
566 | // Sort bridges low to high by Secondary bus followed by subordinate bus\r | |
567 | //\r | |
568 | if (NumberOfBridges > 1) {\r | |
569 | Index = 0;\r | |
570 | do {\r | |
571 | SortedBridgeIndex[Index] = Index;\r | |
572 | ++Index;\r | |
573 | } while (Index < NumberOfBridges);\r | |
574 | \r | |
575 | for (Index = 0; Index < NumberOfBridges - 1; Index++) {\r | |
576 | for (Index1 = Index + 1; Index1 < NumberOfBridges; Index1++) {\r | |
577 | if (Bridges[Index].SecondaryBus > Bridges[Index1].SecondaryBus) {\r | |
578 | SortedBridgeIndex[Index] = Index1;\r | |
579 | SortedBridgeIndex[Index1] = Index;\r | |
580 | }\r | |
581 | \r | |
582 | if ((Bridges[Index].SecondaryBus == Bridges[Index1].SecondaryBus) &&\r | |
583 | (Bridges[Index].SubordinateBus > Bridges[Index1].SubordinateBus)\r | |
584 | ) {\r | |
585 | SortedBridgeIndex[Index] = Index1;\r | |
586 | SortedBridgeIndex[Index1] = Index;\r | |
587 | }\r | |
588 | }\r | |
589 | }\r | |
590 | }\r | |
591 | FreePool (HandleBuffer);\r | |
592 | return EFI_SUCCESS;\r | |
593 | }\r | |
594 | \r | |
595 | \r | |
596 | /**\r | |
597 | Find base Bridge for device.\r | |
598 | \r | |
599 | @param Private Legacy BIOS Instance data\r | |
600 | @param PciBus Input = Bus of device.\r | |
601 | @param PciDevice Input = Device.\r | |
602 | @param RoutingTable The platform specific routing table\r | |
603 | @param RoutingTableEntries Number of entries in table\r | |
604 | \r | |
605 | @retval EFI_SUCCESS At base bus.\r | |
606 | @retval EFI_NOT_FOUND Behind a bridge.\r | |
607 | \r | |
608 | **/\r | |
609 | EFI_STATUS\r | |
610 | GetBaseBus (\r | |
611 | IN LEGACY_BIOS_INSTANCE *Private,\r | |
612 | IN UINTN PciBus,\r | |
613 | IN UINTN PciDevice,\r | |
614 | IN EFI_LEGACY_IRQ_ROUTING_ENTRY *RoutingTable,\r | |
615 | IN UINTN RoutingTableEntries\r | |
616 | )\r | |
617 | {\r | |
618 | UINTN Index;\r | |
619 | for (Index = 0; Index < RoutingTableEntries; Index++) {\r | |
620 | if ((RoutingTable[Index].Bus == PciBus) && (RoutingTable[Index].Device == (PciDevice << 3))) {\r | |
621 | return EFI_SUCCESS;\r | |
622 | }\r | |
623 | }\r | |
624 | \r | |
625 | return EFI_NOT_FOUND;\r | |
626 | }\r | |
627 | \r | |
628 | /**\r | |
629 | Translate PIRQ through busses\r | |
630 | \r | |
631 | @param Private Legacy BIOS Instance data\r | |
632 | @param PciBus Input = Bus of device. Output = Translated Bus\r | |
633 | @param PciDevice Input = Device. Output = Translated Device\r | |
634 | @param PciFunction Input = Function. Output = Translated Function\r | |
635 | @param PirqIndex Input = Original PIRQ index. If single function\r | |
636 | device then 0, otherwise 0-3.\r | |
637 | Output = Translated Index\r | |
638 | \r | |
639 | @retval EFI_SUCCESS Pirq successfully translated.\r | |
640 | @retval EFI_NOT_FOUND The device is not behind any known bridge.\r | |
641 | \r | |
642 | **/\r | |
643 | EFI_STATUS\r | |
644 | TranslateBusPirq (\r | |
645 | IN LEGACY_BIOS_INSTANCE *Private,\r | |
646 | IN OUT UINTN *PciBus,\r | |
647 | IN OUT UINTN *PciDevice,\r | |
648 | IN OUT UINTN *PciFunction,\r | |
649 | IN OUT UINT8 *PirqIndex\r | |
650 | )\r | |
651 | {\r | |
652 | /*\r | |
653 | This routine traverses the PCI busses from base slot\r | |
654 | and translates the PIRQ register to the appropriate one.\r | |
655 | \r | |
656 | Example:\r | |
657 | \r | |
658 | Bus 0, Device 1 is PCI-PCI bridge that all PCI slots reside on.\r | |
659 | Primary bus# = 0\r | |
660 | Secondary bus # = 1\r | |
661 | Subordinate bus # is highest bus # behind this bus\r | |
662 | Bus 1, Device 0 is Slot 0 and is not a bridge.\r | |
663 | Bus 1, Device 1 is Slot 1 and is a bridge.\r | |
664 | Slot PIRQ routing is A,B,C,D.\r | |
665 | Primary bus # = 1\r | |
666 | Secondary bus # = 2\r | |
667 | Subordinate bus # = 5\r | |
668 | Bus 2, Device 6 is a bridge. It has no bridges behind it.\r | |
669 | Primary bus # = 2\r | |
670 | Secondary bus # = 3\r | |
671 | Subordinate bus # = 3\r | |
672 | Bridge PIRQ routing is C,D,A,B\r | |
673 | Bus 2, Device 7 is a bridge. It has 1 bridge behind it.\r | |
674 | Primary bus # = 2\r | |
675 | Secondary bus = 4 Device 6 takes bus 2.\r | |
676 | Subordinate bus = 5.\r | |
677 | Bridge PIRQ routing is D,A,B,C\r | |
678 | Bus 4, Device 2 is a bridge. It has no bridges behind it.\r | |
679 | Primary bus # = 4\r | |
680 | Secondary bus # = 5\r | |
681 | Subordinate bus = 5\r | |
682 | Bridge PIRQ routing is B,C,D,A\r | |
683 | Bus 5, Device 1 is to be programmed.\r | |
684 | Device PIRQ routing is C,D,A,B\r | |
685 | \r | |
686 | \r | |
687 | Search busses starting from slot bus for final bus >= Secondary bus and\r | |
688 | final bus <= Suborninate bus. Assumption is bus entries increase in bus\r | |
689 | number.\r | |
690 | Starting PIRQ is A,B,C,D.\r | |
691 | Bus 2, Device 7 satisfies search criteria. Rotate (A,B,C,D) left by device\r | |
692 | 7 modulo 4 giving (D,A,B,C).\r | |
693 | Bus 4, Device 2 satisfies search criteria. Rotate (D,A,B,C) left by 2 giving\r | |
694 | (B,C,D,A).\r | |
695 | No other busses match criteria. Device to be programmed is Bus 5, Device 1.\r | |
696 | Rotate (B,C,D,A) by 1 giving C,D,A,B. Translated PIRQ is C.\r | |
697 | \r | |
698 | */\r | |
699 | UINTN LocalBus;\r | |
700 | UINTN LocalDevice;\r | |
701 | UINTN BaseBus;\r | |
702 | UINTN BaseDevice;\r | |
703 | UINTN BaseFunction;\r | |
704 | UINT8 LocalPirqIndex;\r | |
705 | BOOLEAN BaseIndexFlag;\r | |
706 | UINTN BridgeIndex;\r | |
707 | UINTN SBridgeIndex;\r | |
708 | BaseIndexFlag = FALSE;\r | |
709 | BridgeIndex = 0x00;\r | |
710 | \r | |
711 | LocalPirqIndex = *PirqIndex;\r | |
712 | LocalBus = *PciBus;\r | |
713 | LocalDevice = *PciDevice;\r | |
714 | BaseBus = *PciBus;\r | |
715 | BaseDevice = *PciDevice;\r | |
716 | BaseFunction = *PciFunction;\r | |
717 | \r | |
718 | //\r | |
719 | // LocalPirqIndex list PIRQs in rotated fashion\r | |
720 | // = 0 A,B,C,D\r | |
721 | // = 1 B,C,D,A\r | |
722 | // = 2 C,D,A,B\r | |
723 | // = 3 D,A,B,C\r | |
724 | //\r | |
725 | \r | |
726 | for (BridgeIndex = 0; BridgeIndex < NumberOfBridges; BridgeIndex++) {\r | |
727 | SBridgeIndex = SortedBridgeIndex[BridgeIndex];\r | |
728 | //\r | |
729 | // Check if device behind this bridge\r | |
730 | //\r | |
731 | if ((LocalBus >= Bridges[SBridgeIndex].SecondaryBus) && (LocalBus <= Bridges[SBridgeIndex].SubordinateBus)) {\r | |
732 | //\r | |
733 | // If BaseIndexFlag = FALSE then have found base bridge, i.e\r | |
734 | // bridge in slot. Save info for use by IRQ routing table.\r | |
735 | //\r | |
736 | if (!BaseIndexFlag) {\r | |
737 | BaseBus = Bridges[SBridgeIndex].PciBus;\r | |
738 | BaseDevice = Bridges[SBridgeIndex].PciDevice;\r | |
739 | BaseFunction = Bridges[SBridgeIndex].PciFunction;\r | |
740 | BaseIndexFlag = TRUE;\r | |
741 | } else {\r | |
742 | LocalPirqIndex = (UINT8) ((LocalPirqIndex + (UINT8)Bridges[SBridgeIndex].PciDevice)%4);\r | |
743 | }\r | |
744 | \r | |
745 | //\r | |
746 | // Check if at device. If not get new PCI location & PIRQ\r | |
747 | //\r | |
748 | if (Bridges[SBridgeIndex].SecondaryBus == (UINT8) LocalBus) {\r | |
749 | //\r | |
750 | // Translate PIRQ\r | |
751 | //\r | |
752 | LocalPirqIndex = (UINT8) ((LocalPirqIndex + (UINT8) (LocalDevice)) % 4);\r | |
753 | break;\r | |
754 | }\r | |
755 | }\r | |
756 | }\r | |
757 | \r | |
758 | //\r | |
759 | // In case we fail to find the Bridge just above us, this is some potential error and we want to warn the user\r | |
760 | //\r | |
761 | if(BridgeIndex >= NumberOfBridges){\r | |
762 | DEBUG ((EFI_D_ERROR, "Cannot Find IRQ Routing for Bus %d, Device %d, Function %d\n", *PciBus, *PciDevice, *PciFunction));\r | |
763 | }\r | |
764 | \r | |
765 | *PirqIndex = LocalPirqIndex;\r | |
766 | *PciBus = BaseBus;\r | |
767 | *PciDevice = BaseDevice;\r | |
768 | *PciFunction = BaseFunction;\r | |
769 | \r | |
770 | return EFI_SUCCESS;\r | |
771 | }\r | |
772 | \r | |
773 | \r | |
774 | /**\r | |
775 | Copy the $PIR table as required.\r | |
776 | \r | |
777 | @param Private Legacy BIOS Instance data\r | |
778 | @param RoutingTable Pointer to IRQ routing table\r | |
779 | @param RoutingTableEntries IRQ routing table entries\r | |
780 | @param PirqTable Pointer to $PIR table\r | |
781 | @param PirqTableSize Length of table\r | |
782 | \r | |
783 | **/\r | |
784 | VOID\r | |
785 | CopyPirqTable (\r | |
786 | IN LEGACY_BIOS_INSTANCE *Private,\r | |
787 | IN EFI_LEGACY_IRQ_ROUTING_ENTRY *RoutingTable,\r | |
788 | IN UINTN RoutingTableEntries,\r | |
789 | IN EFI_LEGACY_PIRQ_TABLE_HEADER *PirqTable,\r | |
790 | IN UINTN PirqTableSize\r | |
791 | )\r | |
792 | {\r | |
793 | EFI_IA32_REGISTER_SET Regs;\r | |
794 | UINT32 Granularity;\r | |
795 | \r | |
796 | //\r | |
797 | // Copy $PIR table, if it exists.\r | |
798 | //\r | |
799 | if (PirqTable != NULL) {\r | |
800 | Private->LegacyRegion->UnLock (\r | |
801 | Private->LegacyRegion,\r | |
802 | 0xE0000,\r | |
803 | 0x20000,\r | |
804 | &Granularity\r | |
805 | );\r | |
806 | \r | |
807 | Private->InternalIrqRoutingTable = RoutingTable;\r | |
808 | Private->NumberIrqRoutingEntries = (UINT16) (RoutingTableEntries);\r | |
809 | ZeroMem (&Regs, sizeof (EFI_IA32_REGISTER_SET));\r | |
810 | \r | |
811 | Regs.X.AX = Legacy16GetTableAddress;\r | |
812 | Regs.X.CX = (UINT16) PirqTableSize;\r | |
813 | //\r | |
814 | // Allocate at F segment according to PCI IRQ Routing Table Specification\r | |
815 | //\r | |
816 | Regs.X.BX = (UINT16) 0x1;\r | |
817 | //\r | |
818 | // 16-byte boundary alignment requirement according to \r | |
819 | // PCI IRQ Routing Table Specification\r | |
820 | //\r | |
821 | Regs.X.DX = 0x10;\r | |
822 | Private->LegacyBios.FarCall86 (\r | |
823 | &Private->LegacyBios,\r | |
824 | Private->Legacy16CallSegment,\r | |
825 | Private->Legacy16CallOffset,\r | |
826 | &Regs,\r | |
827 | NULL,\r | |
828 | 0\r | |
829 | );\r | |
830 | \r | |
831 | Private->Legacy16Table->IrqRoutingTablePointer = (UINT32) (Regs.X.DS * 16 + Regs.X.BX);\r | |
832 | if (Regs.X.AX != 0) {\r | |
833 | DEBUG ((EFI_D_ERROR, "PIRQ table length insufficient - %x\n", PirqTableSize));\r | |
834 | } else {\r | |
835 | DEBUG ((EFI_D_INFO, "PIRQ table in legacy region - %x\n", Private->Legacy16Table->IrqRoutingTablePointer)); \r | |
836 | Private->Legacy16Table->IrqRoutingTableLength = (UINT32)PirqTableSize;\r | |
837 | CopyMem (\r | |
838 | (VOID *) (UINTN)Private->Legacy16Table->IrqRoutingTablePointer,\r | |
839 | PirqTable,\r | |
840 | PirqTableSize\r | |
841 | );\r | |
842 | }\r | |
843 | \r | |
844 | Private->Cpu->FlushDataCache (Private->Cpu, 0xE0000, 0x20000, EfiCpuFlushTypeWriteBackInvalidate);\r | |
845 | Private->LegacyRegion->Lock (\r | |
846 | Private->LegacyRegion,\r | |
847 | 0xE0000,\r | |
848 | 0x20000,\r | |
849 | &Granularity\r | |
850 | );\r | |
851 | }\r | |
852 | \r | |
853 | Private->PciInterruptLine = TRUE;\r | |
854 | mHandleCount = 0;\r | |
855 | }\r | |
856 | \r | |
857 | /**\r | |
858 | Dump EFI_LEGACY_INSTALL_PCI_HANDLER structure information.\r | |
859 | \r | |
860 | @param PciHandle The pointer to EFI_LEGACY_INSTALL_PCI_HANDLER structure\r | |
861 | \r | |
862 | **/\r | |
863 | VOID\r | |
864 | DumpPciHandle (\r | |
865 | IN EFI_LEGACY_INSTALL_PCI_HANDLER *PciHandle\r | |
866 | )\r | |
867 | {\r | |
868 | DEBUG ((EFI_D_INFO, "PciBus - %02x\n", (UINTN)PciHandle->PciBus));\r | |
869 | DEBUG ((EFI_D_INFO, "PciDeviceFun - %02x\n", (UINTN)PciHandle->PciDeviceFun));\r | |
870 | DEBUG ((EFI_D_INFO, "PciSegment - %02x\n", (UINTN)PciHandle->PciSegment));\r | |
871 | DEBUG ((EFI_D_INFO, "PciClass - %02x\n", (UINTN)PciHandle->PciClass));\r | |
872 | DEBUG ((EFI_D_INFO, "PciSubclass - %02x\n", (UINTN)PciHandle->PciSubclass));\r | |
873 | DEBUG ((EFI_D_INFO, "PciInterface - %02x\n", (UINTN)PciHandle->PciInterface));\r | |
874 | \r | |
875 | DEBUG ((EFI_D_INFO, "PrimaryIrq - %02x\n", (UINTN)PciHandle->PrimaryIrq));\r | |
876 | DEBUG ((EFI_D_INFO, "PrimaryReserved - %02x\n", (UINTN)PciHandle->PrimaryReserved));\r | |
877 | DEBUG ((EFI_D_INFO, "PrimaryControl - %04x\n", (UINTN)PciHandle->PrimaryControl));\r | |
878 | DEBUG ((EFI_D_INFO, "PrimaryBase - %04x\n", (UINTN)PciHandle->PrimaryBase));\r | |
879 | DEBUG ((EFI_D_INFO, "PrimaryBusMaster - %04x\n", (UINTN)PciHandle->PrimaryBusMaster));\r | |
880 | \r | |
881 | DEBUG ((EFI_D_INFO, "SecondaryIrq - %02x\n", (UINTN)PciHandle->SecondaryIrq));\r | |
882 | DEBUG ((EFI_D_INFO, "SecondaryReserved - %02x\n", (UINTN)PciHandle->SecondaryReserved));\r | |
883 | DEBUG ((EFI_D_INFO, "SecondaryControl - %04x\n", (UINTN)PciHandle->SecondaryControl));\r | |
884 | DEBUG ((EFI_D_INFO, "SecondaryBase - %04x\n", (UINTN)PciHandle->SecondaryBase));\r | |
885 | DEBUG ((EFI_D_INFO, "SecondaryBusMaster - %04x\n", (UINTN)PciHandle->SecondaryBusMaster));\r | |
886 | return;\r | |
887 | }\r | |
888 | \r | |
889 | /**\r | |
890 | Copy the $PIR table as required.\r | |
891 | \r | |
892 | @param Private Legacy BIOS Instance data\r | |
893 | @param PciIo Pointer to PCI_IO protocol\r | |
894 | @param PciIrq Pci IRQ number\r | |
895 | @param PciConfigHeader Type00 Pci configuration header\r | |
896 | \r | |
897 | **/\r | |
898 | VOID\r | |
899 | InstallLegacyIrqHandler (\r | |
900 | IN LEGACY_BIOS_INSTANCE *Private,\r | |
901 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
902 | IN UINT8 PciIrq,\r | |
903 | IN PCI_TYPE00 *PciConfigHeader\r | |
904 | )\r | |
905 | {\r | |
906 | EFI_IA32_REGISTER_SET Regs;\r | |
907 | UINT16 LegMask;\r | |
908 | UINTN PciSegment;\r | |
909 | UINTN PciBus;\r | |
910 | UINTN PciDevice;\r | |
911 | UINTN PciFunction;\r | |
912 | EFI_LEGACY_8259_PROTOCOL *Legacy8259;\r | |
913 | UINT16 PrimaryMaster;\r | |
914 | UINT16 SecondaryMaster;\r | |
915 | UINTN TempData;\r | |
916 | UINTN RegisterAddress;\r | |
917 | UINT32 Granularity;\r | |
918 | \r | |
919 | PrimaryMaster = 0;\r | |
920 | SecondaryMaster = 0;\r | |
921 | Legacy8259 = Private->Legacy8259;\r | |
922 | //\r | |
923 | // Disable interrupt in PIC, in case shared, to prevent an\r | |
924 | // interrupt from occuring.\r | |
925 | //\r | |
926 | Legacy8259->GetMask (\r | |
927 | Legacy8259,\r | |
928 | &LegMask,\r | |
929 | NULL,\r | |
930 | NULL,\r | |
931 | NULL\r | |
932 | );\r | |
933 | \r | |
934 | LegMask = (UINT16) (LegMask | (UINT16) (1 << PciIrq));\r | |
935 | \r | |
936 | Legacy8259->SetMask (\r | |
937 | Legacy8259,\r | |
938 | &LegMask,\r | |
939 | NULL,\r | |
940 | NULL,\r | |
941 | NULL\r | |
942 | );\r | |
943 | \r | |
944 | PciIo->GetLocation (\r | |
945 | PciIo,\r | |
946 | &PciSegment,\r | |
947 | &PciBus,\r | |
948 | &PciDevice,\r | |
949 | &PciFunction\r | |
950 | );\r | |
951 | Private->IntThunk->PciHandler.PciBus = (UINT8) PciBus;\r | |
952 | Private->IntThunk->PciHandler.PciDeviceFun = (UINT8) ((PciDevice << 3) + PciFunction);\r | |
953 | Private->IntThunk->PciHandler.PciSegment = (UINT8) PciSegment;\r | |
954 | Private->IntThunk->PciHandler.PciClass = PciConfigHeader->Hdr.ClassCode[2];\r | |
955 | Private->IntThunk->PciHandler.PciSubclass = PciConfigHeader->Hdr.ClassCode[1];\r | |
956 | Private->IntThunk->PciHandler.PciInterface = PciConfigHeader->Hdr.ClassCode[0];\r | |
957 | \r | |
958 | //\r | |
959 | // Use native mode base address registers in two cases:\r | |
960 | // 1. Programming Interface (PI) register indicates Primary Controller is\r | |
961 | // in native mode OR\r | |
962 | // 2. PCI device Sub Class Code is not IDE\r | |
963 | //\r | |
964 | Private->IntThunk->PciHandler.PrimaryBusMaster = (UINT16)(PciConfigHeader->Device.Bar[4] & 0xfffc);\r | |
965 | if (((PciConfigHeader->Hdr.ClassCode[0] & 0x01) != 0) || (PciConfigHeader->Hdr.ClassCode[1] != PCI_CLASS_MASS_STORAGE_IDE)) {\r | |
966 | Private->IntThunk->PciHandler.PrimaryIrq = PciIrq;\r | |
967 | Private->IntThunk->PciHandler.PrimaryBase = (UINT16) (PciConfigHeader->Device.Bar[0] & 0xfffc);\r | |
968 | Private->IntThunk->PciHandler.PrimaryControl = (UINT16) ((PciConfigHeader->Device.Bar[1] & 0xfffc) + 2);\r | |
969 | } else {\r | |
970 | Private->IntThunk->PciHandler.PrimaryIrq = 14;\r | |
971 | Private->IntThunk->PciHandler.PrimaryBase = 0x1f0;\r | |
972 | Private->IntThunk->PciHandler.PrimaryControl = 0x3f6;\r | |
973 | }\r | |
974 | //\r | |
975 | // Secondary controller data\r | |
976 | //\r | |
977 | if (Private->IntThunk->PciHandler.PrimaryBusMaster != 0) {\r | |
978 | Private->IntThunk->PciHandler.SecondaryBusMaster = (UINT16) ((PciConfigHeader->Device.Bar[4] & 0xfffc) + 8);\r | |
979 | PrimaryMaster = (UINT16) (Private->IntThunk->PciHandler.PrimaryBusMaster + 2);\r | |
980 | SecondaryMaster = (UINT16) (Private->IntThunk->PciHandler.SecondaryBusMaster + 2);\r | |
981 | \r | |
982 | //\r | |
983 | // Clear pending interrupts in Bus Master registers\r | |
984 | //\r | |
985 | IoWrite16 (PrimaryMaster, 0x04);\r | |
986 | IoWrite16 (SecondaryMaster, 0x04);\r | |
987 | \r | |
988 | }\r | |
989 | \r | |
990 | //\r | |
991 | // Use native mode base address registers in two cases:\r | |
992 | // 1. Programming Interface (PI) register indicates Secondary Controller is\r | |
993 | // in native mode OR\r | |
994 | // 2. PCI device Sub Class Code is not IDE\r | |
995 | //\r | |
996 | if (((PciConfigHeader->Hdr.ClassCode[0] & 0x04) != 0) || (PciConfigHeader->Hdr.ClassCode[1] != PCI_CLASS_MASS_STORAGE_IDE)) {\r | |
997 | Private->IntThunk->PciHandler.SecondaryIrq = PciIrq;\r | |
998 | Private->IntThunk->PciHandler.SecondaryBase = (UINT16) (PciConfigHeader->Device.Bar[2] & 0xfffc);\r | |
999 | Private->IntThunk->PciHandler.SecondaryControl = (UINT16) ((PciConfigHeader->Device.Bar[3] & 0xfffc) + 2);\r | |
1000 | } else {\r | |
1001 | \r | |
1002 | Private->IntThunk->PciHandler.SecondaryIrq = 15;\r | |
1003 | Private->IntThunk->PciHandler.SecondaryBase = 0x170;\r | |
1004 | Private->IntThunk->PciHandler.SecondaryControl = 0x376;\r | |
1005 | }\r | |
1006 | \r | |
1007 | //\r | |
1008 | // Clear pending interrupts in IDE Command Block Status reg before we\r | |
1009 | // Thunk to CSM16 below. Don't want a pending Interrupt before we\r | |
1010 | // install the handlers as wierd corruption would occur and hang system.\r | |
1011 | //\r | |
1012 | //\r | |
1013 | // Read IDE CMD blk status reg to clear out any pending interrupts.\r | |
1014 | // Do here for Primary and Secondary IDE channels\r | |
1015 | //\r | |
1016 | RegisterAddress = (UINT16)Private->IntThunk->PciHandler.PrimaryBase + 0x07;\r | |
1017 | IoRead8 (RegisterAddress);\r | |
1018 | RegisterAddress = (UINT16)Private->IntThunk->PciHandler.SecondaryBase + 0x07;\r | |
1019 | IoRead8 (RegisterAddress);\r | |
1020 | \r | |
1021 | Private->IntThunk->PciHandler.PrimaryReserved = 0;\r | |
1022 | Private->IntThunk->PciHandler.SecondaryReserved = 0;\r | |
1023 | Private->LegacyRegion->UnLock (\r | |
1024 | Private->LegacyRegion,\r | |
1025 | 0xE0000,\r | |
1026 | 0x20000,\r | |
1027 | &Granularity\r | |
1028 | );\r | |
1029 | \r | |
1030 | Regs.X.AX = Legacy16InstallPciHandler;\r | |
1031 | TempData = (UINTN) &Private->IntThunk->PciHandler;\r | |
1032 | Regs.X.ES = EFI_SEGMENT ((UINT32) TempData);\r | |
1033 | Regs.X.BX = EFI_OFFSET ((UINT32) TempData);\r | |
1034 | \r | |
1035 | DumpPciHandle (&Private->IntThunk->PciHandler);\r | |
1036 | \r | |
1037 | Private->LegacyBios.FarCall86 (\r | |
1038 | &Private->LegacyBios,\r | |
1039 | Private->Legacy16CallSegment,\r | |
1040 | Private->Legacy16CallOffset,\r | |
1041 | &Regs,\r | |
1042 | NULL,\r | |
1043 | 0\r | |
1044 | );\r | |
1045 | \r | |
1046 | Private->Cpu->FlushDataCache (Private->Cpu, 0xE0000, 0x20000, EfiCpuFlushTypeWriteBackInvalidate);\r | |
1047 | Private->LegacyRegion->Lock (\r | |
1048 | Private->LegacyRegion,\r | |
1049 | 0xE0000,\r | |
1050 | 0x20000,\r | |
1051 | &Granularity\r | |
1052 | );\r | |
1053 | \r | |
1054 | }\r | |
1055 | \r | |
1056 | \r | |
1057 | /**\r | |
1058 | Program the interrupt routing register in all the PCI devices. On a PC AT system\r | |
1059 | this register contains the 8259 IRQ vector that matches it's PCI interrupt.\r | |
1060 | \r | |
1061 | @param Private Legacy BIOS Instance data\r | |
1062 | \r | |
1063 | @retval EFI_SUCCESS Succeed.\r | |
1064 | @retval EFI_ALREADY_STARTED All PCI devices have been processed.\r | |
1065 | \r | |
1066 | **/\r | |
1067 | EFI_STATUS\r | |
1068 | PciProgramAllInterruptLineRegisters (\r | |
1069 | IN LEGACY_BIOS_INSTANCE *Private\r | |
1070 | )\r | |
1071 | {\r | |
1072 | EFI_STATUS Status;\r | |
1073 | EFI_PCI_IO_PROTOCOL *PciIo;\r | |
1074 | EFI_LEGACY_8259_PROTOCOL *Legacy8259;\r | |
1075 | EFI_LEGACY_INTERRUPT_PROTOCOL *LegacyInterrupt;\r | |
1076 | EFI_LEGACY_BIOS_PLATFORM_PROTOCOL *LegacyBiosPlatform;\r | |
1077 | UINT8 InterruptPin;\r | |
1078 | UINTN Index;\r | |
1079 | UINTN HandleCount;\r | |
1080 | EFI_HANDLE *HandleBuffer;\r | |
1081 | UINTN MassStorageHandleCount;\r | |
1082 | EFI_HANDLE *MassStorageHandleBuffer;\r | |
1083 | UINTN MassStorageHandleIndex;\r | |
1084 | UINT8 PciIrq;\r | |
1085 | UINT16 Command;\r | |
1086 | UINTN PciSegment;\r | |
1087 | UINTN PciBus;\r | |
1088 | UINTN PciDevice;\r | |
1089 | UINTN PciFunction;\r | |
1090 | EFI_LEGACY_IRQ_ROUTING_ENTRY *RoutingTable;\r | |
1091 | UINTN RoutingTableEntries;\r | |
1092 | UINT16 LegMask;\r | |
1093 | UINT16 LegEdgeLevel;\r | |
1094 | PCI_TYPE00 PciConfigHeader;\r | |
1095 | EFI_LEGACY_PIRQ_TABLE_HEADER *PirqTable;\r | |
1096 | UINTN PirqTableSize;\r | |
1097 | UINTN Flags;\r | |
1098 | HDD_INFO *HddInfo;\r | |
1099 | UINT64 Supports;\r | |
1100 | \r | |
1101 | //\r | |
1102 | // Note - This routine use to return immediately if Private->PciInterruptLine\r | |
1103 | // was true. Routine changed since resets etc can cause not all\r | |
1104 | // PciIo protocols to be registered the first time through.\r | |
1105 | // New algorithm is to do the copy $PIR table on first pass and save\r | |
1106 | // HandleCount on first pass. If subsequent passes LocateHandleBuffer gives\r | |
1107 | // a larger handle count then proceed with body of function else return\r | |
1108 | // EFI_ALREADY_STARTED. In addition check if PCI device InterruptLine != 0.\r | |
1109 | // If zero then function unprogrammed else skip function.\r | |
1110 | //\r | |
1111 | Legacy8259 = Private->Legacy8259;\r | |
1112 | LegacyInterrupt = Private->LegacyInterrupt;\r | |
1113 | LegacyBiosPlatform = Private->LegacyBiosPlatform;\r | |
1114 | \r | |
1115 | LegacyBiosPlatform->GetRoutingTable (\r | |
1116 | Private->LegacyBiosPlatform,\r | |
1117 | (VOID *) &RoutingTable,\r | |
1118 | &RoutingTableEntries,\r | |
1119 | (VOID *) &PirqTable,\r | |
1120 | &PirqTableSize,\r | |
1121 | NULL,\r | |
1122 | NULL\r | |
1123 | );\r | |
1124 | CreateBridgeTable (RoutingTable, RoutingTableEntries);\r | |
1125 | \r | |
1126 | if (!Private->PciInterruptLine) {\r | |
1127 | CopyPirqTable (\r | |
1128 | Private,\r | |
1129 | RoutingTable,\r | |
1130 | RoutingTableEntries,\r | |
1131 | PirqTable,\r | |
1132 | PirqTableSize\r | |
1133 | );\r | |
1134 | }\r | |
1135 | \r | |
1136 | Status = gBS->LocateHandleBuffer (\r | |
1137 | ByProtocol,\r | |
1138 | &gEfiPciIoProtocolGuid,\r | |
1139 | NULL,\r | |
1140 | &HandleCount,\r | |
1141 | &HandleBuffer\r | |
1142 | );\r | |
1143 | if (EFI_ERROR (Status)) {\r | |
1144 | return EFI_NOT_FOUND;\r | |
1145 | }\r | |
1146 | if (HandleCount == mHandleCount) {\r | |
1147 | FreePool (HandleBuffer);\r | |
1148 | return EFI_ALREADY_STARTED;\r | |
1149 | }\r | |
1150 | \r | |
1151 | if (mHandleCount == 0x00) {\r | |
1152 | mHandleCount = HandleCount;\r | |
1153 | }\r | |
1154 | \r | |
1155 | for (Index = 0; Index < HandleCount; Index++) {\r | |
1156 | //\r | |
1157 | // If VGA then only do VGA to allow drives fore time to spin up\r | |
1158 | // otherwise assign PCI IRQs to all potential devices.\r | |
1159 | //\r | |
1160 | if ((mVgaInstallationInProgress) && (HandleBuffer[Index] != mVgaHandle)) {\r | |
1161 | continue;\r | |
1162 | } else {\r | |
1163 | //\r | |
1164 | // Force code to go through all handles next time called if video.\r | |
1165 | // This will catch case where HandleCount doesn't change but want\r | |
1166 | // to get drive info etc.\r | |
1167 | //\r | |
1168 | mHandleCount = 0x00;\r | |
1169 | }\r | |
1170 | \r | |
1171 | Status = gBS->HandleProtocol (\r | |
1172 | HandleBuffer[Index],\r | |
1173 | &gEfiPciIoProtocolGuid,\r | |
1174 | (VOID **) &PciIo\r | |
1175 | );\r | |
1176 | ASSERT_EFI_ERROR (Status);\r | |
1177 | \r | |
1178 | //\r | |
1179 | // Test whether the device can be enabled or not.\r | |
1180 | // If it can't be enabled, then just skip it to avoid further operation.\r | |
1181 | //\r | |
1182 | PciIo->Pci.Read (\r | |
1183 | PciIo,\r | |
1184 | EfiPciIoWidthUint32,\r | |
1185 | 0,\r | |
1186 | sizeof (PciConfigHeader) / sizeof (UINT32),\r | |
1187 | &PciConfigHeader\r | |
1188 | );\r | |
1189 | Command = PciConfigHeader.Hdr.Command;\r | |
1190 | \r | |
1191 | //\r | |
1192 | // Note PciIo->Attributes does not program the PCI command register\r | |
1193 | //\r | |
1194 | Status = PciIo->Attributes (\r | |
1195 | PciIo,\r | |
1196 | EfiPciIoAttributeOperationSupported,\r | |
1197 | 0,\r | |
1198 | &Supports\r | |
1199 | );\r | |
1200 | if (!EFI_ERROR (Status)) {\r | |
1a45b15e | 1201 | Supports &= (UINT64)EFI_PCI_DEVICE_ENABLE;\r |
bcecde14 | 1202 | Status = PciIo->Attributes (\r |
1203 | PciIo,\r | |
1204 | EfiPciIoAttributeOperationEnable,\r | |
1205 | Supports,\r | |
1206 | NULL\r | |
1207 | );\r | |
1208 | }\r | |
1209 | PciIo->Pci.Write (PciIo, EfiPciIoWidthUint16, 0x04, 1, &Command);\r | |
1210 | \r | |
1211 | if (EFI_ERROR (Status)) {\r | |
1212 | continue;\r | |
1213 | }\r | |
1214 | \r | |
1215 | InterruptPin = PciConfigHeader.Device.InterruptPin;\r | |
1216 | \r | |
1217 | if ((InterruptPin != 0) && (PciConfigHeader.Device.InterruptLine == PCI_INT_LINE_UNKNOWN)) {\r | |
1218 | PciIo->GetLocation (\r | |
1219 | PciIo,\r | |
1220 | &PciSegment,\r | |
1221 | &PciBus,\r | |
1222 | &PciDevice,\r | |
1223 | &PciFunction\r | |
1224 | );\r | |
1225 | //\r | |
1226 | // Translate PIRQ index back thru busses to slot bus with InterruptPin\r | |
1227 | // zero based\r | |
1228 | //\r | |
1229 | InterruptPin -= 1;\r | |
1230 | \r | |
1231 | Status = GetBaseBus (\r | |
1232 | Private,\r | |
1233 | PciBus,\r | |
1234 | PciDevice,\r | |
1235 | RoutingTable,\r | |
1236 | RoutingTableEntries\r | |
1237 | );\r | |
1238 | \r | |
1239 | if (Status == EFI_NOT_FOUND) {\r | |
1240 | TranslateBusPirq (\r | |
1241 | Private,\r | |
1242 | &PciBus,\r | |
1243 | &PciDevice,\r | |
1244 | &PciFunction,\r | |
1245 | &InterruptPin\r | |
1246 | );\r | |
1247 | }\r | |
1248 | //\r | |
1249 | // Translate InterruptPin(0-3) into PIRQ\r | |
1250 | //\r | |
1251 | Status = LegacyBiosPlatform->TranslatePirq (\r | |
1252 | LegacyBiosPlatform,\r | |
1253 | PciBus,\r | |
1254 | (PciDevice << 3),\r | |
1255 | PciFunction,\r | |
1256 | &InterruptPin,\r | |
1257 | &PciIrq\r | |
1258 | );\r | |
1259 | //\r | |
1260 | // TranslatePirq() should never fail or we are in trouble\r | |
1261 | // If it does return failure status, check your PIRQ routing table to see if some item is missing or incorrect\r | |
1262 | //\r | |
1263 | if (EFI_ERROR (Status)) {\r | |
1264 | DEBUG ((EFI_D_ERROR, "Translate Pirq Failed - Status = %r\n ", Status));\r | |
1265 | continue;\r | |
1266 | }\r | |
1267 | \r | |
1268 | LegacyInterrupt->WritePirq (\r | |
1269 | LegacyInterrupt,\r | |
1270 | InterruptPin,\r | |
1271 | PciIrq\r | |
1272 | );\r | |
1273 | \r | |
1274 | //\r | |
1275 | // Check if device has an OPROM associated with it.\r | |
1276 | // If not invoke special 16-bit function, to allow 16-bit\r | |
1277 | // code to install an interrupt handler.\r | |
1278 | //\r | |
1279 | Status = LegacyBiosCheckPciRom (\r | |
1280 | &Private->LegacyBios,\r | |
1281 | HandleBuffer[Index],\r | |
1282 | NULL,\r | |
1283 | NULL,\r | |
1284 | &Flags\r | |
1285 | );\r | |
1286 | if ((EFI_ERROR (Status)) && (PciConfigHeader.Hdr.ClassCode[2] == PCI_CLASS_MASS_STORAGE)) {\r | |
1287 | //\r | |
1288 | // Device has no OPROM associated with it and is a mass storage\r | |
1289 | // device. It needs to have an PCI IRQ handler installed. To\r | |
1290 | // correctly install the handler we need to insure device is\r | |
1291 | // connected. The device may just have register itself but not\r | |
1292 | // been connected. Re-read PCI config space after as it can\r | |
1293 | // change\r | |
1294 | //\r | |
1295 | //\r | |
1296 | // Get IDE Handle. If matches handle then skip ConnectController\r | |
1297 | // since ConnectController may force native mode and we don't\r | |
1298 | // want that for primary IDE controller\r | |
1299 | //\r | |
1300 | MassStorageHandleCount = 0;\r | |
1301 | MassStorageHandleBuffer = NULL;\r | |
1302 | LegacyBiosPlatform->GetPlatformHandle (\r | |
1303 | Private->LegacyBiosPlatform,\r | |
1304 | EfiGetPlatformIdeHandle,\r | |
1305 | 0,\r | |
1306 | &MassStorageHandleBuffer,\r | |
1307 | &MassStorageHandleCount,\r | |
1308 | NULL\r | |
1309 | );\r | |
1310 | \r | |
1311 | HddInfo = &Private->IntThunk->EfiToLegacy16BootTable.HddInfo[0];\r | |
1312 | \r | |
1313 | LegacyBiosBuildIdeData (Private, &HddInfo, 0);\r | |
1314 | PciIo->Pci.Read (\r | |
1315 | PciIo,\r | |
1316 | EfiPciIoWidthUint32,\r | |
1317 | 0,\r | |
1318 | sizeof (PciConfigHeader) / sizeof (UINT32),\r | |
1319 | &PciConfigHeader\r | |
1320 | );\r | |
1321 | \r | |
1322 | for (MassStorageHandleIndex = 0; MassStorageHandleIndex < MassStorageHandleCount; MassStorageHandleIndex++) {\r | |
1323 | if (MassStorageHandleBuffer[MassStorageHandleIndex] == HandleBuffer[Index]) {\r | |
1324 | //\r | |
1325 | // InstallLegacyIrqHandler according to Platform requirement\r | |
1326 | //\r | |
1327 | InstallLegacyIrqHandler (\r | |
1328 | Private,\r | |
1329 | PciIo,\r | |
1330 | PciIrq,\r | |
1331 | &PciConfigHeader\r | |
1332 | );\r | |
1333 | break;\r | |
1334 | }\r | |
1335 | }\r | |
1336 | }\r | |
1337 | //\r | |
1338 | // Write InterruptPin and enable 8259.\r | |
1339 | //\r | |
1340 | PciIo->Pci.Write (\r | |
1341 | PciIo,\r | |
1342 | EfiPciIoWidthUint8,\r | |
1343 | 0x3c,\r | |
1344 | 1,\r | |
1345 | &PciIrq\r | |
1346 | );\r | |
1347 | Private->IntThunk->EfiToLegacy16BootTable.PciIrqMask = (UINT16) (Private->IntThunk->EfiToLegacy16BootTable.PciIrqMask | (UINT16) (1 << PciIrq));\r | |
1348 | \r | |
1349 | Legacy8259->GetMask (\r | |
1350 | Legacy8259,\r | |
1351 | &LegMask,\r | |
1352 | &LegEdgeLevel,\r | |
1353 | NULL,\r | |
1354 | NULL\r | |
1355 | );\r | |
1356 | \r | |
1357 | LegMask = (UINT16) (LegMask & (UINT16)~(1 << PciIrq));\r | |
1358 | LegEdgeLevel = (UINT16) (LegEdgeLevel | (UINT16) (1 << PciIrq));\r | |
1359 | Legacy8259->SetMask (\r | |
1360 | Legacy8259,\r | |
1361 | &LegMask,\r | |
1362 | &LegEdgeLevel,\r | |
1363 | NULL,\r | |
1364 | NULL\r | |
1365 | );\r | |
1366 | }\r | |
1367 | }\r | |
1368 | FreePool (HandleBuffer);\r | |
1369 | return EFI_SUCCESS;\r | |
1370 | }\r | |
1371 | \r | |
1372 | \r | |
1373 | /**\r | |
1374 | Find & verify PnP Expansion header in ROM image\r | |
1375 | \r | |
1376 | @param Private Protocol instance pointer.\r | |
1377 | @param FirstHeader 1 = Find first header, 0 = Find successive headers\r | |
1378 | @param PnpPtr Input Rom start if FirstHeader =1, Current Header\r | |
1379 | otherwise Output Next header, if it exists\r | |
1380 | \r | |
1381 | @retval EFI_SUCCESS Next Header found at BasePnpPtr\r | |
1382 | @retval EFI_NOT_FOUND No more headers\r | |
1383 | \r | |
1384 | **/\r | |
1385 | EFI_STATUS\r | |
1386 | FindNextPnpExpansionHeader (\r | |
1387 | IN LEGACY_BIOS_INSTANCE *Private,\r | |
1388 | IN BOOLEAN FirstHeader,\r | |
1389 | IN OUT LEGACY_PNP_EXPANSION_HEADER **PnpPtr\r | |
1390 | \r | |
1391 | )\r | |
1392 | {\r | |
1393 | UINTN TempData;\r | |
1394 | LEGACY_PNP_EXPANSION_HEADER *LocalPnpPtr;\r | |
1395 | LocalPnpPtr = *PnpPtr;\r | |
1396 | if (FirstHeader == FIRST_INSTANCE) {\r | |
1397 | mBasePnpPtr = LocalPnpPtr;\r | |
1398 | mBbsRomSegment = (UINT16) ((UINTN) mBasePnpPtr >> 4);\r | |
1399 | //\r | |
1400 | // Offset 0x1a gives offset to PnP expansion header for the first\r | |
1401 | // instance, there after the structure gives the offset to the next\r | |
1402 | // structure\r | |
1403 | //\r | |
1404 | LocalPnpPtr = (LEGACY_PNP_EXPANSION_HEADER *) ((UINT8 *) LocalPnpPtr + 0x1a);\r | |
1405 | TempData = (*((UINT16 *) LocalPnpPtr));\r | |
1406 | } else {\r | |
1407 | TempData = (UINT16) LocalPnpPtr->NextHeader;\r | |
1408 | }\r | |
1409 | \r | |
1410 | LocalPnpPtr = (LEGACY_PNP_EXPANSION_HEADER *) (((UINT8 *) mBasePnpPtr + TempData));\r | |
1411 | \r | |
1412 | //\r | |
1413 | // Search for PnP table in Shadowed ROM\r | |
1414 | //\r | |
1415 | *PnpPtr = LocalPnpPtr;\r | |
1416 | if (*(UINT32 *) LocalPnpPtr == SIGNATURE_32 ('$', 'P', 'n', 'P')) {\r | |
1417 | return EFI_SUCCESS;\r | |
1418 | } else {\r | |
1419 | return EFI_NOT_FOUND;\r | |
1420 | }\r | |
1421 | }\r | |
1422 | \r | |
1423 | \r | |
1424 | /**\r | |
1425 | Update list of Bev or BCV table entries.\r | |
1426 | \r | |
1427 | @param Private Protocol instance pointer.\r | |
1428 | @param RomStart Table of ROM start address in RAM/ROM. PciIo _\r | |
1429 | Handle to PCI IO for this device\r | |
1430 | @param PciIo Instance of PCI I/O Protocol\r | |
1431 | \r | |
1432 | @retval EFI_SUCCESS Always should succeed.\r | |
1433 | \r | |
1434 | **/\r | |
1435 | EFI_STATUS\r | |
1436 | UpdateBevBcvTable (\r | |
1437 | IN LEGACY_BIOS_INSTANCE *Private,\r | |
1438 | IN EFI_LEGACY_EXPANSION_ROM_HEADER *RomStart,\r | |
1439 | IN EFI_PCI_IO_PROTOCOL *PciIo\r | |
1440 | )\r | |
1441 | {\r | |
1442 | VOID *RomEnd;\r | |
1443 | BBS_TABLE *BbsTable;\r | |
1444 | UINTN BbsIndex;\r | |
1445 | EFI_LEGACY_EXPANSION_ROM_HEADER *PciPtr;\r | |
1446 | LEGACY_PNP_EXPANSION_HEADER *PnpPtr;\r | |
1447 | BOOLEAN Instance;\r | |
1448 | EFI_STATUS Status;\r | |
1449 | UINTN Segment;\r | |
1450 | UINTN Bus;\r | |
1451 | UINTN Device;\r | |
1452 | UINTN Function;\r | |
1453 | UINT8 Class;\r | |
1454 | UINT16 DeviceType;\r | |
1455 | Segment = 0;\r | |
1456 | Bus = 0;\r | |
1457 | Device = 0;\r | |
1458 | Function = 0;\r | |
1459 | Class = 0;\r | |
1460 | DeviceType = BBS_UNKNOWN;\r | |
1461 | \r | |
1462 | //\r | |
1463 | // Skip floppy and 2*onboard IDE controller entries(Master/Slave per\r | |
1464 | // controller).\r | |
1465 | //\r | |
1466 | BbsIndex = Private->IntThunk->EfiToLegacy16BootTable.NumberBbsEntries;\r | |
1467 | \r | |
1468 | BbsTable = (BBS_TABLE*)(UINTN) Private->IntThunk->EfiToLegacy16BootTable.BbsTable;\r | |
1469 | PnpPtr = (LEGACY_PNP_EXPANSION_HEADER *) RomStart;\r | |
1470 | PciPtr = (EFI_LEGACY_EXPANSION_ROM_HEADER *) RomStart;\r | |
1471 | \r | |
1472 | RomEnd = (VOID *) (PciPtr->Size512 * 512 + (UINTN) PciPtr);\r | |
1473 | Instance = FIRST_INSTANCE;\r | |
1474 | //\r | |
1475 | // OPROMs like PXE may not be tied to a piece of hardware and thus\r | |
1476 | // don't have a PciIo associated with them\r | |
1477 | //\r | |
1478 | if (PciIo != NULL) {\r | |
1479 | PciIo->GetLocation (\r | |
1480 | PciIo,\r | |
1481 | &Segment,\r | |
1482 | &Bus,\r | |
1483 | &Device,\r | |
1484 | &Function\r | |
1485 | );\r | |
1486 | PciIo->Pci.Read (\r | |
1487 | PciIo,\r | |
1488 | EfiPciIoWidthUint8,\r | |
1489 | 0x0b,\r | |
1490 | 1,\r | |
1491 | &Class\r | |
1492 | );\r | |
1493 | \r | |
1494 | if (Class == PCI_CLASS_MASS_STORAGE) {\r | |
1495 | DeviceType = BBS_HARDDISK;\r | |
1496 | } else {\r | |
1497 | if (Class == PCI_CLASS_NETWORK) {\r | |
1498 | DeviceType = BBS_EMBED_NETWORK;\r | |
1499 | }\r | |
1500 | }\r | |
1501 | }\r | |
1502 | \r | |
22921b02 | 1503 | while (TRUE) {\r |
1504 | Status = FindNextPnpExpansionHeader (Private, Instance, &PnpPtr);\r | |
1505 | Instance = NOT_FIRST_INSTANCE;\r | |
1506 | if (EFI_ERROR (Status)) {\r | |
1507 | break;\r | |
1508 | }\r | |
1509 | //\r | |
1510 | // There can be additional $PnP headers within the OPROM.\r | |
1511 | // Example: SCSI can have one per drive.\r | |
1512 | //\r | |
1513 | BbsTable[BbsIndex].BootPriority = BBS_UNPRIORITIZED_ENTRY;\r | |
1514 | BbsTable[BbsIndex].DeviceType = DeviceType;\r | |
1515 | BbsTable[BbsIndex].Bus = (UINT32) Bus;\r | |
1516 | BbsTable[BbsIndex].Device = (UINT32) Device;\r | |
1517 | BbsTable[BbsIndex].Function = (UINT32) Function;\r | |
1518 | BbsTable[BbsIndex].StatusFlags.OldPosition = 0;\r | |
1519 | BbsTable[BbsIndex].StatusFlags.Reserved1 = 0;\r | |
1520 | BbsTable[BbsIndex].StatusFlags.Enabled = 0;\r | |
1521 | BbsTable[BbsIndex].StatusFlags.Failed = 0;\r | |
1522 | BbsTable[BbsIndex].StatusFlags.MediaPresent = 0;\r | |
1523 | BbsTable[BbsIndex].StatusFlags.Reserved2 = 0;\r | |
1524 | BbsTable[BbsIndex].Class = PnpPtr->Class;\r | |
1525 | BbsTable[BbsIndex].SubClass = PnpPtr->SubClass;\r | |
1526 | BbsTable[BbsIndex].DescStringOffset = PnpPtr->ProductNamePointer;\r | |
1527 | BbsTable[BbsIndex].DescStringSegment = mBbsRomSegment;\r | |
1528 | BbsTable[BbsIndex].MfgStringOffset = PnpPtr->MfgPointer;\r | |
1529 | BbsTable[BbsIndex].MfgStringSegment = mBbsRomSegment;\r | |
1530 | BbsTable[BbsIndex].BootHandlerSegment = mBbsRomSegment;\r | |
bcecde14 | 1531 | \r |
22921b02 | 1532 | //\r |
1533 | // Have seen case where PXE base code have PnP expansion ROM\r | |
1534 | // header but no Bcv or Bev vectors.\r | |
1535 | //\r | |
1536 | if (PnpPtr->Bcv != 0) {\r | |
1537 | BbsTable[BbsIndex].BootHandlerOffset = PnpPtr->Bcv;\r | |
1538 | ++BbsIndex;\r | |
1539 | }\r | |
bcecde14 | 1540 | \r |
22921b02 | 1541 | if (PnpPtr->Bev != 0) {\r |
1542 | BbsTable[BbsIndex].BootHandlerOffset = PnpPtr->Bev;\r | |
1543 | BbsTable[BbsIndex].DeviceType = BBS_BEV_DEVICE;\r | |
1544 | ++BbsIndex;\r | |
1545 | }\r | |
bcecde14 | 1546 | \r |
22921b02 | 1547 | if ((PnpPtr == (LEGACY_PNP_EXPANSION_HEADER *) PciPtr) || (PnpPtr > (LEGACY_PNP_EXPANSION_HEADER *) RomEnd)) {\r |
1548 | break;\r | |
bcecde14 | 1549 | }\r |
1550 | }\r | |
1551 | \r | |
1552 | BbsTable[BbsIndex].BootPriority = BBS_IGNORE_ENTRY;\r | |
1553 | Private->IntThunk->EfiToLegacy16BootTable.NumberBbsEntries = (UINT32) BbsIndex;\r | |
1554 | return EFI_SUCCESS;\r | |
1555 | }\r | |
1556 | \r | |
1557 | \r | |
1558 | /**\r | |
1559 | Shadow all the PCI legacy ROMs. Use data from the Legacy BIOS Protocol\r | |
1560 | to chose the order. Skip any devices that have already have legacy\r | |
1561 | BIOS run.\r | |
1562 | \r | |
1563 | @param Private Protocol instance pointer.\r | |
1564 | \r | |
1565 | @retval EFI_SUCCESS Succeed.\r | |
1566 | @retval EFI_UNSUPPORTED Cannot get VGA device handle.\r | |
1567 | \r | |
1568 | **/\r | |
1569 | EFI_STATUS\r | |
1570 | PciShadowRoms (\r | |
1571 | IN LEGACY_BIOS_INSTANCE *Private\r | |
1572 | )\r | |
1573 | {\r | |
1574 | EFI_STATUS Status;\r | |
1575 | EFI_PCI_IO_PROTOCOL *PciIo;\r | |
1576 | PCI_TYPE00 Pci;\r | |
1577 | UINTN Index;\r | |
1578 | UINTN HandleCount;\r | |
1579 | EFI_HANDLE *HandleBuffer;\r | |
1580 | EFI_HANDLE VgaHandle;\r | |
1581 | EFI_HANDLE FirstHandle;\r | |
1582 | VOID **RomStart;\r | |
1583 | UINTN Flags;\r | |
1584 | PCI_TYPE00 PciConfigHeader;\r | |
1585 | UINT16 *Command;\r | |
1586 | UINT64 Supports;\r | |
1587 | \r | |
1588 | //\r | |
1589 | // Make the VGA device first\r | |
1590 | //\r | |
1591 | Status = Private->LegacyBiosPlatform->GetPlatformHandle (\r | |
1592 | Private->LegacyBiosPlatform,\r | |
1593 | EfiGetPlatformVgaHandle,\r | |
1594 | 0,\r | |
1595 | &HandleBuffer,\r | |
1596 | &HandleCount,\r | |
1597 | NULL\r | |
1598 | ); \r | |
1599 | if (EFI_ERROR (Status)) {\r | |
1600 | return EFI_UNSUPPORTED;\r | |
1601 | }\r | |
1602 | \r | |
1603 | VgaHandle = HandleBuffer[0];\r | |
1604 | \r | |
1605 | Status = gBS->LocateHandleBuffer (\r | |
1606 | ByProtocol,\r | |
1607 | &gEfiPciIoProtocolGuid,\r | |
1608 | NULL,\r | |
1609 | &HandleCount,\r | |
1610 | &HandleBuffer\r | |
1611 | );\r | |
1612 | \r | |
1613 | if (EFI_ERROR (Status)) {\r | |
1614 | return Status;\r | |
1615 | }\r | |
1616 | //\r | |
1617 | // Place the VGA handle as first.\r | |
1618 | //\r | |
1619 | for (Index = 0; Index < HandleCount; Index++) {\r | |
1620 | if (HandleBuffer[Index] == VgaHandle) {\r | |
1621 | FirstHandle = HandleBuffer[0];\r | |
1622 | HandleBuffer[0] = HandleBuffer[Index];\r | |
1623 | HandleBuffer[Index] = FirstHandle;\r | |
1624 | break;\r | |
1625 | }\r | |
1626 | }\r | |
1627 | //\r | |
1628 | // Allocate memory to save Command WORD from each device. We do this\r | |
1629 | // to restore devices to same state as EFI after switching to legacy.\r | |
1630 | //\r | |
1631 | Command = (UINT16 *) AllocatePool (\r | |
1632 | sizeof (UINT16) * (HandleCount + 1)\r | |
1633 | );\r | |
1634 | if (NULL == Command) {\r | |
1635 | FreePool (HandleBuffer);\r | |
1636 | return EFI_OUT_OF_RESOURCES;\r | |
1637 | }\r | |
1638 | //\r | |
1639 | // Disconnect all EFI devices first. This covers cases where alegacy BIOS\r | |
1640 | // may control multiple PCI devices.\r | |
1641 | //\r | |
1642 | for (Index = 0; Index < HandleCount; Index++) {\r | |
1643 | \r | |
1644 | Status = gBS->HandleProtocol (\r | |
1645 | HandleBuffer[Index],\r | |
1646 | &gEfiPciIoProtocolGuid,\r | |
1647 | (VOID **) &PciIo\r | |
1648 | );\r | |
1649 | ASSERT_EFI_ERROR (Status);\r | |
1650 | \r | |
1651 | //\r | |
1652 | // Save command register for "connect" loop\r | |
1653 | //\r | |
1654 | PciIo->Pci.Read (\r | |
1655 | PciIo,\r | |
1656 | EfiPciIoWidthUint32,\r | |
1657 | 0,\r | |
1658 | sizeof (PciConfigHeader) / sizeof (UINT32),\r | |
1659 | &PciConfigHeader\r | |
1660 | );\r | |
1661 | Command[Index] = PciConfigHeader.Hdr.Command;\r | |
1662 | //\r | |
1663 | // Skip any device that already has a legacy ROM run\r | |
1664 | //\r | |
1665 | Status = IsLegacyRom (HandleBuffer[Index]);\r | |
1666 | if (!EFI_ERROR (Status)) {\r | |
1667 | continue;\r | |
1668 | }\r | |
1669 | //\r | |
1670 | // Stop EFI Drivers with oprom.\r | |
1671 | //\r | |
1672 | gBS->DisconnectController (\r | |
1673 | HandleBuffer[Index],\r | |
1674 | NULL,\r | |
1675 | NULL\r | |
1676 | );\r | |
1677 | }\r | |
1678 | //\r | |
1679 | // For every device that has not had a legacy ROM started. Start a legacy ROM.\r | |
1680 | //\r | |
1681 | for (Index = 0; Index < HandleCount; Index++) {\r | |
1682 | \r | |
1683 | Status = gBS->HandleProtocol (\r | |
1684 | HandleBuffer[Index],\r | |
1685 | &gEfiPciIoProtocolGuid,\r | |
1686 | (VOID **) &PciIo\r | |
1687 | );\r | |
1688 | \r | |
1689 | ASSERT_EFI_ERROR (Status);\r | |
1690 | \r | |
1691 | //\r | |
1692 | // Here make sure if one VGA have been shadowed,\r | |
1693 | // then wil not shadowed another one.\r | |
1694 | //\r | |
1695 | PciIo->Pci.Read (\r | |
1696 | PciIo,\r | |
1697 | EfiPciIoWidthUint32,\r | |
1698 | 0,\r | |
1699 | sizeof (Pci) / sizeof (UINT32),\r | |
1700 | &Pci\r | |
1701 | );\r | |
1702 | \r | |
1703 | //\r | |
1704 | // Only one Video OPROM can be given control in BIOS phase. If there are multiple Video devices, \r | |
1705 | // one will work in legacy mode (OPROM will be given control) and \r | |
1706 | // other Video devices will work in native mode (OS driver will handle these devices).\r | |
1707 | // \r | |
1708 | if (IS_PCI_DISPLAY (&Pci) && Index != 0) { \r | |
1709 | continue;\r | |
1710 | }\r | |
1711 | //\r | |
1712 | // Skip any device that already has a legacy ROM run\r | |
1713 | //\r | |
1714 | Status = IsLegacyRom (HandleBuffer[Index]);\r | |
1715 | if (!EFI_ERROR (Status)) {\r | |
1716 | continue;\r | |
1717 | }\r | |
0934a605 | 1718 | \r |
1719 | //\r | |
1720 | // If legacy VBIOS Oprom has not been dispatched before, install legacy VBIOS here.\r | |
1721 | //\r | |
1722 | if (IS_PCI_DISPLAY (&Pci) && Index == 0) { \r | |
1723 | Status = LegacyBiosInstallVgaRom (Private);\r | |
1724 | //\r | |
1725 | // A return status of EFI_NOT_FOUND is considered valid (No EFI\r | |
1726 | // driver is controlling video).\r | |
1727 | //\r | |
1728 | ASSERT ((Status == EFI_SUCCESS) || (Status == EFI_NOT_FOUND));\r | |
1729 | continue;\r | |
1730 | }\r | |
1731 | \r | |
bcecde14 | 1732 | //\r |
1733 | // Install legacy ROM\r | |
1734 | //\r | |
1735 | Status = LegacyBiosInstallPciRom (\r | |
1736 | &Private->LegacyBios,\r | |
1737 | HandleBuffer[Index],\r | |
1738 | NULL,\r | |
1739 | &Flags,\r | |
1740 | NULL,\r | |
1741 | NULL,\r | |
1742 | (VOID **) &RomStart,\r | |
1743 | NULL\r | |
1744 | );\r | |
1745 | if (EFI_ERROR (Status)) {\r | |
1746 | if (!((Status == EFI_UNSUPPORTED) && (Flags == NO_ROM))) {\r | |
1747 | continue;\r | |
1748 | }\r | |
1749 | }\r | |
1750 | //\r | |
1751 | // Restore Command register so legacy has same devices enabled or disabled\r | |
1752 | // as EFI.\r | |
1753 | // If Flags = NO_ROM use command register as is. This covers the\r | |
1754 | // following cases:\r | |
1755 | // Device has no ROMs associated with it.\r | |
1756 | // Device has ROM associated with it but was already\r | |
1757 | // installed.\r | |
1758 | // = ROM_FOUND but not VALID_LEGACY_ROM, disable it.\r | |
1759 | // = ROM_FOUND and VALID_LEGACY_ROM, enable it.\r | |
1760 | //\r | |
1761 | if ((Flags & ROM_FOUND) == ROM_FOUND) {\r | |
1762 | if ((Flags & VALID_LEGACY_ROM) == 0) {\r | |
1763 | Command[Index] = 0;\r | |
1764 | } else {\r | |
1765 | //\r | |
1766 | // For several VGAs, only one of them can be enabled.\r | |
1767 | //\r | |
1768 | Status = PciIo->Attributes (\r | |
1769 | PciIo,\r | |
1770 | EfiPciIoAttributeOperationSupported,\r | |
1771 | 0,\r | |
1772 | &Supports\r | |
1773 | );\r | |
1774 | if (!EFI_ERROR (Status)) {\r | |
1a45b15e | 1775 | Supports &= (UINT64)EFI_PCI_DEVICE_ENABLE;\r |
bcecde14 | 1776 | Status = PciIo->Attributes (\r |
1777 | PciIo,\r | |
1778 | EfiPciIoAttributeOperationEnable,\r | |
1779 | Supports,\r | |
1780 | NULL\r | |
1781 | );\r | |
1782 | }\r | |
1783 | if (!EFI_ERROR (Status)) {\r | |
1784 | Command[Index] = 0x1f;\r | |
1785 | }\r | |
1786 | }\r | |
1787 | }\r | |
1788 | \r | |
1789 | PciIo->Pci.Write (\r | |
1790 | PciIo,\r | |
1791 | EfiPciIoWidthUint16,\r | |
1792 | 0x04,\r | |
1793 | 1,\r | |
1794 | &Command[Index]\r | |
1795 | );\r | |
1796 | }\r | |
1797 | \r | |
1798 | FreePool (Command);\r | |
1799 | FreePool (HandleBuffer);\r | |
1800 | return EFI_SUCCESS;\r | |
1801 | }\r | |
1802 | \r | |
1803 | \r | |
1804 | /**\r | |
1805 | Test to see if a legacy PCI ROM exists for this device. Optionally return\r | |
1806 | the Legacy ROM instance for this PCI device.\r | |
1807 | \r | |
1808 | @param This Protocol instance pointer.\r | |
1809 | @param PciHandle The PCI PC-AT OPROM from this devices ROM BAR will\r | |
1810 | be loaded\r | |
1811 | @param RomImage Return the legacy PCI ROM for this device\r | |
1812 | @param RomSize Size of ROM Image\r | |
1813 | @param Flags Indicates if ROM found and if PC-AT.\r | |
1814 | \r | |
70d3fe9d | 1815 | @retval EFI_SUCCESS Legacy Option ROM available for this device\r |
bcecde14 | 1816 | @retval EFI_UNSUPPORTED Legacy Option ROM not supported.\r |
1817 | \r | |
1818 | **/\r | |
1819 | EFI_STATUS\r | |
1820 | EFIAPI\r | |
1821 | LegacyBiosCheckPciRom (\r | |
1822 | IN EFI_LEGACY_BIOS_PROTOCOL *This,\r | |
1823 | IN EFI_HANDLE PciHandle,\r | |
1824 | OUT VOID **RomImage, OPTIONAL\r | |
1825 | OUT UINTN *RomSize, OPTIONAL\r | |
1826 | OUT UINTN *Flags\r | |
1827 | )\r | |
1828 | {\r | |
1829 | return LegacyBiosCheckPciRomEx (\r | |
1830 | This,\r | |
1831 | PciHandle,\r | |
1832 | RomImage,\r | |
1833 | RomSize,\r | |
1834 | NULL,\r | |
1835 | Flags,\r | |
1836 | NULL,\r | |
1837 | NULL\r | |
1838 | );\r | |
1839 | \r | |
1840 | }\r | |
1841 | \r | |
1842 | /**\r | |
1843 | \r | |
1844 | Routine Description:\r | |
1845 | Test to see if a legacy PCI ROM exists for this device. Optionally return\r | |
1846 | the Legacy ROM instance for this PCI device.\r | |
1847 | \r | |
1848 | @param[in] This Protocol instance pointer.\r | |
1849 | @param[in] PciHandle The PCI PC-AT OPROM from this devices ROM BAR will be loaded\r | |
1850 | @param[out] RomImage Return the legacy PCI ROM for this device\r | |
1851 | @param[out] RomSize Size of ROM Image\r | |
1852 | @param[out] RuntimeImageLength Runtime size of ROM Image\r | |
1853 | @param[out] Flags Indicates if ROM found and if PC-AT.\r | |
1854 | @param[out] OpromRevision Revision of the PCI Rom\r | |
1855 | @param[out] ConfigUtilityCodeHeaderPointer of Configuration Utility Code Header\r | |
1856 | \r | |
70d3fe9d | 1857 | @return EFI_SUCCESS Legacy Option ROM available for this device\r |
bcecde14 | 1858 | @return EFI_ALREADY_STARTED This device is already managed by its Oprom\r |
1859 | @return EFI_UNSUPPORTED Legacy Option ROM not supported.\r | |
1860 | \r | |
1861 | **/\r | |
1862 | EFI_STATUS\r | |
1863 | LegacyBiosCheckPciRomEx (\r | |
1864 | IN EFI_LEGACY_BIOS_PROTOCOL *This,\r | |
1865 | IN EFI_HANDLE PciHandle,\r | |
1866 | OUT VOID **RomImage, OPTIONAL\r | |
1867 | OUT UINTN *RomSize, OPTIONAL\r | |
1868 | OUT UINTN *RuntimeImageLength, OPTIONAL\r | |
1869 | OUT UINTN *Flags, OPTIONAL\r | |
1870 | OUT UINT8 *OpromRevision, OPTIONAL\r | |
1871 | OUT VOID **ConfigUtilityCodeHeader OPTIONAL\r | |
1872 | )\r | |
1873 | {\r | |
1874 | EFI_STATUS Status;\r | |
1875 | LEGACY_BIOS_INSTANCE *Private;\r | |
1876 | EFI_PCI_IO_PROTOCOL *PciIo;\r | |
1877 | UINTN LocalRomSize;\r | |
1878 | VOID *LocalRomImage;\r | |
1879 | PCI_TYPE00 PciConfigHeader;\r | |
1880 | VOID *LocalConfigUtilityCodeHeader;\r | |
1881 | \r | |
613382e9 | 1882 | LocalConfigUtilityCodeHeader = NULL;\r |
bcecde14 | 1883 | *Flags = NO_ROM;\r |
1884 | Status = gBS->HandleProtocol (\r | |
1885 | PciHandle,\r | |
1886 | &gEfiPciIoProtocolGuid,\r | |
1887 | (VOID **) &PciIo\r | |
1888 | );\r | |
1889 | if (EFI_ERROR (Status)) {\r | |
1890 | return EFI_UNSUPPORTED;\r | |
1891 | }\r | |
1892 | \r | |
1893 | //\r | |
1894 | // See if the option ROM for PciHandle has already been executed\r | |
1895 | //\r | |
1896 | Status = IsLegacyRom (PciHandle);\r | |
1897 | if (!EFI_ERROR (Status)) {\r | |
1a45b15e | 1898 | *Flags |= (UINTN)(ROM_FOUND | VALID_LEGACY_ROM);\r |
bcecde14 | 1899 | return EFI_SUCCESS;\r |
1900 | }\r | |
1901 | //\r | |
1902 | // Check for PCI ROM Bar\r | |
1903 | //\r | |
1904 | LocalRomSize = (UINTN) PciIo->RomSize;\r | |
1905 | LocalRomImage = PciIo->RomImage;\r | |
1906 | if (LocalRomSize != 0) {\r | |
1907 | *Flags |= ROM_FOUND;\r | |
1908 | }\r | |
1909 | \r | |
1910 | //\r | |
1911 | // PCI specification states you should check VendorId and Device Id.\r | |
1912 | //\r | |
1913 | PciIo->Pci.Read (\r | |
1914 | PciIo,\r | |
1915 | EfiPciIoWidthUint32,\r | |
1916 | 0,\r | |
1917 | sizeof (PciConfigHeader) / sizeof (UINT32),\r | |
1918 | &PciConfigHeader\r | |
1919 | );\r | |
1920 | \r | |
1921 | Private = LEGACY_BIOS_INSTANCE_FROM_THIS (This);\r | |
1922 | Status = GetPciLegacyRom (\r | |
1923 | Private->Csm16PciInterfaceVersion,\r | |
1924 | PciConfigHeader.Hdr.VendorId,\r | |
1925 | PciConfigHeader.Hdr.DeviceId,\r | |
1926 | &LocalRomImage,\r | |
1927 | &LocalRomSize,\r | |
1928 | RuntimeImageLength,\r | |
1929 | OpromRevision,\r | |
1930 | &LocalConfigUtilityCodeHeader\r | |
1931 | );\r | |
1932 | if (EFI_ERROR (Status)) {\r | |
1933 | return EFI_UNSUPPORTED;\r | |
1934 | }\r | |
1935 | \r | |
1936 | *Flags |= VALID_LEGACY_ROM;\r | |
1937 | \r | |
1938 | //\r | |
1939 | // See if Configuration Utility Code Header valid\r | |
1940 | //\r | |
1941 | if (LocalConfigUtilityCodeHeader != NULL) {\r | |
1942 | *Flags |= ROM_WITH_CONFIG;\r | |
1943 | }\r | |
1944 | \r | |
1945 | if (ConfigUtilityCodeHeader != NULL) {\r | |
1946 | *ConfigUtilityCodeHeader = LocalConfigUtilityCodeHeader;\r | |
1947 | }\r | |
1948 | \r | |
1949 | if (RomImage != NULL) {\r | |
1950 | *RomImage = LocalRomImage;\r | |
1951 | }\r | |
1952 | \r | |
1953 | if (RomSize != NULL) {\r | |
1954 | *RomSize = LocalRomSize;\r | |
1955 | }\r | |
1956 | \r | |
1957 | return EFI_SUCCESS;\r | |
1958 | }\r | |
1959 | \r | |
1960 | /**\r | |
1961 | Load a legacy PC-AT OPROM on the PciHandle device. Return information\r | |
1962 | about how many disks were added by the OPROM and the shadow address and\r | |
1963 | size. DiskStart & DiskEnd are INT 13h drive letters. Thus 0x80 is C:\r | |
1964 | \r | |
1965 | @retval EFI_SUCCESS Legacy ROM loaded for this device\r | |
1966 | @retval EFI_NOT_FOUND No PS2 Keyboard found\r | |
1967 | \r | |
1968 | **/\r | |
1969 | EFI_STATUS\r | |
1970 | EnablePs2Keyboard (\r | |
1971 | VOID\r | |
1972 | )\r | |
1973 | {\r | |
1974 | EFI_STATUS Status;\r | |
1975 | EFI_HANDLE *HandleBuffer;\r | |
1976 | UINTN HandleCount;\r | |
1977 | EFI_ISA_IO_PROTOCOL *IsaIo;\r | |
1978 | UINTN Index;\r | |
1979 | \r | |
1980 | //\r | |
1981 | // Get SimpleTextIn and find PS2 controller\r | |
1982 | //\r | |
1983 | Status = gBS->LocateHandleBuffer (\r | |
1984 | ByProtocol,\r | |
1985 | &gEfiSimpleTextInProtocolGuid,\r | |
1986 | NULL,\r | |
1987 | &HandleCount,\r | |
1988 | &HandleBuffer\r | |
1989 | );\r | |
1990 | if (EFI_ERROR (Status)) {\r | |
1991 | return EFI_NOT_FOUND;\r | |
1992 | }\r | |
1993 | for (Index = 0; Index < HandleCount; Index++) {\r | |
1994 | //\r | |
1995 | // Open the IO Abstraction(s) needed to perform the supported test\r | |
1996 | //\r | |
1997 | Status = gBS->OpenProtocol (\r | |
1998 | HandleBuffer[Index],\r | |
1999 | &gEfiIsaIoProtocolGuid,\r | |
2000 | (VOID **) &IsaIo,\r | |
2001 | NULL,\r | |
2002 | HandleBuffer[Index],\r | |
2003 | EFI_OPEN_PROTOCOL_BY_HANDLE_PROTOCOL\r | |
2004 | );\r | |
2005 | \r | |
2006 | if (!EFI_ERROR (Status)) {\r | |
2007 | //\r | |
2008 | // Use the ISA I/O Protocol to see if Controller is the Keyboard\r | |
2009 | // controller\r | |
2010 | //\r | |
2011 | if (IsaIo->ResourceList->Device.HID != EISA_PNP_ID (0x303) || IsaIo->ResourceList->Device.UID != 0) {\r | |
2012 | Status = EFI_UNSUPPORTED;\r | |
2013 | }\r | |
2014 | \r | |
2015 | gBS->CloseProtocol (\r | |
2016 | HandleBuffer[Index],\r | |
2017 | &gEfiIsaIoProtocolGuid,\r | |
2018 | NULL,\r | |
2019 | HandleBuffer[Index]\r | |
2020 | );\r | |
2021 | }\r | |
2022 | \r | |
2023 | if (!EFI_ERROR (Status)) {\r | |
2024 | gBS->ConnectController (HandleBuffer[Index], NULL, NULL, FALSE);\r | |
2025 | }\r | |
2026 | }\r | |
2027 | FreePool (HandleBuffer);\r | |
2028 | return EFI_SUCCESS;\r | |
2029 | }\r | |
2030 | \r | |
2031 | \r | |
2032 | /**\r | |
2033 | Load a legacy PC-AT OpROM for VGA controller.\r | |
2034 | \r | |
2035 | @param Private Driver private data.\r | |
2036 | \r | |
2037 | @retval EFI_SUCCESS Legacy ROM successfully installed for this device.\r | |
2038 | @retval EFI_DEVICE_ERROR No VGA device handle found, or native EFI video\r | |
2039 | driver cannot be successfully disconnected, or VGA\r | |
2040 | thunk driver cannot be successfully connected.\r | |
2041 | \r | |
2042 | **/\r | |
2043 | EFI_STATUS\r | |
2044 | LegacyBiosInstallVgaRom (\r | |
2045 | IN LEGACY_BIOS_INSTANCE *Private\r | |
2046 | )\r | |
2047 | {\r | |
2048 | EFI_STATUS Status;\r | |
2049 | EFI_HANDLE VgaHandle;\r | |
2050 | UINTN HandleCount;\r | |
2051 | EFI_HANDLE *HandleBuffer;\r | |
2052 | EFI_HANDLE *ConnectHandleBuffer;\r | |
2053 | EFI_PCI_IO_PROTOCOL *PciIo;\r | |
2054 | PCI_TYPE00 PciConfigHeader;\r | |
2055 | UINT64 Supports;\r | |
2056 | EFI_OPEN_PROTOCOL_INFORMATION_ENTRY *OpenInfoBuffer;\r | |
2057 | UINTN EntryCount;\r | |
2058 | UINTN Index;\r | |
2059 | VOID *Interface;\r | |
2060 | \r | |
2061 | //\r | |
2062 | // EfiLegacyBiosGuild attached to a device implies that there is a legacy\r | |
2063 | // BIOS associated with that device.\r | |
2064 | //\r | |
2065 | // There are 3 cases to consider.\r | |
2066 | // Case 1: No EFI driver is controlling the video.\r | |
2067 | // Action: Return EFI_SUCCESS from DisconnectController, search\r | |
2068 | // video thunk driver, and connect it.\r | |
2069 | // Case 2: EFI driver is controlling the video and EfiLegacyBiosGuid is\r | |
2070 | // not on the image handle.\r | |
2071 | // Action: Disconnect EFI driver.\r | |
2072 | // ConnectController for video thunk\r | |
2073 | // Case 3: EFI driver is controlling the video and EfiLegacyBiosGuid is\r | |
2074 | // on the image handle.\r | |
2075 | // Action: Do nothing and set Private->VgaInstalled = TRUE.\r | |
2076 | // Then this routine is not called any more.\r | |
2077 | //\r | |
2078 | //\r | |
2079 | // Get the VGA device.\r | |
2080 | //\r | |
2081 | Status = Private->LegacyBiosPlatform->GetPlatformHandle (\r | |
2082 | Private->LegacyBiosPlatform,\r | |
2083 | EfiGetPlatformVgaHandle,\r | |
2084 | 0,\r | |
2085 | &HandleBuffer,\r | |
2086 | &HandleCount,\r | |
2087 | NULL\r | |
2088 | );\r | |
2089 | if (EFI_ERROR (Status)) {\r | |
2090 | return EFI_DEVICE_ERROR;\r | |
2091 | }\r | |
2092 | \r | |
2093 | VgaHandle = HandleBuffer[0];\r | |
2094 | \r | |
2095 | //\r | |
2096 | // Check whether video thunk driver already starts.\r | |
2097 | //\r | |
2098 | Status = gBS->OpenProtocolInformation (\r | |
2099 | VgaHandle,\r | |
2100 | &gEfiPciIoProtocolGuid,\r | |
2101 | &OpenInfoBuffer,\r | |
2102 | &EntryCount\r | |
2103 | );\r | |
2104 | if (EFI_ERROR (Status)) {\r | |
2105 | return Status;\r | |
2106 | }\r | |
2107 | \r | |
2108 | for (Index = 0; Index < EntryCount; Index++) {\r | |
2109 | if ((OpenInfoBuffer[Index].Attributes & EFI_OPEN_PROTOCOL_BY_DRIVER) != 0) {\r | |
2110 | Status = gBS->HandleProtocol (\r | |
2111 | OpenInfoBuffer[Index].AgentHandle,\r | |
2112 | &gEfiLegacyBiosGuid,\r | |
2113 | (VOID **) &Interface\r | |
2114 | );\r | |
2115 | if (!EFI_ERROR (Status)) {\r | |
2116 | //\r | |
2117 | // This should be video thunk driver which is managing video device\r | |
2118 | // So it need not start again\r | |
2119 | //\r | |
2120 | DEBUG ((EFI_D_INFO, "Video thunk driver already start! Return!\n"));\r | |
2121 | Private->VgaInstalled = TRUE;\r | |
2122 | return EFI_SUCCESS;\r | |
2123 | }\r | |
2124 | }\r | |
2125 | }\r | |
2126 | \r | |
2127 | //\r | |
2128 | // Kick off the native EFI driver\r | |
2129 | //\r | |
2130 | Status = gBS->DisconnectController (\r | |
2131 | VgaHandle,\r | |
2132 | NULL,\r | |
2133 | NULL\r | |
2134 | );\r | |
2135 | if (EFI_ERROR (Status)) {\r | |
2136 | if (Status != EFI_NOT_FOUND) {\r | |
2137 | return EFI_DEVICE_ERROR;\r | |
2138 | } else {\r | |
2139 | return Status;\r | |
2140 | }\r | |
2141 | }\r | |
2142 | //\r | |
2143 | // Find all the Thunk Driver\r | |
2144 | //\r | |
2145 | HandleBuffer = NULL;\r | |
2146 | Status = gBS->LocateHandleBuffer (\r | |
2147 | ByProtocol,\r | |
2148 | &gEfiLegacyBiosGuid,\r | |
2149 | NULL,\r | |
2150 | &HandleCount,\r | |
2151 | &HandleBuffer\r | |
2152 | );\r | |
2153 | ASSERT_EFI_ERROR (Status);\r | |
2154 | ConnectHandleBuffer = (EFI_HANDLE *) AllocatePool (sizeof (EFI_HANDLE) * (HandleCount + 1));\r | |
2155 | ASSERT (ConnectHandleBuffer != NULL);\r | |
2156 | \r | |
2157 | CopyMem (\r | |
2158 | ConnectHandleBuffer,\r | |
2159 | HandleBuffer,\r | |
2160 | sizeof (EFI_HANDLE) * HandleCount\r | |
2161 | );\r | |
2162 | ConnectHandleBuffer[HandleCount] = NULL;\r | |
2163 | \r | |
2164 | FreePool (HandleBuffer);\r | |
2165 | \r | |
2166 | //\r | |
2167 | // Enable the device and make sure VGA cycles are being forwarded to this VGA device\r | |
2168 | //\r | |
2169 | Status = gBS->HandleProtocol (\r | |
2170 | VgaHandle,\r | |
2171 | &gEfiPciIoProtocolGuid,\r | |
2172 | (VOID **) &PciIo\r | |
2173 | );\r | |
2174 | ASSERT_EFI_ERROR (Status);\r | |
2175 | PciIo->Pci.Read (\r | |
2176 | PciIo,\r | |
2177 | EfiPciIoWidthUint32,\r | |
2178 | 0,\r | |
2179 | sizeof (PciConfigHeader) / sizeof (UINT32),\r | |
2180 | &PciConfigHeader\r | |
2181 | );\r | |
2182 | \r | |
2183 | Status = PciIo->Attributes (\r | |
2184 | PciIo,\r | |
2185 | EfiPciIoAttributeOperationSupported,\r | |
2186 | 0,\r | |
2187 | &Supports\r | |
2188 | );\r | |
2189 | if (!EFI_ERROR (Status)) {\r | |
1a45b15e JF |
2190 | Supports &= (UINT64)(EFI_PCI_DEVICE_ENABLE | EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY | \\r |
2191 | EFI_PCI_IO_ATTRIBUTE_VGA_IO | EFI_PCI_IO_ATTRIBUTE_VGA_IO_16);\r | |
bcecde14 | 2192 | Status = PciIo->Attributes (\r |
2193 | PciIo,\r | |
2194 | EfiPciIoAttributeOperationEnable,\r | |
2195 | Supports,\r | |
2196 | NULL\r | |
2197 | );\r | |
2198 | }\r | |
2199 | \r | |
2200 | if (Status == EFI_SUCCESS) {\r | |
2201 | Private->VgaInstalled = TRUE;\r | |
2202 | \r | |
2203 | //\r | |
2204 | // Attach the VGA thunk driver.\r | |
2205 | // Assume the video is installed. This prevents potential of infinite recursion.\r | |
2206 | //\r | |
2207 | Status = gBS->ConnectController (\r | |
2208 | VgaHandle,\r | |
2209 | ConnectHandleBuffer,\r | |
2210 | NULL,\r | |
2211 | TRUE\r | |
2212 | );\r | |
2213 | }\r | |
2214 | \r | |
2215 | FreePool (ConnectHandleBuffer);\r | |
2216 | \r | |
2217 | if (EFI_ERROR (Status)) {\r | |
2218 | \r | |
2219 | Private->VgaInstalled = FALSE;\r | |
2220 | \r | |
2221 | //\r | |
2222 | // Reconnect the EFI VGA driver.\r | |
2223 | //\r | |
2224 | gBS->ConnectController (VgaHandle, NULL, NULL, TRUE);\r | |
2225 | return EFI_DEVICE_ERROR;\r | |
2226 | }\r | |
2227 | \r | |
2228 | return EFI_SUCCESS;\r | |
2229 | }\r | |
2230 | \r | |
2231 | \r | |
2232 | /**\r | |
2233 | Load a legacy PC-AT OpROM.\r | |
2234 | \r | |
2235 | @param This Protocol instance pointer.\r | |
2236 | @param Private Driver's private data.\r | |
2237 | @param PciHandle The EFI handle for the PCI device. It could be\r | |
2238 | NULL if the OpROM image is not associated with\r | |
2239 | any device.\r | |
2240 | @param OpromRevision The revision of PCI PC-AT ROM image.\r | |
2241 | @param RomImage Pointer to PCI PC-AT ROM image header. It must not\r | |
2242 | be NULL.\r | |
2243 | @param ImageSize Size of the PCI PC-AT ROM image.\r | |
2244 | @param RuntimeImageLength On input is the max runtime image length indicated by the PCIR structure\r | |
2245 | On output is the actual runtime image length\r | |
2246 | @param DiskStart Disk number of first device hooked by the ROM. If\r | |
2247 | DiskStart is the same as DiskEnd no disked were\r | |
2248 | hooked.\r | |
2249 | @param DiskEnd Disk number of the last device hooked by the ROM.\r | |
2250 | @param RomShadowAddress Shadow address of PC-AT ROM\r | |
2251 | \r | |
2252 | @retval EFI_SUCCESS Legacy ROM loaded for this device\r | |
2253 | @retval EFI_OUT_OF_RESOURCES No more space for this ROM\r | |
2254 | \r | |
2255 | **/\r | |
2256 | EFI_STATUS\r | |
2257 | EFIAPI\r | |
2258 | LegacyBiosInstallRom (\r | |
2259 | IN EFI_LEGACY_BIOS_PROTOCOL *This,\r | |
2260 | IN LEGACY_BIOS_INSTANCE *Private,\r | |
2261 | IN EFI_HANDLE PciHandle,\r | |
2262 | IN UINT8 OpromRevision,\r | |
2263 | IN VOID *RomImage,\r | |
2264 | IN UINTN ImageSize,\r | |
2265 | IN OUT UINTN *RuntimeImageLength,\r | |
2266 | OUT UINT8 *DiskStart, OPTIONAL\r | |
2267 | OUT UINT8 *DiskEnd, OPTIONAL\r | |
2268 | OUT VOID **RomShadowAddress OPTIONAL\r | |
2269 | )\r | |
2270 | {\r | |
2271 | EFI_STATUS Status;\r | |
2272 | EFI_STATUS PciEnableStatus;\r | |
2273 | EFI_PCI_IO_PROTOCOL *PciIo;\r | |
2274 | UINT8 LocalDiskStart;\r | |
2275 | UINT8 LocalDiskEnd;\r | |
2276 | UINTN Segment;\r | |
2277 | UINTN Bus;\r | |
2278 | UINTN Device;\r | |
2279 | UINTN Function;\r | |
2280 | EFI_IA32_REGISTER_SET Regs;\r | |
2281 | UINT8 VideoMode;\r | |
d057d8c4 | 2282 | UINT8 OldVideoMode;\r |
bcecde14 | 2283 | EFI_TIME BootTime;\r |
2284 | UINT32 *BdaPtr;\r | |
2285 | UINT32 LocalTime;\r | |
2286 | UINT32 StartBbsIndex;\r | |
2287 | UINT32 EndBbsIndex;\r | |
ff247afd | 2288 | UINT32 MaxRomAddr;\r |
bcecde14 | 2289 | UINTN TempData;\r |
2290 | UINTN InitAddress;\r | |
2291 | UINTN RuntimeAddress;\r | |
2292 | EFI_PHYSICAL_ADDRESS PhysicalAddress;\r | |
2293 | UINT32 Granularity;\r | |
2294 | \r | |
2295 | PciIo = NULL;\r | |
2296 | LocalDiskStart = 0;\r | |
2297 | LocalDiskEnd = 0;\r | |
2298 | Segment = 0;\r | |
2299 | Bus = 0;\r | |
2300 | Device = 0;\r | |
2301 | Function = 0;\r | |
2302 | VideoMode = 0;\r | |
d057d8c4 | 2303 | OldVideoMode = 0;\r |
bcecde14 | 2304 | PhysicalAddress = 0;\r |
ff247afd DW |
2305 | MaxRomAddr = PcdGet32 (PcdEndOpromShadowAddress);\r |
2306 | \r | |
2307 | if ((Private->Legacy16Table->TableLength >= OFFSET_OF(EFI_COMPATIBILITY16_TABLE, HiPermanentMemoryAddress)) &&\r | |
2308 | (Private->Legacy16Table->UmaAddress != 0) && \r | |
2309 | (Private->Legacy16Table->UmaSize != 0) &&\r | |
2310 | (MaxRomAddr > (Private->Legacy16Table->UmaAddress))) {\r | |
2311 | MaxRomAddr = Private->Legacy16Table->UmaAddress;\r | |
2312 | }\r | |
2313 | \r | |
bcecde14 | 2314 | \r |
2315 | PciProgramAllInterruptLineRegisters (Private);\r | |
2316 | \r | |
2317 | if ((OpromRevision >= 3) && (Private->Csm16PciInterfaceVersion >= 0x0300)) {\r | |
2318 | //\r | |
2319 | // CSM16 3.0 meets PCI 3.0 OpROM\r | |
2320 | // first test if there is enough space for its INIT code\r | |
2321 | //\r | |
2322 | PhysicalAddress = CONVENTIONAL_MEMORY_TOP;\r | |
2323 | Status = gBS->AllocatePages (\r | |
2324 | AllocateMaxAddress,\r | |
2325 | EfiBootServicesCode,\r | |
2326 | EFI_SIZE_TO_PAGES (ImageSize),\r | |
2327 | &PhysicalAddress\r | |
2328 | );\r | |
2329 | \r | |
2330 | if (EFI_ERROR (Status)) {\r | |
2331 | DEBUG ((EFI_D_ERROR, "return LegacyBiosInstallRom(%d): EFI_OUT_OF_RESOURCES (no more space for OpROM)\n", __LINE__));\r | |
cb38c322 | 2332 | //\r |
2333 | // Report Status Code to indicate that there is no enough space for OpROM\r | |
2334 | //\r | |
2335 | REPORT_STATUS_CODE (\r | |
2336 | EFI_ERROR_CODE | EFI_ERROR_MINOR,\r | |
2337 | (EFI_SOFTWARE_DXE_BS_DRIVER | EFI_SW_DXE_BS_EC_LEGACY_OPROM_NO_SPACE)\r | |
2338 | );\r | |
bcecde14 | 2339 | return EFI_OUT_OF_RESOURCES;\r |
2340 | }\r | |
2341 | InitAddress = (UINTN) PhysicalAddress;\r | |
2342 | //\r | |
2343 | // then test if there is enough space for its RT code\r | |
2344 | //\r | |
2345 | RuntimeAddress = Private->OptionRom;\r | |
ff247afd | 2346 | if (RuntimeAddress + *RuntimeImageLength > MaxRomAddr) {\r |
bcecde14 | 2347 | DEBUG ((EFI_D_ERROR, "return LegacyBiosInstallRom(%d): EFI_OUT_OF_RESOURCES (no more space for OpROM)\n", __LINE__));\r |
2348 | gBS->FreePages (PhysicalAddress, EFI_SIZE_TO_PAGES (ImageSize));\r | |
cb38c322 | 2349 | //\r |
2350 | // Report Status Code to indicate that there is no enough space for OpROM\r | |
2351 | //\r | |
2352 | REPORT_STATUS_CODE (\r | |
2353 | EFI_ERROR_CODE | EFI_ERROR_MINOR,\r | |
2354 | (EFI_SOFTWARE_DXE_BS_DRIVER | EFI_SW_DXE_BS_EC_LEGACY_OPROM_NO_SPACE)\r | |
2355 | );\r | |
bcecde14 | 2356 | return EFI_OUT_OF_RESOURCES;\r |
2357 | }\r | |
2358 | } else {\r | |
2359 | // CSM16 3.0 meets PCI 2.x OpROM\r | |
2360 | // CSM16 2.x meets PCI 2.x/3.0 OpROM\r | |
2361 | // test if there is enough space for its INIT code\r | |
2362 | //\r | |
2363 | InitAddress = PCI_START_ADDRESS (Private->OptionRom);\r | |
ff247afd | 2364 | if (InitAddress + ImageSize > MaxRomAddr) {\r |
bcecde14 | 2365 | DEBUG ((EFI_D_ERROR, "return LegacyBiosInstallRom(%d): EFI_OUT_OF_RESOURCES (no more space for OpROM)\n", __LINE__));\r |
cb38c322 | 2366 | //\r |
2367 | // Report Status Code to indicate that there is no enough space for OpROM\r | |
2368 | //\r | |
2369 | REPORT_STATUS_CODE (\r | |
2370 | EFI_ERROR_CODE | EFI_ERROR_MINOR,\r | |
2371 | (EFI_SOFTWARE_DXE_BS_DRIVER | EFI_SW_DXE_BS_EC_LEGACY_OPROM_NO_SPACE)\r | |
2372 | );\r | |
bcecde14 | 2373 | return EFI_OUT_OF_RESOURCES;\r |
2374 | }\r | |
2375 | \r | |
2376 | RuntimeAddress = InitAddress;\r | |
2377 | }\r | |
2378 | \r | |
2379 | Private->LegacyRegion->UnLock (\r | |
2380 | Private->LegacyRegion,\r | |
2381 | 0xE0000,\r | |
2382 | 0x20000,\r | |
2383 | &Granularity\r | |
2384 | );\r | |
2385 | \r | |
2386 | Private->LegacyRegion->UnLock (\r | |
2387 | Private->LegacyRegion,\r | |
2388 | (UINT32) RuntimeAddress,\r | |
2389 | (UINT32) ImageSize,\r | |
2390 | &Granularity\r | |
2391 | );\r | |
2392 | \r | |
2393 | DEBUG ((EFI_D_INFO, " Shadowing OpROM init/runtime/isize = %x/%x/%x\n", InitAddress, RuntimeAddress, ImageSize));\r | |
2394 | \r | |
2395 | CopyMem ((VOID *) InitAddress, RomImage, ImageSize);\r | |
2396 | \r | |
2397 | //\r | |
2398 | // Read the highest disk number "installed: and assume a new disk will\r | |
2399 | // show up on the first drive past the current value.\r | |
2400 | // There are several considerations here:\r | |
2401 | // 1. Non-BBS compliant drives will change 40:75 but 16-bit CSM will undo\r | |
2402 | // the change until boot selection time frame.\r | |
2403 | // 2. BBS compliants drives will not change 40:75 until boot time.\r | |
2404 | // 3. Onboard IDE controllers will change 40:75\r | |
2405 | //\r | |
2ea3576e JW |
2406 | ACCESS_PAGE0_CODE (\r |
2407 | LocalDiskStart = (UINT8) ((*(UINT8 *) ((UINTN) 0x475)) + 0x80);\r | |
2408 | if ((Private->Disk4075 + 0x80) < LocalDiskStart) {\r | |
2409 | //\r | |
2410 | // Update table since onboard IDE drives found\r | |
2411 | //\r | |
2412 | Private->LegacyEfiHddTable[Private->LegacyEfiHddTableIndex].PciSegment = 0xff;\r | |
2413 | Private->LegacyEfiHddTable[Private->LegacyEfiHddTableIndex].PciBus = 0xff;\r | |
2414 | Private->LegacyEfiHddTable[Private->LegacyEfiHddTableIndex].PciDevice = 0xff;\r | |
2415 | Private->LegacyEfiHddTable[Private->LegacyEfiHddTableIndex].PciFunction = 0xff;\r | |
2416 | Private->LegacyEfiHddTable[Private->LegacyEfiHddTableIndex].StartDriveNumber = (UINT8) (Private->Disk4075 + 0x80);\r | |
2417 | Private->LegacyEfiHddTable[Private->LegacyEfiHddTableIndex].EndDriveNumber = LocalDiskStart;\r | |
2418 | Private->LegacyEfiHddTableIndex ++;\r | |
2419 | Private->Disk4075 = (UINT8) (LocalDiskStart & 0x7f);\r | |
2420 | Private->DiskEnd = LocalDiskStart;\r | |
2421 | }\r | |
bcecde14 | 2422 | \r |
2ea3576e | 2423 | if (PciHandle != mVgaHandle) {\r |
bcecde14 | 2424 | \r |
2ea3576e | 2425 | EnablePs2Keyboard ();\r |
d057d8c4 | 2426 | \r |
2ea3576e JW |
2427 | //\r |
2428 | // Store current mode settings since PrepareToScanRom may change mode.\r | |
2429 | //\r | |
2430 | VideoMode = *(UINT8 *) ((UINTN) (0x400 + BDA_VIDEO_MODE));\r | |
2431 | }\r | |
2432 | );\r | |
d057d8c4 | 2433 | \r |
bcecde14 | 2434 | //\r |
2435 | // Notify the platform that we are about to scan the ROM\r | |
2436 | //\r | |
2437 | Status = Private->LegacyBiosPlatform->PlatformHooks (\r | |
2438 | Private->LegacyBiosPlatform,\r | |
2439 | EfiPlatformHookPrepareToScanRom,\r | |
2440 | 0,\r | |
2441 | PciHandle,\r | |
2442 | &InitAddress,\r | |
2443 | NULL,\r | |
2444 | NULL\r | |
2445 | );\r | |
2446 | \r | |
2447 | //\r | |
2448 | // If Status returned is EFI_UNSUPPORTED then abort due to platform\r | |
2449 | // policy.\r | |
2450 | //\r | |
2451 | if (Status == EFI_UNSUPPORTED) {\r | |
2452 | goto Done;\r | |
2453 | }\r | |
2454 | \r | |
2455 | //\r | |
2456 | // Report corresponding status code\r | |
2457 | //\r | |
2458 | REPORT_STATUS_CODE (\r | |
2459 | EFI_PROGRESS_CODE,\r | |
2460 | (EFI_SOFTWARE_DXE_BS_DRIVER | EFI_SW_CSM_LEGACY_ROM_INIT)\r | |
2461 | );\r | |
2462 | \r | |
2463 | //\r | |
2464 | // Generate number of ticks since midnight for BDA. Some OPROMs require\r | |
2465 | // this. Place result in 40:6C-6F\r | |
2466 | //\r | |
2467 | gRT->GetTime (&BootTime, NULL);\r | |
2468 | LocalTime = BootTime.Hour * 3600 + BootTime.Minute * 60 + BootTime.Second;\r | |
2469 | \r | |
2470 | //\r | |
2471 | // Multiply result by 18.2 for number of ticks since midnight.\r | |
2472 | // Use 182/10 to avoid floating point math.\r | |
2473 | //\r | |
2ea3576e JW |
2474 | ACCESS_PAGE0_CODE (\r |
2475 | LocalTime = (LocalTime * 182) / 10;\r | |
2476 | BdaPtr = (UINT32 *) ((UINTN) 0x46C);\r | |
2477 | *BdaPtr = LocalTime;\r | |
2478 | );\r | |
bcecde14 | 2479 | \r |
2480 | //\r | |
2481 | // Pass in handoff data\r | |
2482 | //\r | |
2483 | PciEnableStatus = EFI_UNSUPPORTED;\r | |
2484 | ZeroMem (&Regs, sizeof (Regs));\r | |
2485 | if (PciHandle != NULL) {\r | |
2486 | \r | |
2487 | Status = gBS->HandleProtocol (\r | |
2488 | PciHandle,\r | |
2489 | &gEfiPciIoProtocolGuid,\r | |
2490 | (VOID **) &PciIo\r | |
2491 | );\r | |
2492 | ASSERT_EFI_ERROR (Status);\r | |
2493 | \r | |
2494 | //\r | |
2495 | // Enable command register.\r | |
2496 | //\r | |
2497 | PciEnableStatus = PciIo->Attributes (\r | |
2498 | PciIo,\r | |
2499 | EfiPciIoAttributeOperationEnable,\r | |
2500 | EFI_PCI_DEVICE_ENABLE,\r | |
2501 | NULL\r | |
2502 | );\r | |
2503 | \r | |
2504 | PciIo->GetLocation (\r | |
2505 | PciIo,\r | |
2506 | &Segment,\r | |
2507 | &Bus,\r | |
2508 | &Device,\r | |
2509 | &Function\r | |
2510 | );\r | |
2511 | DEBUG ((EFI_D_INFO, "Shadowing OpROM on the PCI device %x/%x/%x\n", Bus, Device, Function));\r | |
2512 | }\r | |
2513 | \r | |
2514 | mIgnoreBbsUpdateFlag = FALSE;\r | |
2515 | Regs.X.AX = Legacy16DispatchOprom;\r | |
2516 | \r | |
2517 | //\r | |
2518 | // Generate DispatchOpRomTable data\r | |
2519 | //\r | |
2520 | Private->IntThunk->DispatchOpromTable.PnPInstallationCheckSegment = Private->Legacy16Table->PnPInstallationCheckSegment;\r | |
2521 | Private->IntThunk->DispatchOpromTable.PnPInstallationCheckOffset = Private->Legacy16Table->PnPInstallationCheckOffset;\r | |
2522 | Private->IntThunk->DispatchOpromTable.OpromSegment = (UINT16) (InitAddress >> 4);\r | |
2523 | Private->IntThunk->DispatchOpromTable.PciBus = (UINT8) Bus;\r | |
2524 | Private->IntThunk->DispatchOpromTable.PciDeviceFunction = (UINT8) ((Device << 3) | Function);\r | |
2525 | Private->IntThunk->DispatchOpromTable.NumberBbsEntries = (UINT8) Private->IntThunk->EfiToLegacy16BootTable.NumberBbsEntries;\r | |
2526 | Private->IntThunk->DispatchOpromTable.BbsTablePointer = (UINT32) (UINTN) Private->BbsTablePtr;\r | |
2527 | Private->IntThunk->DispatchOpromTable.RuntimeSegment = (UINT16)((OpromRevision < 3) ? 0xffff : (RuntimeAddress >> 4));\r | |
2528 | TempData = (UINTN) &Private->IntThunk->DispatchOpromTable;\r | |
2529 | Regs.X.ES = EFI_SEGMENT ((UINT32) TempData);\r | |
2530 | Regs.X.BX = EFI_OFFSET ((UINT32) TempData);\r | |
2531 | //\r | |
2532 | // Skip dispatching ROM for those PCI devices that can not be enabled by PciIo->Attributes\r | |
2533 | // Otherwise, it may cause the system to hang in some cases\r | |
2534 | //\r | |
2535 | if (!EFI_ERROR (PciEnableStatus)) {\r | |
2536 | DEBUG ((EFI_D_INFO, " Legacy16DispatchOprom - %02x/%02x/%02x\n", Bus, Device, Function));\r | |
2537 | Private->LegacyBios.FarCall86 (\r | |
2538 | &Private->LegacyBios,\r | |
2539 | Private->Legacy16CallSegment,\r | |
2540 | Private->Legacy16CallOffset,\r | |
2541 | &Regs,\r | |
2542 | NULL,\r | |
2543 | 0\r | |
2544 | );\r | |
2545 | } else {\r | |
2546 | Regs.X.BX = 0;\r | |
2547 | }\r | |
2548 | \r | |
2549 | if (Private->IntThunk->DispatchOpromTable.NumberBbsEntries != (UINT8) Private->IntThunk->EfiToLegacy16BootTable.NumberBbsEntries) {\r | |
2550 | Private->IntThunk->EfiToLegacy16BootTable.NumberBbsEntries = (UINT8) Private->IntThunk->DispatchOpromTable.NumberBbsEntries;\r | |
2551 | mIgnoreBbsUpdateFlag = TRUE;\r | |
2552 | }\r | |
2553 | //\r | |
2554 | // Check if non-BBS compliant drives found\r | |
2555 | //\r | |
2556 | if (Regs.X.BX != 0) {\r | |
2557 | LocalDiskEnd = (UINT8) (LocalDiskStart + Regs.H.BL);\r | |
2558 | Private->LegacyEfiHddTable[Private->LegacyEfiHddTableIndex].PciSegment = (UINT8) Segment;\r | |
2559 | Private->LegacyEfiHddTable[Private->LegacyEfiHddTableIndex].PciBus = (UINT8) Bus;\r | |
2560 | Private->LegacyEfiHddTable[Private->LegacyEfiHddTableIndex].PciDevice = (UINT8) Device;\r | |
2561 | Private->LegacyEfiHddTable[Private->LegacyEfiHddTableIndex].PciFunction = (UINT8) Function;\r | |
2562 | Private->LegacyEfiHddTable[Private->LegacyEfiHddTableIndex].StartDriveNumber = Private->DiskEnd;\r | |
2563 | Private->DiskEnd = LocalDiskEnd;\r | |
2564 | Private->LegacyEfiHddTable[Private->LegacyEfiHddTableIndex].EndDriveNumber = Private->DiskEnd;\r | |
2565 | Private->LegacyEfiHddTableIndex += 1;\r | |
2566 | }\r | |
2567 | //\r | |
2568 | // Skip video mode set, if installing VGA\r | |
2569 | //\r | |
2570 | if (PciHandle != mVgaHandle) {\r | |
2571 | //\r | |
2572 | // Set mode settings since PrepareToScanRom may change mode\r | |
2573 | //\r | |
2ea3576e JW |
2574 | ACCESS_PAGE0_CODE ({\r |
2575 | OldVideoMode = *(UINT8 *) ((UINTN) (0x400 + BDA_VIDEO_MODE));\r | |
2576 | });\r | |
d057d8c4 JW |
2577 | \r |
2578 | if (VideoMode != OldVideoMode) {\r | |
edf4af6f | 2579 | //\r |
2580 | // The active video mode is changed, restore it to original mode.\r | |
2581 | //\r | |
2582 | Regs.H.AH = 0x00;\r | |
2583 | Regs.H.AL = VideoMode;\r | |
2584 | Private->LegacyBios.Int86 (&Private->LegacyBios, 0x10, &Regs);\r | |
2585 | }\r | |
bcecde14 | 2586 | }\r |
2587 | //\r | |
2588 | // Regs.X.AX from the adapter initializion is ignored since some adapters\r | |
2589 | // do not follow the standard of setting AX = 0 on success.\r | |
2590 | //\r | |
2591 | //\r | |
2592 | // The ROM could have updated it's size so we need to read again.\r | |
2593 | //\r | |
22921b02 | 2594 | if (((EFI_LEGACY_EXPANSION_ROM_HEADER *) RuntimeAddress)->Signature != PCI_EXPANSION_ROM_HEADER_SIGNATURE) {\r |
7f446eba | 2595 | //\r |
22921b02 | 2596 | // Now we check the signature (0xaa55) to judge whether the run-time code is truly generated by INIT function.\r |
2597 | // If signature is not valid, that means the INIT function didn't copy the run-time code to RuntimeAddress.\r | |
7f446eba RN |
2598 | //\r |
2599 | *RuntimeImageLength = 0;\r | |
2600 | } else {\r | |
2601 | *RuntimeImageLength = ((EFI_LEGACY_EXPANSION_ROM_HEADER *) RuntimeAddress)->Size512 * 512;\r | |
2602 | }\r | |
2603 | \r | |
bcecde14 | 2604 | DEBUG ((EFI_D_INFO, " fsize = %x\n", *RuntimeImageLength));\r |
2605 | \r | |
2606 | //\r | |
2607 | // If OpROM runs in 2.0 mode\r | |
2608 | //\r | |
2609 | if (PhysicalAddress == 0) {\r | |
2610 | if (*RuntimeImageLength < ImageSize) {\r | |
2611 | //\r | |
2612 | // Make area from end of shadowed rom to end of original rom all ffs\r | |
2613 | //\r | |
2614 | gBS->SetMem ((VOID *) (InitAddress + *RuntimeImageLength), ImageSize - *RuntimeImageLength, 0xff);\r | |
2615 | }\r | |
2616 | }\r | |
2617 | \r | |
2ea3576e JW |
2618 | ACCESS_PAGE0_CODE (\r |
2619 | LocalDiskEnd = (UINT8) ((*(UINT8 *) ((UINTN) 0x475)) + 0x80);\r | |
2620 | );\r | |
bcecde14 | 2621 | \r |
2622 | //\r | |
2623 | // Allow platform to perform any required actions after the\r | |
2624 | // OPROM has been initialized.\r | |
2625 | //\r | |
2626 | Status = Private->LegacyBiosPlatform->PlatformHooks (\r | |
2627 | Private->LegacyBiosPlatform,\r | |
2628 | EfiPlatformHookAfterRomInit,\r | |
2629 | 0,\r | |
2630 | PciHandle,\r | |
2631 | &RuntimeAddress,\r | |
2632 | NULL,\r | |
2633 | NULL\r | |
2634 | );\r | |
2635 | if (PciHandle != NULL) {\r | |
2636 | //\r | |
2637 | // If no PCI Handle then no header or Bevs.\r | |
2638 | //\r | |
2639 | if ((*RuntimeImageLength != 0) && (!mIgnoreBbsUpdateFlag)) {\r | |
2640 | StartBbsIndex = Private->IntThunk->EfiToLegacy16BootTable.NumberBbsEntries;\r | |
2641 | TempData = RuntimeAddress;\r | |
2642 | UpdateBevBcvTable (\r | |
2643 | Private,\r | |
2644 | (EFI_LEGACY_EXPANSION_ROM_HEADER *) TempData,\r | |
2645 | PciIo\r | |
2646 | );\r | |
2647 | EndBbsIndex = Private->IntThunk->EfiToLegacy16BootTable.NumberBbsEntries;\r | |
2648 | LocalDiskEnd = (UINT8) (LocalDiskStart + (UINT8) (EndBbsIndex - StartBbsIndex));\r | |
2649 | if (LocalDiskEnd != LocalDiskStart) {\r | |
2650 | Private->LegacyEfiHddTable[Private->LegacyEfiHddTableIndex].PciSegment = (UINT8) Segment;\r | |
2651 | Private->LegacyEfiHddTable[Private->LegacyEfiHddTableIndex].PciBus = (UINT8) Bus;\r | |
2652 | Private->LegacyEfiHddTable[Private->LegacyEfiHddTableIndex].PciDevice = (UINT8) Device;\r | |
2653 | Private->LegacyEfiHddTable[Private->LegacyEfiHddTableIndex].PciFunction = (UINT8) Function;\r | |
2654 | Private->LegacyEfiHddTable[Private->LegacyEfiHddTableIndex].StartDriveNumber = Private->DiskEnd;\r | |
2655 | Private->DiskEnd = LocalDiskEnd;\r | |
2656 | Private->LegacyEfiHddTable[Private->LegacyEfiHddTableIndex].EndDriveNumber = Private->DiskEnd;\r | |
2657 | Private->LegacyEfiHddTableIndex += 1;\r | |
2658 | }\r | |
2659 | }\r | |
2660 | //\r | |
2661 | // Mark PCI device as having a legacy BIOS ROM loaded.\r | |
2662 | //\r | |
2663 | RomShadow (\r | |
2664 | PciHandle,\r | |
2665 | (UINT32) RuntimeAddress,\r | |
2666 | (UINT32) *RuntimeImageLength,\r | |
2667 | LocalDiskStart,\r | |
2668 | LocalDiskEnd\r | |
2669 | );\r | |
2670 | }\r | |
2671 | \r | |
2672 | //\r | |
2673 | // Stuff caller's OPTIONAL return parameters.\r | |
2674 | //\r | |
2675 | if (RomShadowAddress != NULL) {\r | |
2676 | *RomShadowAddress = (VOID *) RuntimeAddress;\r | |
2677 | }\r | |
2678 | \r | |
2679 | if (DiskStart != NULL) {\r | |
2680 | *DiskStart = LocalDiskStart;\r | |
2681 | }\r | |
2682 | \r | |
2683 | if (DiskEnd != NULL) {\r | |
2684 | *DiskEnd = LocalDiskEnd;\r | |
2685 | }\r | |
2686 | \r | |
2687 | Private->OptionRom = (UINT32) (RuntimeAddress + *RuntimeImageLength);\r | |
2688 | \r | |
2689 | Status = EFI_SUCCESS;\r | |
2690 | \r | |
2691 | Done:\r | |
2692 | if (PhysicalAddress != 0) {\r | |
2693 | //\r | |
2694 | // Free pages when OpROM is 3.0\r | |
2695 | //\r | |
2696 | gBS->FreePages (PhysicalAddress, EFI_SIZE_TO_PAGES (ImageSize));\r | |
2697 | }\r | |
2698 | \r | |
2699 | //\r | |
2700 | // Insure all shadowed areas are locked\r | |
2701 | //\r | |
2702 | Private->LegacyRegion->Lock (\r | |
2703 | Private->LegacyRegion,\r | |
2704 | 0xC0000,\r | |
2705 | 0x40000,\r | |
2706 | &Granularity\r | |
2707 | );\r | |
2708 | \r | |
2709 | return Status;\r | |
2710 | }\r | |
2711 | \r | |
60794ee6 JY |
2712 | /**\r |
2713 | Let IOMMU grant DMA access for the PCI device.\r | |
2714 | \r | |
2715 | @param PciHandle The EFI handle for the PCI device.\r | |
2716 | @param HostAddress The system memory address to map to the PCI controller.\r | |
2717 | @param NumberOfBytes The number of bytes to map.\r | |
2718 | \r | |
2719 | @retval EFI_SUCCESS The DMA access is granted.\r | |
2720 | **/\r | |
2721 | EFI_STATUS\r | |
2722 | IoMmuGrantAccess (\r | |
2723 | IN EFI_HANDLE PciHandle,\r | |
2724 | IN EFI_PHYSICAL_ADDRESS HostAddress,\r | |
2725 | IN UINTN NumberOfBytes\r | |
2726 | )\r | |
2727 | {\r | |
2728 | EFI_PHYSICAL_ADDRESS DeviceAddress;\r | |
2729 | VOID *Mapping;\r | |
2730 | EFI_STATUS Status;\r | |
2731 | \r | |
2732 | if (PciHandle == NULL) {\r | |
2733 | return EFI_UNSUPPORTED;\r | |
2734 | }\r | |
2735 | \r | |
2736 | Status = EFI_SUCCESS;\r | |
2737 | if (mIoMmu == NULL) {\r | |
2738 | gBS->LocateProtocol (&gEdkiiIoMmuProtocolGuid, NULL, (VOID **)&mIoMmu);\r | |
2739 | }\r | |
2740 | if (mIoMmu != NULL) {\r | |
2741 | Status = mIoMmu->Map (\r | |
2742 | mIoMmu,\r | |
2743 | EdkiiIoMmuOperationBusMasterCommonBuffer,\r | |
2744 | (VOID *)(UINTN)HostAddress,\r | |
2745 | &NumberOfBytes,\r | |
2746 | &DeviceAddress,\r | |
2747 | &Mapping\r | |
2748 | );\r | |
2749 | if (EFI_ERROR(Status)) {\r | |
2750 | DEBUG ((DEBUG_ERROR, "LegacyPci - IoMmuMap - %r\n", Status));\r | |
2751 | } else {\r | |
2752 | ASSERT (DeviceAddress == HostAddress);\r | |
2753 | Status = mIoMmu->SetAttribute (\r | |
2754 | mIoMmu,\r | |
2755 | PciHandle,\r | |
2756 | Mapping,\r | |
2757 | EDKII_IOMMU_ACCESS_READ | EDKII_IOMMU_ACCESS_WRITE\r | |
2758 | );\r | |
2759 | if (EFI_ERROR(Status)) {\r | |
2760 | DEBUG ((DEBUG_ERROR, "LegacyPci - IoMmuSetAttribute - %r\n", Status));\r | |
2761 | }\r | |
2762 | }\r | |
2763 | }\r | |
2764 | return Status;\r | |
2765 | }\r | |
2766 | \r | |
bcecde14 | 2767 | /**\r |
2768 | Load a legacy PC-AT OPROM on the PciHandle device. Return information\r | |
2769 | about how many disks were added by the OPROM and the shadow address and\r | |
2770 | size. DiskStart & DiskEnd are INT 13h drive letters. Thus 0x80 is C:\r | |
2771 | \r | |
2772 | @param This Protocol instance pointer.\r | |
2773 | @param PciHandle The PCI PC-AT OPROM from this devices ROM BAR will\r | |
2774 | be loaded. This value is NULL if RomImage is\r | |
2775 | non-NULL. This is the normal case.\r | |
2776 | @param RomImage A PCI PC-AT ROM image. This argument is non-NULL\r | |
2777 | if there is no hardware associated with the ROM\r | |
2778 | and thus no PciHandle, otherwise is must be NULL.\r | |
2779 | Example is PXE base code.\r | |
2780 | @param Flags Indicates if ROM found and if PC-AT.\r | |
2781 | @param DiskStart Disk number of first device hooked by the ROM. If\r | |
2782 | DiskStart is the same as DiskEnd no disked were\r | |
2783 | hooked.\r | |
2784 | @param DiskEnd Disk number of the last device hooked by the ROM.\r | |
2785 | @param RomShadowAddress Shadow address of PC-AT ROM\r | |
2786 | @param RomShadowedSize Size of RomShadowAddress in bytes\r | |
2787 | \r | |
2788 | @retval EFI_SUCCESS Legacy ROM loaded for this device\r | |
2789 | @retval EFI_INVALID_PARAMETER PciHandle not found\r | |
2790 | @retval EFI_UNSUPPORTED There is no PCI ROM in the ROM BAR or no onboard\r | |
2791 | ROM\r | |
2792 | \r | |
2793 | **/\r | |
2794 | EFI_STATUS\r | |
2795 | EFIAPI\r | |
2796 | LegacyBiosInstallPciRom (\r | |
2797 | IN EFI_LEGACY_BIOS_PROTOCOL * This,\r | |
2798 | IN EFI_HANDLE PciHandle,\r | |
2799 | IN VOID **RomImage,\r | |
2800 | OUT UINTN *Flags,\r | |
2801 | OUT UINT8 *DiskStart, OPTIONAL\r | |
2802 | OUT UINT8 *DiskEnd, OPTIONAL\r | |
2803 | OUT VOID **RomShadowAddress, OPTIONAL\r | |
2804 | OUT UINT32 *RomShadowedSize OPTIONAL\r | |
2805 | )\r | |
2806 | {\r | |
2807 | EFI_STATUS Status;\r | |
2808 | LEGACY_BIOS_INSTANCE *Private;\r | |
2809 | VOID *LocalRomImage;\r | |
2810 | UINTN ImageSize;\r | |
2811 | UINTN RuntimeImageLength;\r | |
2812 | EFI_PCI_IO_PROTOCOL *PciIo;\r | |
2813 | PCI_TYPE01 PciConfigHeader;\r | |
2814 | UINTN HandleCount;\r | |
2815 | EFI_HANDLE *HandleBuffer;\r | |
2816 | UINTN PciSegment;\r | |
2817 | UINTN PciBus;\r | |
2818 | UINTN PciDevice;\r | |
2819 | UINTN PciFunction;\r | |
2820 | UINTN LastBus;\r | |
2821 | UINTN Index;\r | |
2822 | UINT8 OpromRevision;\r | |
2823 | UINT32 Granularity;\r | |
2824 | PCI_3_0_DATA_STRUCTURE *Pcir;\r | |
2825 | \r | |
2826 | OpromRevision = 0;\r | |
2827 | \r | |
2828 | Private = LEGACY_BIOS_INSTANCE_FROM_THIS (This);\r | |
2829 | if (Private->Legacy16Table->LastPciBus == 0) {\r | |
2830 | //\r | |
2831 | // Get last bus number if not already found\r | |
2832 | //\r | |
2833 | Status = gBS->LocateHandleBuffer (\r | |
2834 | ByProtocol,\r | |
2835 | &gEfiPciIoProtocolGuid,\r | |
2836 | NULL,\r | |
2837 | &HandleCount,\r | |
2838 | &HandleBuffer\r | |
2839 | );\r | |
2840 | \r | |
2841 | LastBus = 0;\r | |
2842 | for (Index = 0; Index < HandleCount; Index++) {\r | |
2843 | Status = gBS->HandleProtocol (\r | |
2844 | HandleBuffer[Index],\r | |
2845 | &gEfiPciIoProtocolGuid,\r | |
2846 | (VOID **) &PciIo\r | |
2847 | );\r | |
2848 | if (EFI_ERROR (Status)) {\r | |
2849 | continue;\r | |
2850 | }\r | |
2851 | \r | |
2852 | Status = PciIo->GetLocation (\r | |
2853 | PciIo,\r | |
2854 | &PciSegment,\r | |
2855 | &PciBus,\r | |
2856 | &PciDevice,\r | |
2857 | &PciFunction\r | |
2858 | );\r | |
2859 | if (PciBus > LastBus) {\r | |
2860 | LastBus = PciBus;\r | |
2861 | }\r | |
2862 | }\r | |
2863 | \r | |
2864 | Private->LegacyRegion->UnLock (\r | |
2865 | Private->LegacyRegion,\r | |
2866 | 0xE0000,\r | |
2867 | 0x20000,\r | |
2868 | &Granularity\r | |
2869 | );\r | |
2870 | Private->Legacy16Table->LastPciBus = (UINT8) LastBus;\r | |
2871 | Private->LegacyRegion->Lock (\r | |
2872 | Private->LegacyRegion,\r | |
2873 | 0xE0000,\r | |
2874 | 0x20000,\r | |
2875 | &Granularity\r | |
2876 | );\r | |
2877 | }\r | |
2878 | \r | |
2879 | *Flags = 0;\r | |
2880 | if ((PciHandle != NULL) && (RomImage == NULL)) {\r | |
2881 | //\r | |
2882 | // If PciHandle has OpRom to Execute \r | |
2883 | // and OpRom are all associated with Hardware\r | |
2884 | //\r | |
2885 | Status = gBS->HandleProtocol (\r | |
2886 | PciHandle,\r | |
2887 | &gEfiPciIoProtocolGuid,\r | |
2888 | (VOID **) &PciIo\r | |
2889 | );\r | |
2890 | \r | |
2891 | if (!EFI_ERROR (Status)) {\r | |
2892 | PciIo->Pci.Read (\r | |
2893 | PciIo,\r | |
2894 | EfiPciIoWidthUint32,\r | |
2895 | 0,\r | |
2896 | sizeof (PciConfigHeader) / sizeof (UINT32),\r | |
2897 | &PciConfigHeader\r | |
2898 | );\r | |
2899 | \r | |
2900 | //\r | |
2901 | // if video installed & OPROM is video return\r | |
2902 | //\r | |
2903 | if (\r | |
2904 | (\r | |
2905 | ((PciConfigHeader.Hdr.ClassCode[2] == PCI_CLASS_OLD) &&\r | |
2906 | (PciConfigHeader.Hdr.ClassCode[1] == PCI_CLASS_OLD_VGA))\r | |
2907 | ||\r | |
2908 | ((PciConfigHeader.Hdr.ClassCode[2] == PCI_CLASS_DISPLAY) &&\r | |
2909 | (PciConfigHeader.Hdr.ClassCode[1] == PCI_CLASS_DISPLAY_VGA))\r | |
2910 | )\r | |
2911 | &&\r | |
2912 | (!Private->VgaInstalled)\r | |
2913 | ) {\r | |
2914 | mVgaInstallationInProgress = TRUE;\r | |
2915 | \r | |
2916 | //\r | |
2917 | // return EFI_UNSUPPORTED;\r | |
2918 | //\r | |
2919 | }\r | |
2920 | }\r | |
2921 | //\r | |
2922 | // To run any legacy image, the VGA needs to be installed first.\r | |
2923 | // if installing the video, then don't need the thunk as already installed.\r | |
2924 | //\r | |
2925 | Status = Private->LegacyBiosPlatform->GetPlatformHandle (\r | |
2926 | Private->LegacyBiosPlatform,\r | |
2927 | EfiGetPlatformVgaHandle,\r | |
2928 | 0,\r | |
2929 | &HandleBuffer,\r | |
2930 | &HandleCount,\r | |
2931 | NULL\r | |
2932 | );\r | |
2933 | \r | |
2934 | if (!EFI_ERROR (Status)) {\r | |
2935 | mVgaHandle = HandleBuffer[0];\r | |
2936 | if ((!Private->VgaInstalled) && (PciHandle != mVgaHandle)) {\r | |
2937 | //\r | |
2938 | // A return status of EFI_NOT_FOUND is considered valid (No EFI\r | |
2939 | // driver is controlling video.\r | |
2940 | //\r | |
2941 | mVgaInstallationInProgress = TRUE;\r | |
2942 | Status = LegacyBiosInstallVgaRom (Private);\r | |
2943 | if (EFI_ERROR (Status)) {\r | |
2944 | if (Status != EFI_NOT_FOUND) {\r | |
2945 | mVgaInstallationInProgress = FALSE;\r | |
2946 | return Status;\r | |
2947 | }\r | |
2948 | } else {\r | |
2949 | mVgaInstallationInProgress = FALSE;\r | |
2950 | }\r | |
2951 | }\r | |
2952 | }\r | |
2953 | //\r | |
2954 | // See if the option ROM for PciHandle has already been executed\r | |
2955 | //\r | |
2956 | Status = IsLegacyRom (PciHandle);\r | |
2957 | \r | |
2958 | if (!EFI_ERROR (Status)) {\r | |
2959 | mVgaInstallationInProgress = FALSE;\r | |
2960 | GetShadowedRomParameters (\r | |
2961 | PciHandle,\r | |
2962 | DiskStart,\r | |
2963 | DiskEnd,\r | |
2964 | RomShadowAddress,\r | |
2965 | (UINTN *) RomShadowedSize\r | |
2966 | );\r | |
2967 | return EFI_SUCCESS;\r | |
2968 | }\r | |
2969 | \r | |
2970 | Status = LegacyBiosCheckPciRomEx (\r | |
2971 | &Private->LegacyBios,\r | |
2972 | PciHandle,\r | |
2973 | &LocalRomImage,\r | |
2974 | &ImageSize,\r | |
2975 | &RuntimeImageLength,\r | |
2976 | Flags,\r | |
2977 | &OpromRevision,\r | |
2978 | NULL\r | |
2979 | );\r | |
2980 | if (EFI_ERROR (Status)) {\r | |
2981 | //\r | |
2982 | // There is no PCI ROM in the ROM BAR or no onboard ROM\r | |
2983 | //\r | |
2984 | mVgaInstallationInProgress = FALSE;\r | |
2985 | return EFI_UNSUPPORTED;\r | |
2986 | }\r | |
2987 | } else {\r | |
16adc276 | 2988 | if ((RomImage == NULL) || (*RomImage == NULL)) {\r |
bcecde14 | 2989 | //\r |
2990 | // If PciHandle is NULL, and no OpRom is to be associated\r | |
2991 | //\r | |
2992 | mVgaInstallationInProgress = FALSE;\r | |
2993 | return EFI_UNSUPPORTED;\r | |
2994 | }\r | |
2995 | \r | |
ee65c508 | 2996 | Status = Private->LegacyBiosPlatform->GetPlatformHandle (\r |
2997 | Private->LegacyBiosPlatform,\r | |
2998 | EfiGetPlatformVgaHandle,\r | |
2999 | 0,\r | |
3000 | &HandleBuffer,\r | |
3001 | &HandleCount,\r | |
3002 | NULL\r | |
3003 | );\r | |
3004 | if ((!EFI_ERROR (Status)) && (!Private->VgaInstalled)) {\r | |
091bb713 | 3005 | //\r |
3006 | // A return status of EFI_NOT_FOUND is considered valid (No EFI\r | |
3007 | // driver is controlling video.\r | |
3008 | //\r | |
3009 | mVgaInstallationInProgress = TRUE;\r | |
3010 | Status = LegacyBiosInstallVgaRom (Private);\r | |
3011 | if (EFI_ERROR (Status)) {\r | |
3012 | if (Status != EFI_NOT_FOUND) {\r | |
3013 | mVgaInstallationInProgress = FALSE;\r | |
3014 | return Status;\r | |
3015 | }\r | |
3016 | } else {\r | |
3017 | mVgaInstallationInProgress = FALSE;\r | |
3018 | }\r | |
3019 | }\r | |
3020 | \r | |
bcecde14 | 3021 | LocalRomImage = *RomImage;\r |
94020bb4 | 3022 | if (((PCI_EXPANSION_ROM_HEADER *) LocalRomImage)->Signature != PCI_EXPANSION_ROM_HEADER_SIGNATURE ||\r |
3023 | ((PCI_EXPANSION_ROM_HEADER *) LocalRomImage)->PcirOffset == 0 ||\r | |
3024 | (((PCI_EXPANSION_ROM_HEADER *) LocalRomImage)->PcirOffset & 3 ) != 0) {\r | |
3025 | mVgaInstallationInProgress = FALSE;\r | |
3026 | return EFI_UNSUPPORTED;\r | |
3027 | }\r | |
3028 | \r | |
bcecde14 | 3029 | Pcir = (PCI_3_0_DATA_STRUCTURE *)\r |
3030 | ((UINT8 *) LocalRomImage + ((PCI_EXPANSION_ROM_HEADER *) LocalRomImage)->PcirOffset);\r | |
94020bb4 | 3031 | \r |
007f932d | 3032 | if ((Pcir->Signature != PCI_DATA_STRUCTURE_SIGNATURE) || (Pcir->CodeType != PCI_CODE_TYPE_PCAT_IMAGE)) {\r |
94020bb4 | 3033 | mVgaInstallationInProgress = FALSE;\r |
3034 | return EFI_UNSUPPORTED;\r | |
3035 | }\r | |
3036 | \r | |
bcecde14 | 3037 | ImageSize = Pcir->ImageLength * 512;\r |
3038 | if (Pcir->Length >= 0x1C) {\r | |
3039 | OpromRevision = Pcir->Revision;\r | |
3040 | } else {\r | |
3041 | OpromRevision = 0;\r | |
3042 | }\r | |
3043 | if (Pcir->Revision < 3) {\r | |
3044 | RuntimeImageLength = 0;\r | |
3045 | } else {\r | |
3046 | RuntimeImageLength = Pcir->MaxRuntimeImageLength * 512;\r | |
3047 | }\r | |
3048 | }\r | |
60794ee6 JY |
3049 | \r |
3050 | //\r | |
3051 | // Grant access for below 1M\r | |
3052 | // BDA/EBDA/LowPMM and scratch memory for OPROM.\r | |
3053 | //\r | |
3054 | IoMmuGrantAccess (PciHandle, 0, SIZE_1MB);\r | |
3055 | //\r | |
3056 | // Grant access for HiPmm\r | |
3057 | //\r | |
3058 | IoMmuGrantAccess (\r | |
3059 | PciHandle,\r | |
3060 | Private->IntThunk->EfiToLegacy16InitTable.HiPmmMemory,\r | |
3061 | Private->IntThunk->EfiToLegacy16InitTable.HiPmmMemorySizeInBytes\r | |
3062 | );\r | |
3063 | \r | |
bcecde14 | 3064 | //\r |
3065 | // Shadow and initialize the OpROM.\r | |
3066 | //\r | |
3067 | ASSERT (Private->TraceIndex < 0x200);\r | |
3068 | Private->Trace[Private->TraceIndex] = LEGACY_PCI_TRACE_000;\r | |
3069 | Private->TraceIndex ++;\r | |
3070 | Private->TraceIndex = (UINT16) (Private->TraceIndex % 0x200);\r | |
3071 | Status = LegacyBiosInstallRom (\r | |
3072 | This,\r | |
3073 | Private,\r | |
3074 | PciHandle,\r | |
3075 | OpromRevision,\r | |
3076 | LocalRomImage,\r | |
3077 | ImageSize,\r | |
3078 | &RuntimeImageLength,\r | |
3079 | DiskStart,\r | |
3080 | DiskEnd,\r | |
3081 | RomShadowAddress\r | |
3082 | );\r | |
3083 | if (RomShadowedSize != NULL) {\r | |
3084 | *RomShadowedSize = (UINT32) RuntimeImageLength;\r | |
3085 | }\r | |
3086 | \r | |
3087 | mVgaInstallationInProgress = FALSE;\r | |
3088 | return Status;\r | |
3089 | }\r | |
3090 | \r |