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4a71b21a | 1 | /** @file\r |
79964ac8 | 2 | This file defines GUIDs and associated data structures for records posted to the Data Hub.\r |
3 | The producers of these records use these definitions to construct records.\r | |
4 | The consumers of these records use these definitions to retrieve, filter and parse records.\r | |
5 | \r | |
6 | Copyright (c) 2007, Intel Corporation\r | |
7 | All rights reserved. This program and the accompanying materials\r | |
8 | are licensed and made available under the terms and conditions of the BSD License\r | |
9 | which accompanies this distribution. The full text of the license may be found at\r | |
10 | http://opensource.org/licenses/bsd-license.php\r | |
11 | \r | |
12 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
13 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
14 | \r | |
15 | Module Name: DataHubRecords.h\r | |
16 | \r | |
17 | @par Revision Reference:\r | |
18 | DataHubRecord.h include all data hub sub class defitions from Cache subclass\r | |
19 | spec 0.9, DataHub SubClass spec 0.9, Memory SubClass Spec 0.9, Processor\r | |
20 | Subclass spec 0.9,Misc SubClass spec 0.9.\r | |
21 | \r | |
22 | **/\r | |
23 | \r | |
24 | #ifndef _DATAHUB_RECORDS_H_\r | |
25 | #define _DATAHUB_RECORDS_H_\r | |
26 | \r | |
b80fbe85 | 27 | #include <PiPei.h>\r |
28 | #include <Protocol/DevicePath.h>\r | |
8bc7aa6a | 29 | #include <Protocol/FrameworkHii.h>\r |
b80fbe85 | 30 | \r |
79964ac8 | 31 | #define EFI_PROCESSOR_SUBCLASS_VERSION 0x00010000\r |
32 | \r | |
79964ac8 | 33 | #pragma pack(1)\r |
34 | \r | |
35 | typedef struct _USB_PORT_DEVICE_PATH {\r | |
9205b2d7 | 36 | ACPI_HID_DEVICE_PATH PciRootBridgeDevicePath;\r |
37 | PCI_DEVICE_PATH PciBusDevicePath;\r | |
38 | EFI_DEVICE_PATH_PROTOCOL EndDevicePath;\r | |
79964ac8 | 39 | } USB_PORT_DEVICE_PATH;\r |
40 | \r | |
41 | //\r | |
42 | // IDE\r | |
43 | //\r | |
44 | typedef struct _IDE_DEVICE_PATH {\r | |
9205b2d7 | 45 | ACPI_HID_DEVICE_PATH PciRootBridgeDevicePath;\r |
46 | PCI_DEVICE_PATH PciBusDevicePath;\r | |
47 | EFI_DEVICE_PATH_PROTOCOL EndDevicePath;\r | |
79964ac8 | 48 | } IDE_DEVICE_PATH;\r |
49 | \r | |
50 | //\r | |
51 | // RMC Connector\r | |
52 | //\r | |
53 | typedef struct _RMC_CONN_DEVICE_PATH {\r | |
9205b2d7 | 54 | ACPI_HID_DEVICE_PATH PciRootBridgeDevicePath;\r |
55 | PCI_DEVICE_PATH PciBridgeDevicePath;\r | |
56 | PCI_DEVICE_PATH PciBusDevicePath;\r | |
57 | EFI_DEVICE_PATH_PROTOCOL EndDevicePath;\r | |
79964ac8 | 58 | } RMC_CONN_DEVICE_PATH;\r |
59 | \r | |
60 | //\r | |
61 | // RIDE\r | |
62 | //\r | |
63 | typedef struct _RIDE_DEVICE_PATH {\r | |
9205b2d7 | 64 | ACPI_HID_DEVICE_PATH PciRootBridgeDevicePath;\r |
65 | PCI_DEVICE_PATH PciBridgeDevicePath;\r | |
66 | PCI_DEVICE_PATH PciBusDevicePath;\r | |
67 | EFI_DEVICE_PATH_PROTOCOL EndDevicePath;\r | |
79964ac8 | 68 | } RIDE_DEVICE_PATH;\r |
69 | \r | |
70 | //\r | |
71 | // Gigabit NIC\r | |
72 | //\r | |
73 | typedef struct _GB_NIC_DEVICE_PATH {\r | |
9205b2d7 | 74 | ACPI_HID_DEVICE_PATH PciRootBridgeDevicePath;\r |
75 | PCI_DEVICE_PATH PciBridgeDevicePath;\r | |
76 | PCI_DEVICE_PATH PciXBridgeDevicePath;\r | |
77 | PCI_DEVICE_PATH PciXBusDevicePath;\r | |
78 | EFI_DEVICE_PATH_PROTOCOL EndDevicePath;\r | |
79964ac8 | 79 | } GB_NIC_DEVICE_PATH;\r |
80 | \r | |
81 | //\r | |
82 | // P/S2 Connector\r | |
83 | //\r | |
84 | typedef struct _PS2_CONN_DEVICE_PATH {\r | |
9205b2d7 | 85 | ACPI_HID_DEVICE_PATH PciRootBridgeDevicePath;\r |
86 | PCI_DEVICE_PATH LpcBridgeDevicePath;\r | |
87 | ACPI_HID_DEVICE_PATH LpcBusDevicePath;\r | |
88 | EFI_DEVICE_PATH_PROTOCOL EndDevicePath;\r | |
79964ac8 | 89 | } PS2_CONN_DEVICE_PATH;\r |
90 | \r | |
91 | //\r | |
92 | // Serial Port Connector\r | |
93 | //\r | |
94 | typedef struct _SERIAL_CONN_DEVICE_PATH {\r | |
9205b2d7 | 95 | ACPI_HID_DEVICE_PATH PciRootBridgeDevicePath;\r |
96 | PCI_DEVICE_PATH LpcBridgeDevicePath;\r | |
97 | ACPI_HID_DEVICE_PATH LpcBusDevicePath;\r | |
98 | EFI_DEVICE_PATH_PROTOCOL EndDevicePath;\r | |
79964ac8 | 99 | } SERIAL_CONN_DEVICE_PATH;\r |
100 | \r | |
101 | //\r | |
102 | // Parallel Port Connector\r | |
103 | //\r | |
104 | typedef struct _PARALLEL_CONN_DEVICE_PATH {\r | |
9205b2d7 | 105 | ACPI_HID_DEVICE_PATH PciRootBridgeDevicePath;\r |
106 | PCI_DEVICE_PATH LpcBridgeDevicePath;\r | |
107 | ACPI_HID_DEVICE_PATH LpcBusDevicePath;\r | |
108 | EFI_DEVICE_PATH_PROTOCOL EndDevicePath;\r | |
79964ac8 | 109 | } PARALLEL_CONN_DEVICE_PATH;\r |
110 | \r | |
111 | //\r | |
112 | // Floopy Connector\r | |
113 | //\r | |
114 | typedef struct _FLOOPY_CONN_DEVICE_PATH {\r | |
9205b2d7 | 115 | ACPI_HID_DEVICE_PATH PciRootBridgeDevicePath;\r |
116 | PCI_DEVICE_PATH LpcBridgeDevicePath;\r | |
117 | ACPI_HID_DEVICE_PATH LpcBusDevicePath;\r | |
118 | EFI_DEVICE_PATH_PROTOCOL EndDevicePath;\r | |
79964ac8 | 119 | } FLOOPY_CONN_DEVICE_PATH;\r |
120 | \r | |
121 | typedef union _EFI_MISC_PORT_DEVICE_PATH {\r | |
9205b2d7 | 122 | USB_PORT_DEVICE_PATH UsbDevicePath;\r |
123 | IDE_DEVICE_PATH IdeDevicePath;\r | |
124 | RMC_CONN_DEVICE_PATH RmcConnDevicePath;\r | |
125 | RIDE_DEVICE_PATH RideDevicePath;\r | |
126 | GB_NIC_DEVICE_PATH GbNicDevicePath;\r | |
127 | PS2_CONN_DEVICE_PATH Ps2ConnDevicePath;\r | |
128 | SERIAL_CONN_DEVICE_PATH SerialConnDevicePath;\r | |
129 | PARALLEL_CONN_DEVICE_PATH ParallelConnDevicePath;\r | |
130 | FLOOPY_CONN_DEVICE_PATH FloppyConnDevicePath;\r | |
79964ac8 | 131 | } EFI_MISC_PORT_DEVICE_PATH;\r |
132 | \r | |
133 | #pragma pack()\r | |
134 | \r | |
135 | //\r | |
136 | // String Token Definition\r | |
137 | //\r | |
9205b2d7 | 138 | #define EFI_STRING_TOKEN UINT16\r |
79964ac8 | 139 | \r |
470d0b27 | 140 | ///\r |
141 | /// Each data record that is a member of some subclass starts with a standard \r | |
142 | /// header of type EFI_SUBCLASS_TYPE1_HEADER.\r | |
143 | /// This header is only a guideline and applicable only to a data \r | |
144 | /// subclass that is producing SMBIOS data records. A subclass can start with a \r | |
145 | /// different header if needed. \r | |
146 | ///\r | |
79964ac8 | 147 | typedef struct {\r |
470d0b27 | 148 | ///\r |
149 | /// The version of the specification to which a specific subclass data record adheres. \r | |
150 | ///\r | |
9205b2d7 | 151 | UINT32 Version;\r |
470d0b27 | 152 | ///\r |
153 | /// The size in bytes of this data class header. \r | |
154 | ///\r | |
9205b2d7 | 155 | UINT32 HeaderSize;\r |
470d0b27 | 156 | ///\r |
157 | /// The instance number of the subclass with the same ProducerName. This number is \r | |
158 | /// applicable in cases where multiple subclass instances that were produced by the same \r | |
159 | /// driver exist in the system. This entry is 1 based; 0 means Reserved and -1 means Not \r | |
160 | /// Applicable. All data consumer drivers should be able to handle all the possible values \r | |
161 | /// of Instance, including Not Applicable and Reserved. \r | |
162 | ///\r | |
9205b2d7 | 163 | UINT16 Instance;\r |
470d0b27 | 164 | ///\r |
165 | /// The instance number of the RecordType for the same Instance. This number is \r | |
166 | /// applicable in cases where multiple instances of the RecordType exist for a specific \r | |
167 | /// Instance. This entry is 1 based; 0 means Reserved and -1 means Not Applicable. \r | |
168 | /// All data consumer drivers should be able to handle all the possible values of \r | |
169 | /// SubInstance, including Not Applicable and Reserved. \r | |
170 | ///\r | |
9205b2d7 | 171 | UINT16 SubInstance;\r |
470d0b27 | 172 | ///\r |
173 | /// The record number for the data record being specified. The numbering scheme and \r | |
174 | /// definition is defined in the specific subclass specification. \r | |
175 | ///\r | |
9205b2d7 | 176 | UINT32 RecordType;\r |
79964ac8 | 177 | } EFI_SUBCLASS_TYPE1_HEADER;\r |
178 | \r | |
470d0b27 | 179 | ///\r |
180 | /// This structure is used to link data records in the same subclasses. A data record is \r | |
181 | /// defined as a link to another data record in the same subclass using this structure. \r | |
182 | ///\r | |
79964ac8 | 183 | typedef struct {\r |
470d0b27 | 184 | ///\r |
185 | /// An EFI_GUID that identifies the component that produced this data record. Type \r | |
186 | /// EFI_GUID is defined in InstallProtocolInterface() in the EFI 1.10 Specification. \r | |
187 | ///\r | |
9205b2d7 | 188 | EFI_GUID ProducerName;\r |
470d0b27 | 189 | ///\r |
190 | /// The instance number of the subclass with the same ProducerName. This number is \r | |
191 | /// applicable in cases where multiple subclass instances that were produced by the same \r | |
192 | /// driver exist in the system. This entry is 1 based; 0 means Reserved and -1 means Not \r | |
193 | /// Applicable. All data consumer drivers should be able to handle all the possible values \r | |
194 | /// of Instance, including Not Applicable and Reserved. \r | |
195 | ///\r | |
9205b2d7 | 196 | UINT16 Instance;\r |
470d0b27 | 197 | /// The instance number of the RecordType for the same Instance. This number is \r |
198 | /// applicable in cases where multiple instances of the RecordType exist for a specific \r | |
199 | /// Instance. This entry is 1 based; 0 means Reserved and -1 means Not Applicable. \r | |
200 | /// All data consumer drivers should be able to handle all the possible values of \r | |
201 | /// SubInstance, including Not Applicable and Reserved. \r | |
9205b2d7 | 202 | UINT16 SubInstance;\r |
79964ac8 | 203 | } EFI_INTER_LINK_DATA;\r |
204 | \r | |
79964ac8 | 205 | //\r |
206 | // EXP data\r | |
207 | //\r | |
470d0b27 | 208 | ///\r |
209 | /// This macro provides a calculation for base-10 representations. Value and Exponent are each \r | |
210 | /// INT16. It is signed to cover negative values and is 16 bits wide (15 bits for data and 1 bit\r | |
211 | /// for the sign). \r | |
212 | ///\r | |
79964ac8 | 213 | typedef struct {\r |
470d0b27 | 214 | ///\r |
215 | /// The INT16 number by which to multiply the base-10 representation. \r | |
216 | ///\r | |
9205b2d7 | 217 | UINT16 Value;\r |
470d0b27 | 218 | ///\r |
219 | /// The INT16 number by which to raise the base-10 calculation. \r | |
220 | ///\r | |
9205b2d7 | 221 | UINT16 Exponent;\r |
79964ac8 | 222 | } EFI_EXP_BASE2_DATA;\r |
223 | \r | |
470d0b27 | 224 | ///\r |
225 | /// This macro provides a calculation for base-2 representations. Value and Exponent are each \r | |
226 | /// INT16. It is 16 bits wide and is unsigned to mean nonnegative values. \r | |
227 | ///\r | |
df2b7d51 | 228 | typedef struct {\r |
470d0b27 | 229 | ///\r |
230 | /// The INT16 number by which to multiply the base-2 representation.\r | |
231 | ///\r | |
9205b2d7 | 232 | UINT16 Value;\r |
470d0b27 | 233 | ///\r |
234 | /// The INT16 number by which to raise the base-2 calculation. \r | |
235 | ///\r | |
9205b2d7 | 236 | UINT16 Exponent;\r |
df2b7d51 | 237 | } EFI_EXP_BASE10_DATA;\r |
238 | \r | |
9205b2d7 | 239 | typedef EFI_EXP_BASE10_DATA EFI_PROCESSOR_MAX_CORE_FREQUENCY_DATA;\r |
240 | typedef EFI_EXP_BASE10_DATA EFI_PROCESSOR_MAX_FSB_FREQUENCY_DATA;\r | |
241 | typedef EFI_EXP_BASE10_DATA EFI_PROCESSOR_CORE_FREQUENCY_DATA;\r | |
470d0b27 | 242 | \r |
243 | ///\r | |
244 | /// This data record refers to the list of frequencies that the processor core supports. The list of \r | |
245 | /// supported frequencies is determined by the firmware based on hardware capabilities--for example, \r | |
246 | /// it could be a common subset of all processors and the chipset. The unit of measurement of this data \r | |
247 | /// record is in Hertz. For asynchronous processors, the content of this data record is zero. \r | |
248 | /// The list is terminated by -1 in the Value field of the last element. A Value field of zero means \r | |
249 | /// that the processor/driver supports automatic frequency selection. \r | |
250 | ///\r | |
9205b2d7 | 251 | typedef EFI_EXP_BASE10_DATA *EFI_PROCESSOR_CORE_FREQUENCY_LIST_DATA;\r |
470d0b27 | 252 | \r |
253 | ///\r | |
254 | /// This data record refers to the list of supported frequencies of the processor external bus. The list of \r | |
255 | /// supported frequencies is determined by the firmware based on hardware capabilities--for example, \r | |
256 | /// it could be a common subset of all processors and the chipset. The unit of measurement of this data \r | |
257 | /// record is in Hertz. For asynchronous processors, the content of this data record is NULL. \r | |
258 | /// The list is terminated by -1 in the Value field of the last element. A Value field of zero means \r | |
259 | /// that the processor/driver supports automatic frequency selection. \r | |
260 | ///\r | |
9205b2d7 | 261 | typedef EFI_EXP_BASE10_DATA *EFI_PROCESSOR_FSB_FREQUENCY_LIST_DATA;\r |
262 | typedef EFI_EXP_BASE10_DATA EFI_PROCESSOR_FSB_FREQUENCY_DATA;\r | |
263 | typedef STRING_REF EFI_PROCESSOR_VERSION_DATA;\r | |
264 | typedef STRING_REF EFI_PROCESSOR_MANUFACTURER_DATA;\r | |
265 | typedef STRING_REF EFI_PROCESSOR_SERIAL_NUMBER_DATA;\r | |
266 | typedef STRING_REF EFI_PROCESSOR_ASSET_TAG_DATA;\r | |
267 | \r | |
268 | typedef struct {\r | |
269 | UINT32 ProcessorSteppingId:4;\r | |
270 | UINT32 ProcessorModel: 4;\r | |
271 | UINT32 ProcessorFamily: 4;\r | |
272 | UINT32 ProcessorType: 2;\r | |
273 | UINT32 ProcessorReserved1: 2;\r | |
274 | UINT32 ProcessorXModel: 4;\r | |
275 | UINT32 ProcessorXFamily: 8;\r | |
276 | UINT32 ProcessorReserved2: 4;\r | |
79964ac8 | 277 | } EFI_PROCESSOR_SIGNATURE;\r |
278 | \r | |
279 | typedef struct {\r | |
9205b2d7 | 280 | UINT32 ProcessorBrandIndex :8;\r |
281 | UINT32 ProcessorClflush :8;\r | |
282 | UINT32 ProcessorReserved :8;\r | |
283 | UINT32 ProcessorDfltApicId :8;\r | |
79964ac8 | 284 | } EFI_PROCESSOR_MISC_INFO;\r |
285 | \r | |
286 | typedef struct {\r | |
9205b2d7 | 287 | UINT32 ProcessorFpu: 1;\r |
288 | UINT32 ProcessorVme: 1;\r | |
289 | UINT32 ProcessorDe: 1;\r | |
290 | UINT32 ProcessorPse: 1;\r | |
291 | UINT32 ProcessorTsc: 1;\r | |
292 | UINT32 ProcessorMsr: 1;\r | |
293 | UINT32 ProcessorPae: 1;\r | |
294 | UINT32 ProcessorMce: 1;\r | |
295 | UINT32 ProcessorCx8: 1;\r | |
296 | UINT32 ProcessorApic: 1;\r | |
297 | UINT32 ProcessorReserved1: 1;\r | |
298 | UINT32 ProcessorSep: 1;\r | |
299 | UINT32 ProcessorMtrr: 1;\r | |
300 | UINT32 ProcessorPge: 1;\r | |
301 | UINT32 ProcessorMca: 1;\r | |
302 | UINT32 ProcessorCmov: 1;\r | |
303 | UINT32 ProcessorPat: 1;\r | |
304 | UINT32 ProcessorPse36: 1;\r | |
305 | UINT32 ProcessorPsn: 1;\r | |
306 | UINT32 ProcessorClfsh: 1;\r | |
307 | UINT32 ProcessorReserved2: 1;\r | |
308 | UINT32 ProcessorDs: 1;\r | |
309 | UINT32 ProcessorAcpi: 1;\r | |
310 | UINT32 ProcessorMmx: 1;\r | |
311 | UINT32 ProcessorFxsr: 1;\r | |
312 | UINT32 ProcessorSse: 1;\r | |
313 | UINT32 ProcessorSse2: 1;\r | |
314 | UINT32 ProcessorSs: 1;\r | |
315 | UINT32 ProcessorReserved3: 1;\r | |
316 | UINT32 ProcessorTm: 1;\r | |
317 | UINT32 ProcessorReserved4: 2;\r | |
79964ac8 | 318 | } EFI_PROCESSOR_FEATURE_FLAGS;\r |
319 | \r | |
470d0b27 | 320 | ///\r |
321 | /// This data record refers to the unique ID that identifies a set of processors. This data record is 16 \r | |
322 | /// bytes in length. The data in this structure is processor specific and reserved values can be defined \r | |
323 | /// for future use. The consumer of this data should not make any assumption and should use this data \r | |
324 | /// with respect to the processor family defined in the Family record number. \r | |
325 | ///\r | |
79964ac8 | 326 | typedef struct {\r |
470d0b27 | 327 | ///\r |
328 | /// Identifies the processor.\r | |
329 | ///\r | |
9205b2d7 | 330 | EFI_PROCESSOR_SIGNATURE Signature;\r |
470d0b27 | 331 | ///\r |
332 | /// Provides additional processor information. \r | |
333 | ///\r | |
9205b2d7 | 334 | EFI_PROCESSOR_MISC_INFO MiscInfo;\r |
470d0b27 | 335 | ///\r |
336 | /// Reserved for future use. \r | |
337 | ///\r | |
9205b2d7 | 338 | UINT32 Reserved;\r |
470d0b27 | 339 | ///\r |
340 | /// Provides additional processor information. \r | |
341 | ///\r | |
9205b2d7 | 342 | EFI_PROCESSOR_FEATURE_FLAGS FeatureFlags;\r |
79964ac8 | 343 | } EFI_PROCESSOR_ID_DATA;\r |
344 | \r | |
470d0b27 | 345 | ///\r |
346 | /// This data record refers to the general classification of the processor. This data record is 4 bytes in \r | |
347 | /// length. \r | |
348 | ///\r | |
79964ac8 | 349 | typedef enum {\r |
350 | EfiProcessorOther = 1,\r | |
351 | EfiProcessorUnknown = 2,\r | |
352 | EfiCentralProcessor = 3,\r | |
353 | EfiMathProcessor = 4,\r | |
354 | EfiDspProcessor = 5,\r | |
355 | EfiVideoProcessor = 6\r | |
356 | } EFI_PROCESSOR_TYPE_DATA;\r | |
357 | \r | |
470d0b27 | 358 | ///\r |
359 | /// This data record refers to the family of the processor as defined by the DMTF. \r | |
360 | /// This data record is 4 bytes in length. \r | |
361 | ///\r | |
79964ac8 | 362 | typedef enum {\r |
a244f400 | 363 | EfiProcessorFamilyOther = 0x01, \r |
364 | EfiProcessorFamilyUnknown = 0x02,\r | |
365 | EfiProcessorFamily8086 = 0x03, \r | |
366 | EfiProcessorFamily80286 = 0x04,\r | |
367 | EfiProcessorFamilyIntel386 = 0x05, \r | |
368 | EfiProcessorFamilyIntel486 = 0x06,\r | |
369 | EfiProcessorFamily8087 = 0x07,\r | |
370 | EfiProcessorFamily80287 = 0x08,\r | |
371 | EfiProcessorFamily80387 = 0x09, \r | |
372 | EfiProcessorFamily80487 = 0x0A,\r | |
373 | EfiProcessorFamilyPentium = 0x0B, \r | |
374 | EfiProcessorFamilyPentiumPro = 0x0C,\r | |
375 | EfiProcessorFamilyPentiumII = 0x0D,\r | |
376 | EfiProcessorFamilyPentiumMMX = 0x0E,\r | |
377 | EfiProcessorFamilyCeleron = 0x0F,\r | |
378 | EfiProcessorFamilyPentiumIIXeon = 0x10,\r | |
379 | EfiProcessorFamilyPentiumIII = 0x11, \r | |
380 | EfiProcessorFamilyM1 = 0x12,\r | |
381 | EfiProcessorFamilyM2 = 0x13,\r | |
382 | EfiProcessorFamilyM1Reserved2 = 0x14,\r | |
383 | EfiProcessorFamilyM1Reserved3 = 0x15,\r | |
384 | EfiProcessorFamilyM1Reserved4 = 0x16,\r | |
385 | EfiProcessorFamilyM1Reserved5 = 0x17,\r | |
386 | EfiProcessorFamilyAmdDuron = 0x18,\r | |
387 | EfiProcessorFamilyK5 = 0x19, \r | |
388 | EfiProcessorFamilyK6 = 0x1A,\r | |
389 | EfiProcessorFamilyK6_2 = 0x1B,\r | |
390 | EfiProcessorFamilyK6_3 = 0x1C,\r | |
391 | EfiProcessorFamilyAmdAthlon = 0x1D,\r | |
392 | EfiProcessorFamilyAmd29000 = 0x1E,\r | |
393 | EfiProcessorFamilyK6_2Plus = 0x1F,\r | |
394 | EfiProcessorFamilyPowerPC = 0x20,\r | |
395 | EfiProcessorFamilyPowerPC601 = 0x21,\r | |
396 | EfiProcessorFamilyPowerPC603 = 0x22,\r | |
397 | EfiProcessorFamilyPowerPC603Plus = 0x23,\r | |
398 | EfiProcessorFamilyPowerPC604 = 0x24,\r | |
399 | EfiProcessorFamilyPowerPC620 = 0x25,\r | |
400 | EfiProcessorFamilyPowerPCx704 = 0x26,\r | |
401 | EfiProcessorFamilyPowerPC750 = 0x27,\r | |
402 | EfiProcessorFamilyAlpha3 = 0x30,\r | |
403 | EfiProcessorFamilyAlpha21064 = 0x31,\r | |
404 | EfiProcessorFamilyAlpha21066 = 0x32,\r | |
405 | EfiProcessorFamilyAlpha21164 = 0x33,\r | |
406 | EfiProcessorFamilyAlpha21164PC = 0x34,\r | |
407 | EfiProcessorFamilyAlpha21164a = 0x35,\r | |
408 | EfiProcessorFamilyAlpha21264 = 0x36,\r | |
409 | EfiProcessorFamilyAlpha21364 = 0x37,\r | |
410 | EfiProcessorFamilyMips = 0x40,\r | |
411 | EfiProcessorFamilyMIPSR4000 = 0x41,\r | |
412 | EfiProcessorFamilyMIPSR4200 = 0x42,\r | |
413 | EfiProcessorFamilyMIPSR4400 = 0x43,\r | |
414 | EfiProcessorFamilyMIPSR4600 = 0x44,\r | |
415 | EfiProcessorFamilyMIPSR10000 = 0x45,\r | |
416 | EfiProcessorFamilySparc = 0x50,\r | |
417 | EfiProcessorFamilySuperSparc = 0x51,\r | |
418 | EfiProcessorFamilymicroSparcII = 0x52,\r | |
419 | EfiProcessorFamilymicroSparcIIep = 0x53,\r | |
420 | EfiProcessorFamilyUltraSparc = 0x54,\r | |
421 | EfiProcessorFamilyUltraSparcII = 0x55,\r | |
422 | EfiProcessorFamilyUltraSparcIIi = 0x56,\r | |
423 | EfiProcessorFamilyUltraSparcIII = 0x57,\r | |
424 | EfiProcessorFamilyUltraSparcIIIi = 0x58,\r | |
425 | EfiProcessorFamily68040 = 0x60,\r | |
426 | EfiProcessorFamily68xxx = 0x61,\r | |
427 | EfiProcessorFamily68000 = 0x62,\r | |
428 | EfiProcessorFamily68010 = 0x63,\r | |
429 | EfiProcessorFamily68020 = 0x64,\r | |
430 | EfiProcessorFamily68030 = 0x65,\r | |
431 | EfiProcessorFamilyHobbit = 0x70,\r | |
432 | EfiProcessorFamilyCrusoeTM5000 = 0x78,\r | |
433 | EfiProcessorFamilyCrusoeTM3000 = 0x79,\r | |
434 | EfiProcessorFamilyEfficeonTM8000 = 0x7A,\r | |
435 | EfiProcessorFamilyWeitek = 0x80,\r | |
436 | EfiProcessorFamilyItanium = 0x82,\r | |
437 | EfiProcessorFamilyAmdAthlon64 = 0x83,\r | |
438 | EfiProcessorFamilyAmdOpteron = 0x84,\r | |
439 | EfiProcessorFamilyAmdSempron = 0x85,\r | |
440 | EfiProcessorFamilyAmdTurion64Mobile = 0x86,\r | |
441 | EfiProcessorFamilyDualCoreAmdOpteron = 0x87,\r | |
442 | EfiProcessorFamilyAmdAthlon64X2DualCore = 0x88,\r | |
443 | EfiProcessorFamilyAmdTurion64X2Mobile = 0x89,\r | |
444 | EfiProcessorFamilyPARISC = 0x90,\r | |
445 | EfiProcessorFamilyPaRisc8500 = 0x91,\r | |
446 | EfiProcessorFamilyPaRisc8000 = 0x92,\r | |
447 | EfiProcessorFamilyPaRisc7300LC = 0x93,\r | |
448 | EfiProcessorFamilyPaRisc7200 = 0x94,\r | |
449 | EfiProcessorFamilyPaRisc7100LC = 0x95,\r | |
450 | EfiProcessorFamilyPaRisc7100 = 0x96,\r | |
451 | EfiProcessorFamilyV30 = 0xA0,\r | |
452 | EfiProcessorFamilyPentiumIIIXeon = 0xB0,\r | |
453 | EfiProcessorFamilyPentiumIIISpeedStep = 0xB1,\r | |
454 | EfiProcessorFamilyPentium4 = 0xB2,\r | |
455 | EfiProcessorFamilyIntelXeon = 0xB3,\r | |
456 | EfiProcessorFamilyAS400 = 0xB4,\r | |
457 | EfiProcessorFamilyIntelXeonMP = 0xB5,\r | |
458 | EfiProcessorFamilyAMDAthlonXP = 0xB6,\r | |
459 | EfiProcessorFamilyAMDAthlonMP = 0xB7,\r | |
460 | EfiProcessorFamilyIntelItanium2 = 0xB8,\r | |
461 | EfiProcessorFamilyIntelPentiumM = 0xB9,\r | |
462 | EfiProcessorFamilyIntelCeleronD = 0xBA,\r | |
463 | EfiProcessorFamilyIntelPentiumD = 0xBB,\r | |
464 | EfiProcessorFamilyIntelPentiumEx = 0xBC,\r | |
465 | EfiProcessorFamilyIntelCoreSolo = 0xBD, ///< SMBIOS spec 2.6 correct this value\r | |
466 | EfiProcessorFamilyReserved = 0xBE,\r | |
467 | EfiProcessorFamilyIntelCore2 = 0xBF,\r | |
468 | EfiProcessorFamilyIBM390 = 0xC8,\r | |
469 | EfiProcessorFamilyG4 = 0xC9,\r | |
470 | EfiProcessorFamilyG5 = 0xCA,\r | |
471 | EfiProcessorFamilyG6 = 0xCB,\r | |
472 | EfiProcessorFamilyzArchitectur = 0xCC,\r | |
473 | EfiProcessorFamilyViaC7M = 0xD2,\r | |
474 | EfiProcessorFamilyViaC7D = 0xD3,\r | |
475 | EfiProcessorFamilyViaC7 = 0xD4,\r | |
476 | EfiProcessorFamilyViaEden = 0xD5,\r | |
477 | EfiProcessorFamilyi860 = 0xFA,\r | |
478 | EfiProcessorFamilyi960 = 0xFB,\r | |
479 | EfiProcessorFamilyIndicatorFamily2 = 0xFE,\r | |
480 | EfiProcessorFamilyReserved1 = 0xFF\r | |
79964ac8 | 481 | } EFI_PROCESSOR_FAMILY_DATA;\r |
482 | \r | |
470d0b27 | 483 | ///\r |
484 | /// This data record refers to the core voltage of the processor being defined. The unit of measurement \r | |
485 | /// of this data record is in volts. \r | |
486 | ///\r | |
9205b2d7 | 487 | typedef EFI_EXP_BASE10_DATA EFI_PROCESSOR_VOLTAGE_DATA;\r |
470d0b27 | 488 | \r |
489 | ///\r | |
490 | /// This data record refers to the base address of the APIC of the processor being defined. This data \r | |
491 | /// record is a physical address location. \r | |
492 | ///\r | |
9205b2d7 | 493 | typedef EFI_PHYSICAL_ADDRESS EFI_PROCESSOR_APIC_BASE_ADDRESS_DATA;\r |
470d0b27 | 494 | \r |
495 | ///\r | |
496 | /// This data record refers to the ID of the APIC of the processor being defined. This data record is a \r | |
497 | /// 4-byte entry. \r | |
498 | ///\r | |
9205b2d7 | 499 | typedef UINT32 EFI_PROCESSOR_APIC_ID_DATA;\r |
470d0b27 | 500 | \r |
501 | ///\r | |
502 | /// This data record refers to the version number of the APIC of the processor being defined. This data \r | |
503 | /// record is a 4-byte entry. \r | |
504 | ///\r | |
9205b2d7 | 505 | typedef UINT32 EFI_PROCESSOR_APIC_VERSION_NUMBER_DATA;\r |
79964ac8 | 506 | \r |
507 | typedef enum {\r | |
508 | EfiProcessorIa32Microcode = 1,\r | |
509 | EfiProcessorIpfPalAMicrocode = 2,\r | |
510 | EfiProcessorIpfPalBMicrocode = 3\r | |
511 | } EFI_PROCESSOR_MICROCODE_TYPE;\r | |
512 | \r | |
470d0b27 | 513 | ///\r |
514 | /// This data record refers to the revision of the processor microcode that is loaded in the processor. \r | |
515 | /// This data record is a 4-byte entry. \r | |
516 | ///\r | |
79964ac8 | 517 | typedef struct {\r |
470d0b27 | 518 | ///\r |
519 | /// Identifies what type of microcode the data is. \r | |
520 | /// \r | |
9205b2d7 | 521 | EFI_PROCESSOR_MICROCODE_TYPE ProcessorMicrocodeType;\r |
470d0b27 | 522 | ///\r |
523 | /// Indicates the revision number of this microcode. \r | |
524 | ///\r | |
9205b2d7 | 525 | UINT32 ProcessorMicrocodeRevisionNumber;\r |
79964ac8 | 526 | } EFI_PROCESSOR_MICROCODE_REVISION_DATA;\r |
527 | \r | |
470d0b27 | 528 | ///\r |
529 | /// This data record refers to the status of the processor.\r | |
530 | ///\r | |
79964ac8 | 531 | typedef struct {\r |
470d0b27 | 532 | UINT32 CpuStatus :3; ///> Indicates the status of the processor. \r |
533 | UINT32 Reserved1 :3; ///> Reserved for future use. Should be set to zero. \r | |
534 | UINT32 SocketPopulated :1; ///> Indicates if the processor is socketed or not. \r | |
535 | UINT32 Reserved2 :1; ///> Reserved for future use. Should be set to zero. \r | |
536 | UINT32 ApicEnable :1; ///> Indicates if the APIC is enabled or not. \r | |
537 | UINT32 BootApplicationProcessor :1; ///> Indicates if this processor is the boot processor. \r | |
538 | UINT32 Reserved3 :22;///> Reserved for future use. Should be set to zero. \r | |
79964ac8 | 539 | } EFI_PROCESSOR_STATUS_DATA;\r |
540 | \r | |
541 | typedef enum {\r | |
542 | EfiCpuStatusUnknown = 0,\r | |
543 | EfiCpuStatusEnabled = 1,\r | |
544 | EfiCpuStatusDisabledByUser = 2,\r | |
545 | EfiCpuStatusDisabledbyBios = 3,\r | |
546 | EfiCpuStatusIdle = 4,\r | |
547 | EfiCpuStatusOther = 7\r | |
548 | } EFI_CPU_STATUS;\r | |
549 | \r | |
550 | typedef enum {\r | |
551 | EfiProcessorSocketOther = 1,\r | |
552 | EfiProcessorSocketUnknown = 2,\r | |
553 | EfiProcessorSocketDaughterBoard = 3,\r | |
554 | EfiProcessorSocketZIF = 4,\r | |
555 | EfiProcessorSocketReplacePiggyBack = 5,\r | |
556 | EfiProcessorSocketNone = 6,\r | |
557 | EfiProcessorSocketLIF = 7,\r | |
558 | EfiProcessorSocketSlot1 = 8,\r | |
559 | EfiProcessorSocketSlot2 = 9,\r | |
560 | EfiProcessorSocket370Pin = 0xA,\r | |
561 | EfiProcessorSocketSlotA = 0xB,\r | |
562 | EfiProcessorSocketSlotM = 0xC,\r | |
563 | EfiProcessorSocket423 = 0xD,\r | |
564 | EfiProcessorSocketA462 = 0xE,\r | |
565 | EfiProcessorSocket478 = 0xF,\r | |
566 | EfiProcessorSocket754 = 0x10,\r | |
567 | EfiProcessorSocket940 = 0x11,\r | |
568 | EfiProcessorSocket939 = 0x12,\r | |
569 | EfiProcessorSocketmPGA604 = 0x13,\r | |
570 | EfiProcessorSocketLGA771 = 0x14,\r | |
571 | EfiProcessorSocketLGA775 = 0x15\r | |
572 | \r | |
573 | } EFI_PROCESSOR_SOCKET_TYPE_DATA;\r | |
574 | \r | |
9205b2d7 | 575 | typedef STRING_REF EFI_PROCESSOR_SOCKET_NAME_DATA;\r |
576 | typedef EFI_INTER_LINK_DATA EFI_CACHE_ASSOCIATION_DATA;\r | |
79964ac8 | 577 | \r |
470d0b27 | 578 | ///\r |
579 | /// This data record refers to the health status of the processor. \r | |
580 | ///\r | |
79964ac8 | 581 | typedef enum {\r |
582 | EfiProcessorHealthy = 1,\r | |
583 | EfiProcessorPerfRestricted = 2,\r | |
470d0b27 | 584 | EfiProcessorFuncRestricted = 3 \r |
79964ac8 | 585 | } EFI_PROCESSOR_HEALTH_STATUS;\r |
586 | \r | |
470d0b27 | 587 | ///\r |
588 | /// This data record refers to the package number of this processor. Multiple logical processors can \r | |
589 | /// exist in a system and each logical processor can be correlated to the physical processor using this \r | |
590 | /// record type. \r | |
591 | ///\r | |
9205b2d7 | 592 | typedef UINTN EFI_PROCESSOR_PACKAGE_NUMBER_DATA;\r |
79964ac8 | 593 | \r |
594 | typedef enum {\r | |
595 | ProcessorCoreFrequencyRecordType = 1,\r | |
596 | ProcessorFsbFrequencyRecordType = 2,\r | |
597 | ProcessorVersionRecordType = 3,\r | |
598 | ProcessorManufacturerRecordType = 4,\r | |
599 | ProcessorSerialNumberRecordType = 5,\r | |
600 | ProcessorIdRecordType = 6,\r | |
601 | ProcessorTypeRecordType = 7,\r | |
602 | ProcessorFamilyRecordType = 8,\r | |
603 | ProcessorVoltageRecordType = 9,\r | |
604 | ProcessorApicBaseAddressRecordType = 10,\r | |
605 | ProcessorApicIdRecordType = 11,\r | |
606 | ProcessorApicVersionNumberRecordType = 12,\r | |
607 | CpuUcodeRevisionDataRecordType = 13,\r | |
608 | ProcessorStatusRecordType = 14,\r | |
609 | ProcessorSocketTypeRecordType = 15,\r | |
610 | ProcessorSocketNameRecordType = 16,\r | |
611 | CacheAssociationRecordType = 17,\r | |
612 | ProcessorMaxCoreFrequencyRecordType = 18,\r | |
613 | ProcessorAssetTagRecordType = 19,\r | |
614 | ProcessorMaxFsbFrequencyRecordType = 20,\r | |
615 | ProcessorPackageNumberRecordType = 21,\r | |
616 | ProcessorCoreFrequencyListRecordType = 22,\r | |
617 | ProcessorFsbFrequencyListRecordType = 23,\r | |
618 | ProcessorHealthStatusRecordType = 24\r | |
619 | } EFI_CPU_VARIABLE_RECORD_TYPE;\r | |
620 | \r | |
621 | typedef union {\r | |
622 | EFI_PROCESSOR_CORE_FREQUENCY_LIST_DATA ProcessorCoreFrequencyList;\r | |
623 | EFI_PROCESSOR_FSB_FREQUENCY_LIST_DATA ProcessorFsbFrequencyList;\r | |
624 | EFI_PROCESSOR_SERIAL_NUMBER_DATA ProcessorSerialNumber;\r | |
625 | EFI_PROCESSOR_CORE_FREQUENCY_DATA ProcessorCoreFrequency;\r | |
626 | EFI_PROCESSOR_FSB_FREQUENCY_DATA ProcessorFsbFrequency;\r | |
627 | EFI_PROCESSOR_MAX_CORE_FREQUENCY_DATA ProcessorMaxCoreFrequency;\r | |
628 | EFI_PROCESSOR_MAX_FSB_FREQUENCY_DATA ProcessorMaxFsbFrequency;\r | |
629 | EFI_PROCESSOR_VERSION_DATA ProcessorVersion;\r | |
630 | EFI_PROCESSOR_MANUFACTURER_DATA ProcessorManufacturer;\r | |
631 | EFI_PROCESSOR_ID_DATA ProcessorId;\r | |
632 | EFI_PROCESSOR_TYPE_DATA ProcessorType;\r | |
633 | EFI_PROCESSOR_FAMILY_DATA ProcessorFamily;\r | |
634 | EFI_PROCESSOR_VOLTAGE_DATA ProcessorVoltage;\r | |
635 | EFI_PROCESSOR_APIC_BASE_ADDRESS_DATA ProcessorApicBase;\r | |
636 | EFI_PROCESSOR_APIC_ID_DATA ProcessorApicId;\r | |
637 | EFI_PROCESSOR_APIC_VERSION_NUMBER_DATA ProcessorApicVersionNumber;\r | |
638 | EFI_PROCESSOR_MICROCODE_REVISION_DATA CpuUcodeRevisionData;\r | |
639 | EFI_PROCESSOR_STATUS_DATA ProcessorStatus;\r | |
640 | EFI_PROCESSOR_SOCKET_TYPE_DATA ProcessorSocketType;\r | |
641 | EFI_PROCESSOR_SOCKET_NAME_DATA ProcessorSocketName;\r | |
642 | EFI_PROCESSOR_ASSET_TAG_DATA ProcessorAssetTag;\r | |
643 | EFI_PROCESSOR_HEALTH_STATUS ProcessorHealthStatus;\r | |
644 | EFI_PROCESSOR_PACKAGE_NUMBER_DATA ProcessorPackageNumber;\r | |
645 | } EFI_CPU_VARIABLE_RECORD;\r | |
646 | \r | |
647 | typedef struct {\r | |
9205b2d7 | 648 | EFI_SUBCLASS_TYPE1_HEADER DataRecordHeader;\r |
649 | EFI_CPU_VARIABLE_RECORD VariableRecord;\r | |
79964ac8 | 650 | } EFI_CPU_DATA_RECORD;\r |
651 | \r | |
652 | #define EFI_CACHE_SUBCLASS_VERSION 0x00010000\r | |
653 | \r | |
9205b2d7 | 654 | typedef EFI_EXP_BASE2_DATA EFI_CACHE_SIZE_DATA;\r |
655 | typedef EFI_EXP_BASE2_DATA EFI_MAXIMUM_CACHE_SIZE_DATA;\r | |
656 | typedef EFI_EXP_BASE10_DATA EFI_CACHE_SPEED_DATA;\r | |
657 | typedef STRING_REF EFI_CACHE_SOCKET_DATA;\r | |
79964ac8 | 658 | \r |
659 | typedef struct {\r | |
9205b2d7 | 660 | UINT32 Other :1;\r |
661 | UINT32 Unknown :1;\r | |
662 | UINT32 NonBurst :1;\r | |
663 | UINT32 Burst :1;\r | |
664 | UINT32 PipelineBurst :1;\r | |
665 | UINT32 Asynchronous :1;\r | |
666 | UINT32 Synchronous :1;\r | |
667 | UINT32 Reserved :25;\r | |
79964ac8 | 668 | } EFI_CACHE_SRAM_TYPE_DATA;\r |
669 | \r | |
9205b2d7 | 670 | typedef EFI_CACHE_SRAM_TYPE_DATA EFI_CACHE_SRAM_INSTALL_DATA;\r |
8403ef2e | 671 | \r |
79964ac8 | 672 | typedef enum {\r |
673 | EfiCacheErrorOther = 1,\r | |
674 | EfiCacheErrorUnknown = 2,\r | |
675 | EfiCacheErrorNone = 3,\r | |
676 | EfiCacheErrorParity = 4,\r | |
677 | EfiCacheErrorSingleBit = 5,\r | |
678 | EfiCacheErrorMultiBit = 6\r | |
679 | } EFI_CACHE_ERROR_TYPE_DATA;\r | |
680 | \r | |
681 | typedef enum {\r | |
682 | EfiCacheTypeOther = 1,\r | |
683 | EfiCacheTypeUnknown = 2,\r | |
684 | EfiCacheTypeInstruction = 3,\r | |
685 | EfiCacheTypeData = 4,\r | |
686 | EfiCacheTypeUnified = 5\r | |
687 | } EFI_CACHE_TYPE_DATA;\r | |
688 | \r | |
689 | typedef enum {\r | |
690 | EfiCacheAssociativityOther = 1,\r | |
691 | EfiCacheAssociativityUnknown = 2,\r | |
692 | EfiCacheAssociativityDirectMapped = 3,\r | |
693 | EfiCacheAssociativity2Way = 4,\r | |
694 | EfiCacheAssociativity4Way = 5,\r | |
695 | EfiCacheAssociativityFully = 6,\r | |
696 | EfiCacheAssociativity8Way = 7,\r | |
ab654bfd | 697 | EfiCacheAssociativity16Way = 8,\r |
698 | EfiCacheAssociativity24Way = 9\r | |
79964ac8 | 699 | } EFI_CACHE_ASSOCIATIVITY_DATA;\r |
700 | \r | |
701 | typedef struct {\r | |
9205b2d7 | 702 | UINT32 Level :3;\r |
703 | UINT32 Socketed :1;\r | |
704 | UINT32 Reserved2 :1;\r | |
705 | UINT32 Location :2;\r | |
706 | UINT32 Enable :1;\r | |
707 | UINT32 OperationalMode :2;\r | |
708 | UINT32 Reserved1 :22;\r | |
79964ac8 | 709 | } EFI_CACHE_CONFIGURATION_DATA;\r |
710 | \r | |
9205b2d7 | 711 | #define EFI_CACHE_L1 1\r |
712 | #define EFI_CACHE_L2 2\r | |
713 | #define EFI_CACHE_L3 3\r | |
714 | #define EFI_CACHE_L4 4\r | |
715 | #define EFI_CACHE_LMAX EFI_CACHE_L4\r | |
79964ac8 | 716 | \r |
717 | #define EFI_CACHE_SOCKETED 1\r | |
718 | #define EFI_CACHE_NOT_SOCKETED 0\r | |
719 | \r | |
720 | typedef enum {\r | |
721 | EfiCacheInternal = 0,\r | |
722 | EfiCacheExternal = 1,\r | |
723 | EfiCacheReserved = 2,\r | |
724 | EfiCacheUnknown = 3\r | |
725 | } EFI_CACHE_LOCATION;\r | |
726 | \r | |
9205b2d7 | 727 | #define EFI_CACHE_ENABLED 1\r |
728 | #define EFI_CACHE_DISABLED 0\r | |
79964ac8 | 729 | \r |
730 | typedef enum {\r | |
731 | EfiCacheWriteThrough = 0,\r | |
732 | EfiCacheWriteBack = 1,\r | |
733 | EfiCacheDynamicMode = 2,\r | |
734 | EfiCacheUnknownMode = 3\r | |
735 | } EFI_CACHE_OPERATIONAL_MODE;\r | |
736 | \r | |
737 | \r | |
738 | \r | |
739 | typedef enum {\r | |
740 | CacheSizeRecordType = 1,\r | |
741 | MaximumSizeCacheRecordType = 2,\r | |
742 | CacheSpeedRecordType = 3,\r | |
743 | CacheSocketRecordType = 4,\r | |
744 | CacheSramTypeRecordType = 5,\r | |
745 | CacheInstalledSramTypeRecordType = 6,\r | |
746 | CacheErrorTypeRecordType = 7,\r | |
747 | CacheTypeRecordType = 8,\r | |
748 | CacheAssociativityRecordType = 9,\r | |
749 | CacheConfigRecordType = 10\r | |
750 | } EFI_CACHE_VARIABLE_RECORD_TYPE;\r | |
751 | \r | |
752 | \r | |
753 | typedef union {\r | |
9205b2d7 | 754 | EFI_CACHE_SIZE_DATA CacheSize;\r |
755 | EFI_MAXIMUM_CACHE_SIZE_DATA MaximumCacheSize;\r | |
756 | EFI_CACHE_SPEED_DATA CacheSpeed;\r | |
757 | EFI_CACHE_SOCKET_DATA CacheSocket;\r | |
758 | EFI_CACHE_SRAM_TYPE_DATA CacheSramType;\r | |
759 | EFI_CACHE_SRAM_TYPE_DATA CacheInstalledSramType;\r | |
760 | EFI_CACHE_ERROR_TYPE_DATA CacheErrorType;\r | |
761 | EFI_CACHE_TYPE_DATA CacheType;\r | |
762 | EFI_CACHE_ASSOCIATIVITY_DATA CacheAssociativity;\r | |
763 | EFI_CACHE_CONFIGURATION_DATA CacheConfig;\r | |
764 | EFI_CACHE_ASSOCIATION_DATA CacheAssociation;\r | |
79964ac8 | 765 | } EFI_CACHE_VARIABLE_RECORD;\r |
766 | \r | |
767 | typedef struct {\r | |
9205b2d7 | 768 | EFI_SUBCLASS_TYPE1_HEADER DataRecordHeader;\r |
769 | EFI_CACHE_VARIABLE_RECORD VariableRecord;\r | |
79964ac8 | 770 | } EFI_CACHE_DATA_RECORD;\r |
771 | \r | |
772 | #define EFI_MEMORY_SUBCLASS_VERSION 0x0100\r | |
9205b2d7 | 773 | #define EFI_MEMORY_SIZE_RECORD_NUMBER 0x00000001\r |
79964ac8 | 774 | \r |
775 | typedef enum _EFI_MEMORY_REGION_TYPE {\r | |
9205b2d7 | 776 | EfiMemoryRegionMemory = 0x01,\r |
777 | EfiMemoryRegionReserved = 0x02,\r | |
778 | EfiMemoryRegionAcpi = 0x03,\r | |
779 | EfiMemoryRegionNvs = 0x04\r | |
79964ac8 | 780 | } EFI_MEMORY_REGION_TYPE;\r |
781 | \r | |
470d0b27 | 782 | ///\r |
783 | /// This data record refers to the size of a memory region. The regions that are \r | |
784 | /// described can refer to physical memory, memory-mapped I/O, or reserved BIOS memory regions. \r | |
785 | /// The unit of measurement of this data record is in bytes. \r | |
786 | ///\r | |
79964ac8 | 787 | typedef struct {\r |
470d0b27 | 788 | ///\r |
789 | /// A zero-based value that indicates which processor(s) can access the memory region. \r | |
790 | /// A value of 0xFFFF indicates the region is accessible by all processors. \r | |
791 | ///\r | |
9205b2d7 | 792 | UINT32 ProcessorNumber;\r |
470d0b27 | 793 | ///\r |
794 | /// A zero-based value that indicates the starting bus that can access the memory region. \r | |
795 | ///\r | |
9205b2d7 | 796 | UINT16 StartBusNumber;\r |
470d0b27 | 797 | ///\r |
798 | /// A zero-based value that indicates the ending bus that can access the memory region. \r | |
799 | /// A value of 0xFF for a PCI system indicates the region is accessible by all buses and \r | |
800 | /// is global in scope. An example of the EndBusNumber not being 0xFF is a system \r | |
801 | /// with two or more peer-to-host PCI bridges. \r | |
802 | ///\r | |
9205b2d7 | 803 | UINT16 EndBusNumber;\r |
470d0b27 | 804 | ///\r |
805 |