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79964ac8 | 1 | /** @file\r |
9f6f9534 | 2 | Include file for definitions in the Intel Platform Innovation Framework for EFI\r |
d5e821ad | 3 | System Management Mode Core Interface Specification (SMM CIS) version 0.91.\r |
79964ac8 | 4 | \r |
1c2f052d | 5 | Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>\r |
22a69a5e | 6 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
79964ac8 | 7 | \r |
79964ac8 | 8 | **/\r |
9 | \r | |
108854b2 LG |
10 | #ifndef _SMM_CIS_H_\r |
11 | #define _SMM_CIS_H_\r | |
79964ac8 | 12 | \r |
a2bb197e | 13 | //\r |
14 | // Share some common definitions with PI SMM\r | |
15 | //\r | |
16 | #include <Pi/PiSmmCis.h>\r | |
17 | #include <Protocol/SmmCpuIo.h>\r | |
18 | \r | |
79964ac8 | 19 | typedef struct _EFI_SMM_SYSTEM_TABLE EFI_SMM_SYSTEM_TABLE;\r |
79964ac8 | 20 | \r |
79964ac8 | 21 | //\r |
22 | // SMM Base specification constant and types\r | |
23 | //\r | |
79964ac8 | 24 | #define EFI_SMM_SYSTEM_TABLE_REVISION (0 << 16) | (0x09)\r |
25 | \r | |
79964ac8 | 26 | /**\r |
f22f941e | 27 | Allocates pool memory from SMRAM for IA-32, or runtime memory for\r |
79964ac8 | 28 | the Itanium processor family.\r |
29 | \r | |
1c2f052d | 30 | @param PoolType The type of pool to allocate. The only supported type\r |
f22f941e | 31 | is EfiRuntimeServicesData.\r |
79964ac8 | 32 | @param Size The number of bytes to allocate from the pool.\r |
1c2f052d | 33 | @param Buffer A pointer to a pointer to the allocated buffer if the\r |
f22f941e | 34 | call succeeds. Otherwise, undefined.\r |
79964ac8 | 35 | \r |
36 | @retval EFI_SUCCESS The requested number of bytes was allocated.\r | |
37 | @retval EFI_OUT_OF_RESOURCES The pool requested could not be allocated.\r | |
38 | @retval EFI_UNSUPPORTED In runtime.\r | |
77a72512 | 39 | @note Inconsistent with specification here:\r |
1c2f052d | 40 | In Framework Spec, this definition is named EFI_SMM_ALLOCATE_POOL.\r |
27d9ad06 | 41 | To avoid a naming conflict, the definition is renamed.\r |
79964ac8 | 42 | **/\r |
43 | typedef\r | |
44 | EFI_STATUS\r | |
69686d56 | 45 | (EFIAPI *EFI_SMMCORE_ALLOCATE_POOL)(\r |
79964ac8 | 46 | IN EFI_MEMORY_TYPE PoolType,\r |
47 | IN UINTN Size,\r | |
48 | OUT VOID **Buffer\r | |
49 | );\r | |
50 | \r | |
51 | /**\r | |
52 | Returns pool memory to the system.\r | |
53 | \r | |
f22f941e | 54 | @param Buffer The pointer to the buffer to free.\r |
79964ac8 | 55 | \r |
56 | @retval EFI_SUCCESS The memory was returned to the system.\r | |
57 | @retval EFI_INVALID_PARAMETER Buffer was invalid.\r | |
58 | @retval EFI_UNSUPPORTED In runtime.\r | |
77a72512 | 59 | @note Inconsistent with specification here:\r |
1c2f052d LG |
60 | In Framework Spec, this definition is named EFI_SMM_FREE_POOL.\r |
61 | To avoid a naming conflict, the definition is renamed.\r | |
79964ac8 | 62 | **/\r |
63 | typedef\r | |
64 | EFI_STATUS\r | |
69686d56 | 65 | (EFIAPI *EFI_SMMCORE_FREE_POOL)(\r |
79964ac8 | 66 | IN VOID *Buffer\r |
67 | );\r | |
68 | \r | |
69 | /**\r | |
70 | Allocates memory pages from the system.\r | |
71 | \r | |
72 | @param Type The type of allocation to perform.\r | |
f22f941e | 73 | @param MemoryType The only supported type is EfiRuntimeServicesData.\r |
74 | @param NumberofPages The number of contiguous 4 KB pages to allocate.\r | |
79964ac8 | 75 | @param Memory Pointer to a physical address. On input, the way in which\r |
76 | the address is used depends on the value of Type. On output, the address\r | |
77 | is set to the base of the page range that was allocated.\r | |
78 | \r | |
79 | @retval EFI_SUCCESS The requested pages were allocated.\r | |
80 | @retval EFI_OUT_OF_RESOURCES The pages requested could not be allocated.\r | |
81 | @retval EFI_NOT_FOUND The requested pages could not be found.\r | |
82 | @retval EFI_INVALID_PARAMETER Type is not AllocateAnyPages or AllocateMaxAddress\r | |
f22f941e | 83 | or AllocateAddress. Or, MemoryType is in the range EfiMaxMemoryType..0x7FFFFFFF.\r |
77a72512 | 84 | @note Inconsistent with specification here:\r |
1c2f052d | 85 | In the Framework Spec, this definition is named EFI_SMM_ALLOCATE_PAGES.\r |
5259c97d | 86 | To avoid a naming conflict, the definition here is renamed.\r |
79964ac8 | 87 | **/\r |
88 | typedef\r | |
89 | EFI_STATUS\r | |
69686d56 | 90 | (EFIAPI *EFI_SMMCORE_ALLOCATE_PAGES)(\r |
79964ac8 | 91 | IN EFI_ALLOCATE_TYPE Type,\r |
92 | IN EFI_MEMORY_TYPE MemoryType,\r | |
93 | IN UINTN NumberOfPages,\r | |
94 | OUT EFI_PHYSICAL_ADDRESS *Memory\r | |
95 | );\r | |
96 | \r | |
97 | /**\r | |
98 | Frees memory pages for the system.\r | |
99 | \r | |
f22f941e | 100 | @param Memory The base physical address of the pages to be freed.\r |
79964ac8 | 101 | @param NumberOfPages The number of contiguous 4 KB pages to free.\r |
102 | \r | |
103 | @retval EFI_SUCCESS The requested memory pages were freed.\r | |
104 | @retval EFI_INVALID_PARAMETER Memory is not a page-aligned address or NumberOfPages is invalid.\r | |
105 | @retval EFI_NOT_FOUND The requested memory pages were not allocated with SmmAllocatePages().\r | |
1c2f052d | 106 | \r |
77a72512 | 107 | @note Inconsistent with specification here:\r |
1c2f052d | 108 | In the Framework Spec, this definition is named EFI_SMM_FREE_PAGES.\r |
5259c97d | 109 | To avoid a naming conflict, the definition here is renamed.\r |
79964ac8 | 110 | **/\r |
111 | typedef\r | |
112 | EFI_STATUS\r | |
69686d56 | 113 | (EFIAPI *EFI_SMMCORE_FREE_PAGES)(\r |
79964ac8 | 114 | IN EFI_PHYSICAL_ADDRESS Memory,\r |
115 | IN UINTN NumberOfPages\r | |
116 | );\r | |
b6d47a83 | 117 | \r |
470d0b27 | 118 | ///\r |
119 | /// The processor save-state information for IA-32 processors. This information is important in that the\r | |
120 | /// SMM drivers may need to ascertain the state of the processor before invoking the SMI.\r | |
121 | ///\r | |
79964ac8 | 122 | typedef struct {\r |
470d0b27 | 123 | ///\r |
124 | /// Reserved for future processors. As such, software should not attempt to interpret or\r | |
125 | /// write to this region.\r | |
126 | ///\r | |
79964ac8 | 127 | UINT8 Reserved1[248];\r |
470d0b27 | 128 | ///\r |
129 | /// The location of the processor SMBASE, which is the location where the processor\r | |
130 | /// will pass control upon receipt of an SMI.\r | |
131 | ///\r | |
79964ac8 | 132 | UINT32 SMBASE;\r |
470d0b27 | 133 | ///\r |
134 | /// The revision of the SMM save state. This value is set by the processor.\r | |
135 | ///\r | |
79964ac8 | 136 | UINT32 SMMRevId;\r |
470d0b27 | 137 | ///\r |
138 | /// The value of the I/O restart field. Allows for restarting an in-process I/O instruction.\r | |
139 | ///\r | |
79964ac8 | 140 | UINT16 IORestart;\r |
470d0b27 | 141 | ///\r |
142 | /// Describes behavior that should be commenced in response to a halt instruction.\r | |
143 | ///\r | |
79964ac8 | 144 | UINT16 AutoHALTRestart;\r |
470d0b27 | 145 | ///\r |
146 | /// Reserved for future processors. As such, software should not attempt to interpret or\r | |
147 | /// write to this region.\r | |
148 | ///\r | |
79964ac8 | 149 | UINT8 Reserved2[164];\r |
470d0b27 | 150 | \r |
151 | //\r | |
1c2f052d | 152 | // Registers in IA-32 processors.\r |
470d0b27 | 153 | //\r |
79964ac8 | 154 | UINT32 ES;\r |
155 | UINT32 CS;\r | |
156 | UINT32 SS;\r | |
157 | UINT32 DS;\r | |
158 | UINT32 FS;\r | |
159 | UINT32 GS;\r | |
160 | UINT32 LDTBase;\r | |
161 | UINT32 TR;\r | |
162 | UINT32 DR7;\r | |
163 | UINT32 DR6;\r | |
164 | UINT32 EAX;\r | |
165 | UINT32 ECX;\r | |
166 | UINT32 EDX;\r | |
167 | UINT32 EBX;\r | |
168 | UINT32 ESP;\r | |
169 | UINT32 EBP;\r | |
170 | UINT32 ESI;\r | |
171 | UINT32 EDI;\r | |
172 | UINT32 EIP;\r | |
173 | UINT32 EFLAGS;\r | |
174 | UINT32 CR3;\r | |
175 | UINT32 CR0;\r | |
176 | } EFI_SMI_CPU_SAVE_STATE;\r | |
177 | \r | |
470d0b27 | 178 | ///\r |
179 | /// The processor save-state information for the Itanium processor family. This information is\r | |
180 | /// important in that the SMM drivers may need to ascertain the state of the processor before invoking\r | |
181 | /// the PMI. This structure is mandatory and must be 512 byte aligned.\r | |
1c2f052d | 182 | ///\r |
79964ac8 | 183 | typedef struct {\r |
184 | UINT64 reserved;\r | |
185 | UINT64 r1;\r | |
186 | UINT64 r2;\r | |
187 | UINT64 r3;\r | |
188 | UINT64 r4;\r | |
189 | UINT64 r5;\r | |
190 | UINT64 r6;\r | |
191 | UINT64 r7;\r | |
192 | UINT64 r8;\r | |
193 | UINT64 r9;\r | |
194 | UINT64 r10;\r | |
195 | UINT64 r11;\r | |
196 | UINT64 r12;\r | |
197 | UINT64 r13;\r | |
198 | UINT64 r14;\r | |
199 | UINT64 r15;\r | |
200 | UINT64 r16;\r | |
201 | UINT64 r17;\r | |
202 | UINT64 r18;\r | |
203 | UINT64 r19;\r | |
204 | UINT64 r20;\r | |
205 | UINT64 r21;\r | |
206 | UINT64 r22;\r | |
207 | UINT64 r23;\r | |
208 | UINT64 r24;\r | |
209 | UINT64 r25;\r | |
210 | UINT64 r26;\r | |
211 | UINT64 r27;\r | |
212 | UINT64 r28;\r | |
213 | UINT64 r29;\r | |
214 | UINT64 r30;\r | |
215 | UINT64 r31;\r | |
216 | \r | |
217 | UINT64 pr;\r | |
218 | \r | |
219 | UINT64 b0;\r | |
220 | UINT64 b1;\r | |
221 | UINT64 b2;\r | |
222 | UINT64 b3;\r | |
223 | UINT64 b4;\r | |
224 | UINT64 b5;\r | |
225 | UINT64 b6;\r | |
226 | UINT64 b7;\r | |
227 | \r | |
228 | // application registers\r | |
229 | UINT64 ar_rsc;\r | |
230 | UINT64 ar_bsp;\r | |
231 | UINT64 ar_bspstore;\r | |
232 | UINT64 ar_rnat;\r | |
233 | \r | |
234 | UINT64 ar_fcr;\r | |
235 | \r | |
236 | UINT64 ar_eflag;\r | |
237 | UINT64 ar_csd;\r | |
238 | UINT64 ar_ssd;\r | |
239 | UINT64 ar_cflg;\r | |
240 | UINT64 ar_fsr;\r | |
241 | UINT64 ar_fir;\r | |
242 | UINT64 ar_fdr;\r | |
243 | \r | |
244 | UINT64 ar_ccv;\r | |
245 | \r | |
246 | UINT64 ar_unat;\r | |
247 | \r | |
248 | UINT64 ar_fpsr;\r | |
249 | \r | |
250 | UINT64 ar_pfs;\r | |
251 | UINT64 ar_lc;\r | |
252 | UINT64 ar_ec;\r | |
253 | \r | |
254 | // control registers\r | |
255 | UINT64 cr_dcr;\r | |
256 | UINT64 cr_itm;\r | |
257 | UINT64 cr_iva;\r | |
258 | UINT64 cr_pta;\r | |
259 | UINT64 cr_ipsr;\r | |
260 | UINT64 cr_isr;\r | |
261 | UINT64 cr_iip;\r | |
262 | UINT64 cr_ifa;\r | |
263 | UINT64 cr_itir;\r | |
264 | UINT64 cr_iipa;\r | |
265 | UINT64 cr_ifs;\r | |
266 | UINT64 cr_iim;\r | |
267 | UINT64 cr_iha;\r | |
268 | \r | |
269 | // debug registers\r | |
270 | UINT64 dbr0;\r | |
271 | UINT64 dbr1;\r | |
272 | UINT64 dbr2;\r | |
273 | UINT64 dbr3;\r | |
274 | UINT64 dbr4;\r | |
275 | UINT64 dbr5;\r | |
276 | UINT64 dbr6;\r | |
277 | UINT64 dbr7;\r | |
278 | \r | |
279 | UINT64 ibr0;\r | |
280 | UINT64 ibr1;\r | |
281 | UINT64 ibr2;\r | |
282 | UINT64 ibr3;\r | |
283 | UINT64 ibr4;\r | |
284 | UINT64 ibr5;\r | |
285 | UINT64 ibr6;\r | |
286 | UINT64 ibr7;\r | |
287 | \r | |
288 | // virtual registers\r | |
289 | UINT64 int_nat; // nat bits for R1-R31\r | |
290 | \r | |
291 | } EFI_PMI_SYSTEM_CONTEXT;\r | |
292 | \r | |
470d0b27 | 293 | ///\r |
294 | /// The processor save-state information for IA-32 and Itanium processors. This information is\r | |
295 | /// important in that the SMM drivers may need to ascertain the state of the processor before invoking\r | |
296 | /// the SMI or PMI.\r | |
297 | ///\r | |
79964ac8 | 298 | typedef union {\r |
470d0b27 | 299 | ///\r |
1c2f052d | 300 | /// The processor save-state information for IA-32 processors.\r |
470d0b27 | 301 | ///\r |
79964ac8 | 302 | EFI_SMI_CPU_SAVE_STATE Ia32SaveState;\r |
470d0b27 | 303 | ///\r |
6ac6f987 | 304 | /// Note: Inconsistency with the Framework SMM CIS spec - Itanium save state not included.\r |
305 | ///\r | |
470d0b27 | 306 | /// The processor save-state information for Itanium processors.\r |
307 | ///\r | |
6ac6f987 | 308 | /// EFI_PMI_SYSTEM_CONTEXT ItaniumSaveState;\r |
79964ac8 | 309 | } EFI_SMM_CPU_SAVE_STATE;\r |
310 | \r | |
470d0b27 | 311 | ///\r |
312 | /// The optional floating point save-state information for IA-32 processors. If the optional floating\r | |
313 | /// point save is indicated for any handler, the following data structure must be preserved.\r | |
314 | ///\r | |
79964ac8 | 315 | typedef struct {\r |
316 | UINT16 Fcw;\r | |
317 | UINT16 Fsw;\r | |
318 | UINT16 Ftw;\r | |
319 | UINT16 Opcode;\r | |
320 | UINT32 Eip;\r | |
321 | UINT16 Cs;\r | |
322 | UINT16 Rsvd1;\r | |
323 | UINT32 DataOffset;\r | |
324 | UINT16 Ds;\r | |
325 | UINT8 Rsvd2[10];\r | |
326 | UINT8 St0Mm0[10], Rsvd3[6];\r | |
327 | UINT8 St0Mm1[10], Rsvd4[6];\r | |
328 | UINT8 St0Mm2[10], Rsvd5[6];\r | |
329 | UINT8 St0Mm3[10], Rsvd6[6];\r | |
330 | UINT8 St0Mm4[10], Rsvd7[6];\r | |
331 | UINT8 St0Mm5[10], Rsvd8[6];\r | |
332 | UINT8 St0Mm6[10], Rsvd9[6];\r | |
333 | UINT8 St0Mm7[10], Rsvd10[6];\r | |
334 | UINT8 Rsvd11[22*16];\r | |
335 | } EFI_SMI_OPTIONAL_FPSAVE_STATE;\r | |
336 | \r | |
470d0b27 | 337 | ///\r |
338 | /// The optional floating point save-state information for the Itanium processor family. If the optional\r | |
1c2f052d LG |
339 | /// floating point save is indicated for any handler, then this data structure must be preserved.\r |
340 | ///\r | |
79964ac8 | 341 | typedef struct {\r |
342 | UINT64 f2[2];\r | |
343 | UINT64 f3[2];\r | |
344 | UINT64 f4[2];\r | |
345 | UINT64 f5[2];\r | |
346 | UINT64 f6[2];\r | |
347 | UINT64 f7[2];\r | |
348 | UINT64 f8[2];\r | |
349 | UINT64 f9[2];\r | |
350 | UINT64 f10[2];\r | |
351 | UINT64 f11[2];\r | |
352 | UINT64 f12[2];\r | |
353 | UINT64 f13[2];\r | |
354 | UINT64 f14[2];\r | |
355 | UINT64 f15[2];\r | |
356 | UINT64 f16[2];\r | |
357 | UINT64 f17[2];\r | |
358 | UINT64 f18[2];\r | |
359 | UINT64 f19[2];\r | |
360 | UINT64 f20[2];\r | |
361 | UINT64 f21[2];\r | |
362 | UINT64 f22[2];\r | |
363 | UINT64 f23[2];\r | |
364 | UINT64 f24[2];\r | |
365 | UINT64 f25[2];\r | |
366 | UINT64 f26[2];\r | |
367 | UINT64 f27[2];\r | |
368 | UINT64 f28[2];\r | |
369 | UINT64 f29[2];\r | |
370 | UINT64 f30[2];\r | |
371 | UINT64 f31[2];\r | |
372 | } EFI_PMI_OPTIONAL_FLOATING_POINT_CONTEXT;\r | |
373 | \r | |
470d0b27 | 374 | ///\r |
375 | /// The processor save-state information for IA-32 and Itanium processors. If the optional floating\r | |
376 | /// point save is indicated for any handler, then this data structure must be preserved.\r | |
377 | ///\r | |
79964ac8 | 378 | typedef union {\r |
1c2f052d LG |
379 | ///\r |
380 | /// The optional floating point save-state information for IA-32 processors.\r | |
470d0b27 | 381 | ///\r |
79964ac8 | 382 | EFI_SMI_OPTIONAL_FPSAVE_STATE Ia32FpSave;\r |
470d0b27 | 383 | ///\r |
1c2f052d | 384 | /// The optional floating point save-state information for Itanium processors.\r |
470d0b27 | 385 | ///\r |
79964ac8 | 386 | EFI_PMI_OPTIONAL_FLOATING_POINT_CONTEXT ItaniumFpSave;\r |
387 | } EFI_SMM_FLOATING_POINT_SAVE_STATE;\r | |
388 | \r | |
389 | /**\r | |
390 | This function is the main entry point for an SMM handler dispatch\r | |
391 | or communicate-based callback.\r | |
392 | \r | |
393 | @param SmmImageHandle A unique value returned by the SMM infrastructure\r | |
394 | in response to registration for a communicate-based callback or dispatch.\r | |
395 | @param CommunicationBuffer\r | |
396 | An optional buffer that will be populated\r | |
397 | by the SMM infrastructure in response to a non-SMM agent (preboot or runtime)\r | |
398 | invoking the EFI_SMM_BASE_PROTOCOL.Communicate() service.\r | |
399 | @param SourceSize If CommunicationBuffer is non-NULL, this field\r | |
400 | indicates the size of the data payload in this buffer.\r | |
401 | \r | |
402 | @return Status Code\r | |
403 | \r | |
404 | **/\r | |
405 | typedef\r | |
406 | EFI_STATUS\r | |
69686d56 | 407 | (EFIAPI *EFI_SMM_HANDLER_ENTRY_POINT)(\r |
79964ac8 | 408 | IN EFI_HANDLE SmmImageHandle,\r |
409 | IN OUT VOID *CommunicationBuffer OPTIONAL,\r | |
410 | IN OUT UINTN *SourceSize OPTIONAL\r | |
411 | );\r | |
412 | \r | |
413 | /**\r | |
414 | The SmmInstallConfigurationTable() function is used to maintain the list\r | |
415 | of configuration tables that are stored in the System Management System\r | |
416 | Table. The list is stored as an array of (GUID, Pointer) pairs. The list\r | |
417 | must be allocated from pool memory with PoolType set to EfiRuntimeServicesData.\r | |
418 | \r | |
419 | @param SystemTable A pointer to the SMM System Table.\r | |
420 | @param Guid A pointer to the GUID for the entry to add, update, or remove.\r | |
421 | @param Table A pointer to the buffer of the table to add.\r | |
422 | @param TableSize The size of the table to install.\r | |
423 | \r | |
424 | @retval EFI_SUCCESS The (Guid, Table) pair was added, updated, or removed.\r | |
425 | @retval EFI_INVALID_PARAMETER Guid is not valid.\r | |
426 | @retval EFI_NOT_FOUND An attempt was made to delete a non-existent entry.\r | |
427 | @retval EFI_OUT_OF_RESOURCES There is not enough memory available to complete the operation.\r | |
428 | \r | |
429 | **/\r | |
430 | typedef\r | |
431 | EFI_STATUS\r | |
69686d56 | 432 | (EFIAPI *EFI_SMM_INSTALL_CONFIGURATION_TABLE)(\r |
79964ac8 | 433 | IN EFI_SMM_SYSTEM_TABLE *SystemTable,\r |
434 | IN EFI_GUID *Guid,\r | |
435 | IN VOID *Table,\r | |
436 | IN UINTN TableSize\r | |
437 | );\r | |
438 | \r | |
439 | //\r | |
440 | // System Management System Table (SMST)\r | |
441 | //\r | |
442 | struct _EFI_SMM_SYSTEM_TABLE {\r | |
470d0b27 | 443 | ///\r |
1c2f052d | 444 | /// The table header for the System Management System Table (SMST).\r |
470d0b27 | 445 | ///\r |
79964ac8 | 446 | EFI_TABLE_HEADER Hdr;\r |
447 | \r | |
470d0b27 | 448 | ///\r |
449 | /// A pointer to a NULL-terminated Unicode string containing the vendor name. It is\r | |
450 | /// permissible for this pointer to be NULL.\r | |
451 | ///\r | |
79964ac8 | 452 | CHAR16 *SmmFirmwareVendor;\r |
470d0b27 | 453 | ///\r |
454 | /// The particular revision of the firmware.\r | |
455 | ///\r | |
79964ac8 | 456 | UINT32 SmmFirmwareRevision;\r |
457 | \r | |
470d0b27 | 458 | ///\r |
1c2f052d | 459 | /// Adds, updates, or removes a configuration table entry from the SMST.\r |
470d0b27 | 460 | ///\r |
79964ac8 | 461 | EFI_SMM_INSTALL_CONFIGURATION_TABLE SmmInstallConfigurationTable;\r |
462 | \r | |
463 | //\r | |
464 | // I/O Services\r | |
465 | //\r | |
470d0b27 | 466 | ///\r |
1c2f052d | 467 | /// A GUID that designates the particular CPU I/O services.\r |
470d0b27 | 468 | ///\r |
79964ac8 | 469 | EFI_GUID EfiSmmCpuIoGuid;\r |
470d0b27 | 470 | ///\r |
471 | /// Provides the basic memory and I/O interfaces that are used to abstract accesses to\r | |
472 | /// devices.\r | |
473 | ///\r | |
79964ac8 | 474 | EFI_SMM_CPU_IO_INTERFACE SmmIo;\r |
475 | \r | |
476 | //\r | |
477 | // Runtime memory service\r | |
478 | //\r | |
470d0b27 | 479 | ///\r |
18d7ae2e | 480 | ///\r |
470d0b27 | 481 | /// Allocates pool memory from SMRAM for IA-32 or runtime memory for the\r |
482 | /// Itanium processor family.\r | |
483 | ///\r | |
79964ac8 | 484 | EFI_SMMCORE_ALLOCATE_POOL SmmAllocatePool;\r |
470d0b27 | 485 | ///\r |
1c2f052d | 486 | /// Returns pool memory to the system.\r |
470d0b27 | 487 | ///\r |
79964ac8 | 488 | EFI_SMMCORE_FREE_POOL SmmFreePool;\r |
470d0b27 | 489 | ///\r |
1c2f052d | 490 | /// Allocates memory pages from the system.\r |
470d0b27 | 491 | ///\r |
79964ac8 | 492 | EFI_SMMCORE_ALLOCATE_PAGES SmmAllocatePages;\r |
470d0b27 | 493 | ///\r |
494 | /// Frees memory pages for the system.\r | |
495 | ///\r | |
79964ac8 | 496 | EFI_SMMCORE_FREE_PAGES SmmFreePages;\r |
497 | \r | |
498 | //\r | |
499 | // MP service\r | |
500 | //\r | |
1c2f052d | 501 | \r |
f22f941e | 502 | /// Inconsistent with specification here:\r |
1c2f052d | 503 | /// In Framework Spec, this definition does not exist. This method is introduced in PI1.1 specification for\r |
f22f941e | 504 | /// the implementation needed.\r |
79964ac8 | 505 | EFI_SMM_STARTUP_THIS_AP SmmStartupThisAp;\r |
506 | \r | |
507 | //\r | |
508 | // CPU information records\r | |
509 | //\r | |
470d0b27 | 510 | ///\r |
511 | /// A 1-relative number between 1 and the NumberOfCpus field. This field designates\r | |
512 | /// which processor is executing the SMM infrastructure. This number also serves as an\r | |
513 | /// index into the CpuSaveState and CpuOptionalFloatingPointState\r | |
514 | /// fields.\r | |
515 | ///\r | |
79964ac8 | 516 | UINTN CurrentlyExecutingCpu;\r |
470d0b27 | 517 | ///\r |
518 | /// The number of EFI Configuration Tables in the buffer\r | |
519 | /// SmmConfigurationTable.\r | |
520 | ///\r | |
79964ac8 | 521 | UINTN NumberOfCpus;\r |
470d0b27 | 522 | ///\r |
523 | /// A pointer to the EFI Configuration Tables. The number of entries in the table is\r | |
524 | /// NumberOfTableEntries.\r | |
525 | ///\r | |
79964ac8 | 526 | EFI_SMM_CPU_SAVE_STATE *CpuSaveState;\r |
470d0b27 | 527 | ///\r |
528 | /// A pointer to a catenation of the EFI_SMM_FLOATING_POINT_SAVE_STATE.\r | |
529 | /// The size of this entire table is NumberOfCpus* size of the\r | |
530 | /// EFI_SMM_FLOATING_POINT_SAVE_STATE. These fields are populated only if\r | |
531 | /// there is at least one SMM driver that has registered for a callback with the\r | |
532 | /// FloatingPointSave field in EFI_SMM_BASE_PROTOCOL.RegisterCallback() set to TRUE.\r | |
533 | ///\r | |
79964ac8 | 534 | EFI_SMM_FLOATING_POINT_SAVE_STATE *CpuOptionalFloatingPointState;\r |
535 | \r | |
536 | //\r | |
537 | // Extensibility table\r | |
538 | //\r | |
470d0b27 | 539 | ///\r |
540 | /// The number of EFI Configuration Tables in the buffer\r | |
541 | /// SmmConfigurationTable.\r | |
542 | ///\r | |
79964ac8 | 543 | UINTN NumberOfTableEntries;\r |
470d0b27 | 544 | ///\r |
545 | /// A pointer to the EFI Configuration Tables. The number of entries in the table is\r | |
546 | /// NumberOfTableEntries.\r | |
547 | ///\r | |
79964ac8 | 548 | EFI_CONFIGURATION_TABLE *SmmConfigurationTable;\r |
549 | };\r | |
550 | \r | |
551 | #endif\r |